Design verification #30

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Closed as not planned

Closed as not planned

Design verification#30

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engdoreis

opened on Nov 20, 2025

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This parent task will be used to track the DV effort

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1. engdoreis

   added sub-issues on Nov 21, 2025

   • Top level DV - Create a 1st version of the top env with the existing RTL top #31
   • Verification Strategy details #3
2. engdoreis

   added sub-issues on Dec 8, 2025

   • M2 - Report on Design Verification (DV) Testplan approach, verification strategy #52
   • Import existing OpenTitan block-level DV #53
   • Create Verification plan for top-level #54
   • Include the formal flow developed by OUI #55
   • CVA6-CHERI Core DV - Block-level SV env just for coverage collection #56
   • Agree top level / block level split. #57
   • Decide on instruction generator for CHERI-CVA6 #58
   • Set up functional coverage collection for CVA6 simulation #59
   • CVA6-CHERI Core DV - Block-level ISA coverage #60
   • CVA6-CHERI Core DV - Block-level micro-architectural assertions/functional cov #61
   • Verilator based testbench #64
   • UVM-based testbench running #65
   • DV smoke test creation #66
3. 15 remaining items

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4. jayalp

   removed sub-issues on Dec 10, 2025

   • Agree top level / block level split. #57
   • Decide on instruction generator for CHERI-CVA6 #58
   • Verilator based testbench #64
   • CVA6-CHERI Core DV - Block-level ISA coverage #60
   • UVM-based testbench running #65
   • CVA6-CHERI Core DV - Block-level micro-architectural assertions/functional cov #61
   • DV smoke test creation #66
   • AXI crossbar DV - Top-level preliminary version of AXI scoreboard #68
   • Tag Controller - Block-level DV for V1 #67
   • Run CVA6-CHERI regressions in CI #69
   • M5 - Report on SoC verification status (DV) #70
   • V1 signoffs #71
   • M6 - Report on complete test plans for V1 sign-off #72
   • UART DV - Block-level env to be imported from OT #103
5. engdoreis

   closed this as not plannedon May 1, 2026

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