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@lowRISC

lowRISC

Developing the Silicon Commons

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  1. opentitan opentitan Public

    OpenTitan: Open source silicon root of trust

    SystemVerilog 3.7k 1.1k

  2. ibex ibex Public

    Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

    SystemVerilog 2.1k 819

  3. ibex-demo-system ibex-demo-system Public

    A demo system for Ibex including debug support and some peripherals

    C 101 89

Repositories

Showing 10 of 163 repositories
  • opentitan Public

    OpenTitan: Open source silicon root of trust

    lowRISC/opentitan's past year of commit activity
    SystemVerilog 3,699 Apache-2.0 1,139 1,667 (10 issues need help) 455 Updated Oct 14, 2026
  • mocha Public

    CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.

    lowRISC/mocha's past year of commit activity
    SystemVerilog 42 21 117 17 Updated Oct 14, 2026
  • lowrisc-nix Public

    lowRISC Nix Packages and Environments

    lowRISC/lowrisc-nix's past year of commit activity
    Nix 9 MIT 14 1 1 Updated Oct 14, 2026
  • QuickCheckVEngine Public Forked from CTSRD-CHERI/QuickCheckVEngine

    A RISC-V TestRIG Verification Engine based on QuickCheck

    lowRISC/QuickCheckVEngine's past year of commit activity
    Haskell 0 BSD-2-Clause 13 0 1 Updated Oct 13, 2026
  • TestRIG Public Forked from CTSRD-CHERI/TestRIG

    Testing processors with Random Instruction Generation

    lowRISC/TestRIG's past year of commit activity
    Python 1 23 0 0 Updated Oct 12, 2026
  • ibex Public

    Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)

    lowRISC/ibex's past year of commit activity
    SystemVerilog 2,106 Apache-2.0 818 210 (4 issues need help) 63 Updated Oct 12, 2026
  • dvsim Public

    DVSim is a build and run system written in Python that runs a variety of EDA tool flows

    lowRISC/dvsim's past year of commit activity
    Python 15 Apache-2.0 22 37 5 Updated Oct 9, 2026
  • cheriot-sail Public Forked from CHERIoT-Platform/cheriot-sail

    Sail code model of the CHERIoT ISA

    lowRISC/cheriot-sail's past year of commit activity
    TeX 1 21 0 0 Updated Oct 5, 2026
  • sail-riscv Public Forked from riscv/sail-riscv

    Sail RISC-V model

    lowRISC/sail-riscv's past year of commit activity
    Coq 0 315 0 1 Updated Oct 5, 2026
  • ot-sku Public

    OT SKUs

    lowRISC/ot-sku's past year of commit activity
    Starlark 1 7 4 3 Updated Sep 30, 2026
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