[oharboe]

asap7/tage_update adds to the variety, relevance and fast turnaround of the ORFS tests: generated SRAMs at scale (6 / 40 / 160 macros through AUTO_MEMORIES) on ORFS's default flow settings, the structure of a TAGE branch predictor as in XiangShan, and a size ladder whose 10-minute base variant already shows the effect.

The design is one cycle of the predictor's stage-2 decision, between the TAGE's SRAMs and the main BTB's, and back to the banks the next pc reads. It is readable SystemVerilog read by slang, and the sources cite the XiangShan lines each piece models. README.md describes what the path does as the field of SRAMs grows.

The default variant (medium, 40 macros) and large (160 macros):

	placement	global route congestion	detailed routing
medium
large

cd flow
make DESIGN_CONFIG=./designs/asap7/tage_update/config.mk
make DESIGN_CONFIG=./designs/asap7/tage_update/config.mk FLOW_VARIANT=small
make DESIGN_CONFIG=./designs/asap7/tage_update/config.mk FLOW_VARIANT=large

🤖 Generated with Claude Code

[gemini-code-assist]

Code Review

This pull request introduces the tage_update design, which models one cycle of a TAGE branch predictor's training based on XiangShan's Frontend, including the top-level logic, individual tables, and SRAM models. The review feedback highlights two critical issues: first, the write buffer in tage_table.sv does not preserve FIFO ordering, potentially causing Write-After-Write hazards and simulation X-propagation; second, in tage_update.sv, a lack of hit in any TAGE table results in an incorrect fallback prediction using an invalid entry from table 0 instead of a default prediction.

[oharboe]

@jhkim-pii @maliberty FYI - trying to extract friendly ORFS idiomatic tests that are readable and don't give up domain knowledge representative of real problems in XiangShan with OpenROAD.

[oharboe]

The FakeRAM width fix this design needs is in #4597. It has to be hooked up before tage_update can be added to CI.

With the fix, all three variants have been tested locally on this ORFS master and run through final; the numbers are in the description.

[openroad-ci]

🔍 QoR check

Metrics reflect the PR merge build — i.e. what will land on the target branch.

Commit 2aeae9a · Jenkins build #12 · Baseline: build · View build on dashboard

62 design(s) checked — 0 with regression(s), 0 without a comparable baseline.

[oharboe]

@vvbandeira @maliberty CI snags...

[maliberty]

It fails for me:

gen_memories: FAKERAM_RUN_PY not set and FakeRAM run.py not found.

[oharboe]

The branch predated #4611, which moved FakeRAM in-tree and dropped FAKERAM_RUN_PY; merged master.

On master the design then needs these fixes:

• memories: a slang-uniquified memory module is named for its definition #4658: slang names each memory instance <definition>$<instance path>; those names went into blackboxes.txt, --blackboxed-module ignores them, and synthesis stops at SYNTH_MEMORY_MAX_BITS.
• FakeRAM asap7: pick a column mux factor instead of hardcoding 1 #4659: FakeRAM builds the 512x17 SRAM 2.28 x 166.6 um (column mux factor 1): MPL-0065.
• FakeRAM asap7: a macro at least one power-strap pitch wide #4662 (draft, waits for FakeRAM asap7: pick a column mux factor instead of hardcoding 1 #4659): the 64x16 SRAM is then 4.18 um wide, narrower than the M5 strap pitch: PDN-0179.
• AUTO_MEMORIES: the generated macros reach the GDS merge #4660: the GDS merge does not get the generated LEFs: Macro not found in LEF file: mbtb_entry_sram.

With all of them applied, base runs through 6_final.gds: 0 DRC violations, setup WNS -225 ps. tage_update is not in CI; it builds as the fixes land.

#4661 makes the first one a hard stop right after the sources are read, naming the modules, instead of the memory-size error.

[oharboe]

@maliberty fixed problems.

This has been helpful for me, is this something that ORFS/OpenROAD maintainers would find useful?

Possibly something it would be useful to have in CI, but certainly useful in my case for more specialized testing.

[maliberty]

make DESIGN_CONFIG=./designs/asap7/tage_update/config.mk fails

Summary:
- Total inferred memories: 61
- Largest single memory instance: 11776 bits (module tage_update)
- Total inferred memory bits (all instances): 0
- SYNTH_MEMORY_MAX_BITS: 4096
- Status: FAIL
Error: Synthesized memory size 4096 exceeds SYNTH_MEMORY_MAX_BITS

[oharboe]

TL;DR: tage_update is a test design for the full AUTO_MEMORIES solution. Merge it now, and we can use it for testing as the PRs trickle in. It is not hooked up to CI.

Status: with master merged in, it stops at [ERROR PDN-0179] Unable to repair all channels, fixed by #4662 (open).

To run it today, use bazel-orfs, which carries the open PRs as patches:

git clone https://github.com/The-OpenROAD-Project/bazel-orfs
git clone https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts

cd bazel-orfs
bazelisk build -c opt @openroad//:openroad @yosys//:yosys @sv-elab//src/yosys_plugin:slang.so
B=$PWD/bazel-bin/external

cd ../OpenROAD-flow-scripts
git checkout $(grep -A1 '^orfs.source(' ../bazel-orfs/MODULE.bazel | grep -o '[0-9a-f]\{40\}')
for p in $(sed -n '/^ORFS_PATCHES = \[/,/^\]/p' ../bazel-orfs/orfs_source.bzl | grep -o '[0-9]*-orfs-[^"]*\.patch'); do
  git apply ../bazel-orfs/patches/$p
done
git fetch origin pull/4595/head
git checkout FETCH_HEAD -- flow/designs/asap7/tage_update flow/designs/src/tage_update

cd flow
YOSYS_PLUGIN_PATH=$B/sv-elab+/src/yosys_plugin make DESIGN_CONFIG=./designs/asap7/tage_update/config.mk \
  OPENROAD_EXE=$B/openroad+/openroad YOSYS_EXE=$B/yosys+/yosys

Run that way, it goes through final: 40 SRAM macros, WNS -225.95 ps at the 473 ps clock, 447 s. The worst paths start at s2_pc and end at an SRAM's RW0_addr, as README.md describes.

[oharboe]

@maliberty 🥹 ?