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AUTO_MEMORIES: stop when a module to blackbox is not a black box - #4661
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read_slang's --blackboxed-module ignores a name it does not know. When a name in blackboxes.txt is not a module definition -- slang names a module per instance, `<definition>$<instance path>`, and a detector that reports those names hands read_slang names it never matches -- the memory's behavioral body is synthesized, and the flow says so only later, as a memory over SYNTH_MEMORY_MAX_BITS with no hint of why. After read_slang, every name in blackboxes.txt must now be a module with the blackbox attribute; synthesis stops otherwise, naming the modules. Tested with a design that instances one memory module twice: the definition name passes, the per-instance names and an unknown name stop. The test is skipped without a yosys that has read_slang. The yosys Verilog frontend is not checked: slang is the supported frontend for AUTO_MEMORIES. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
read_slang blackboxes the escaped module `\1d_ram` given `--blackboxed-module 1d_ram`, and yosys then lists it as `\1d_ram`; the check compared the two as they stood and stopped a design whose memory was blackboxed. The listed names now lose yosys's leading backslash before the comparison. The test design gains an escaped memory module. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Code Review
This pull request introduces a validation step to ensure that modules requested to be blackboxed during synthesis are correctly recognized as blackboxes after reading the design sources, preventing silent failures. This is implemented via a new Tcl script check_blackboxed.tcl integrated into the synthesis preamble, and is supported by a comprehensive Python unit test suite. The review feedback suggests optimizing the validation procedure by returning early when no names are provided and improving the robustness of parsing the Yosys output.
Review: return before the select when blackboxes.txt is empty, and trim each line of the module list, skipping empty ones. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Commit 62 design(s) checked — 0 with regression(s), 0 without a comparable baseline. |
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merge conflict |
…box-check Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
fixed |
read_slang's--blackboxed-moduleignores a name it does not know. When a name inblackboxes.txtis not a module definition, the memory's behavioral body is synthesized, and the flow says so only later, as a memory overSYNTH_MEMORY_MAX_BITSwith no hint of why. asap7/tage_update (#4595) hit this with slang's per-instance names,<definition>$<instance path>.After
read_slang, every name inblackboxes.txtmust now be a module with the blackbox attribute; synthesis stops otherwise, naming the modules. The test reads a design that instances one memory module twice: the definition name passes, the per-instance names and an unknown name stop. It is skipped without a yosys that hasread_slang. The yosys Verilog frontend is not checked: slang is the supported frontend for AUTO_MEMORIES.Interacts with #4650: this reads names through
auto_memories_blackboxes; onceblackboxes.txtcarries an area column, that proc takes the first column. Whichever lands second rebases.🤖 Generated with Claude Code