Issues

• [lc_ctrl] Documentation on lc_hw_debug_clr_o

  Component:RTLIP:lc_ctrl
  lowRISC/opentitan#31776 · Filter by author mohammedkhalid-lr opened on Oct 16, 2026
  1

  

• [dv,lc_ctrl] Alert timeout error

  lowRISC/opentitan#31770 · Filter by author mohammedkhalid-lr opened on Oct 16, 2026
  

• [reggen,i3c] Export reinit only for registers with external storage

  IP:i3cTool:reggenType:Cleanup
  lowRISC/opentitan#31764 · Filter by author andreaskurth opened on Oct 16, 2026

• [test-triage] chip_sw_spi_device_pass_through_collision fails on Earl Grey and Darjeeling

  Component:ChipLevelTestComponent:DarjeelingComponent:DVComponent:TestTriageIP:spi_deviceTOP:earlgrey
  lowRISC/opentitan#31763 · Filter by author andreaskurth opened on Oct 16, 2026

• [i3c] Open points in IP top level

  IP:i3c
  lowRISC/opentitan#31762 · Filter by author glaserf opened on Oct 15, 2026

• [dv,alert_agent] Alert and ping in the same cycle: genuine alert lost, ping can time out

  Component:DV
  lowRISC/opentitan#31755 · Filter by author andreaskurth opened on Oct 14, 2026

• [i3c,lint] Reduce coding-style lint waivers

  IP:i3c
  lowRISC/opentitan#31751 · Filter by author andreaskurth opened on Oct 14, 2026

• [otbn, doc] MAI Spec Potential Ambiguities/ Gaps

  Component:DocIP:otbn
  lowRISC/opentitan#31750 · Filter by author victornwaliLowRISC opened on Oct 14, 2026
  3

  

• [keymgr_dpe,dv] Implement Load root key op in blocklevel dv

  IP:keymgr_dpe
  lowRISC/opentitan#31746 · Filter by author rroth-lowrisc opened on Oct 14, 2026
  

• [CHERIoT,rv_core_ibex,dv] Test tag alignment with PipeLine=1

  lowRISC/opentitan#31745 · Filter by author andreaskurth opened on Oct 14, 2026

• [dv,cip_lib] Race in shadow_reg_errors_with_csr_rw on regwen-gated shadowed registers

  Component:DV
  lowRISC/opentitan#31743 · Filter by author andreaskurth opened on Oct 14, 2026
  1

• [rv_core_ibex,cheriot_mem_sys] LC gate can retract a held core request

  lowRISC/opentitan#31729 · Filter by author thommythomaso opened on Oct 12, 2026
  

• [cheriot_mem_sys,dv] CoredReqHeld_M fails chip CSR and TL error tests in stub-CPU mode

  lowRISC/opentitan#31728 · Filter by author thommythomaso opened on Oct 12, 2026 · Earlgrey-PROD.M3
  

• [doc] Update Secure Boot spec for Earl Grey 2

  Component:Doc
  lowRISC/opentitan#31713 · Filter by author andreaskurth opened on Oct 11, 2026
  

• [top_earlgrey,dv,conn] Add Earl Grey 2 blocks to the clock, reset and AST memory-config connectivity checks

  Component:DV
  lowRISC/opentitan#31711 · Filter by author andreaskurth opened on Oct 11, 2026

• [top_earlgrey,dv] Normal-sleep chip tests fail with "alert fatal has unexpected signal int error"

  Component:DV
  lowRISC/opentitan#31710 · Filter by author andreaskurth opened on Oct 11, 2026

• [top_earlgrey,ast,lint] Re-enable AST lint

  Component:RTL
  lowRISC/opentitan#31709 · Filter by author andreaskurth opened on Oct 11, 2026

• [top_earlgrey,dv] Re-enable the chip-level memory tests

  Component:DV
  lowRISC/opentitan#31708 · Filter by author andreaskurth opened on Oct 11, 2026

• An all-digital glitch detector tested against the TCHES 2024 "Who Watches the Watchers" attacks — interest for the alert handler?

  lowRISC/opentitan#31705 · Filter by author nn20mm2011-ops opened on Oct 11, 2026

• [entropy_src] Repetition count tests count a phantom zero sample after enable (cutoff C reached after C-1 leading zeros)

  lowRISC/opentitan#31700 · Filter by author vera-rubin opened on Oct 9, 2026

• [i2c] Retry after arbitration loss sends a 5-bit address (bit_index not reset on arbitration abort)

  lowRISC/opentitan#31699 · Filter by author vera-rubin opened on Oct 9, 2026

• [i2c] Queued FMT commands still execute after BUS_TIMEOUT halts the controller

  lowRISC/opentitan#31698 · Filter by author vera-rubin opened on Oct 9, 2026

• [uart] A high pulse shorter than half a bit re-arms break detection

  lowRISC/opentitan#31697 · Filter by author vera-rubin opened on Oct 9, 2026
  1

• [uart] Break detection adds up short lows separated by long idle-high gaps

  lowRISC/opentitan#31696 · Filter by author vera-rubin opened on Oct 9, 2026

• [uart] TX_DONE and STATUS.TXIDLE assert at the start of the STOP bit, one bit time early

  lowRISC/opentitan#31695 · Filter by author vera-rubin opened on Oct 9, 2026
  1