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Reduce flash usage and fix PLL handling after >100 MHz outputs (#65) - #105

Merged

NT7S merged 6 commits into

flash-size-refactor+divby4-fix

Oct 10, 2026

Commits on Oct 6, 2026
- Reduce flash usage without changing the public API
  NT7S
  committed
  51e6650
Commits on Oct 8, 2026
- Reset PLL when a multisynth leaves divide-by-4 mode
  NT7S
  committed
  d052ddd
Commits on Oct 9, 2026
- Re-plan PLL when a <=100 MHz output would need an MS ratio below 8
  NT7S
  committed
  9d086d2
- Issue a single PLL reset when re-planning a PLL
  NT7S
  committed
  34c486c
- Move a <=100 MHz output to the other PLL when its PLL is held
  NT7S
  committed
  b8f7988
Commits on Oct 10, 2026
- Bump version to 2.3.0
  NT7S
  committed
  43c6266