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…k lanes The orfs_asap7 backend read only rows and bits from memories.json and emitted the single-port RAM FakeRAM has always emitted: rd_out, addr_in, we_in, wd_in, clk, ce_in. The module the flow blackboxes has its own port names -- for a firtool memory RW0_clk, RW0_addr, RW0_en, RW0_wmode, RW0_wdata, RW0_rdata and RW0_wmask -- and a liberty view with different pin names is one the netlist cannot link to. So conversion produced a macro nothing could instantiate, for every memory, and the flow did not say so. The macro is now built from the pins the inventory declares. A memory declared as one read-write port maps clock, address, enable, write mode, data in and data out onto the single-port RAM's ports under the module's names; a memory declared with any other port configuration is refused with a message rather than emitted wrong. A memory whose pins the detector synthesized (no port convention) keeps FakeRAM's historical names, so nothing that worked before changes. Write masks. SRAM compilers offer byte or lane write enables, and the memories of real designs use them: coralnpu's two TCMs are 128 bits wide with a byte mask, 16 lanes; XiangShan's firtool memories carry 57-bit lanes (two across 114 bits) and per-bit masks in the branch predictor's tables. FakeRAM had no mask at all. RWPortGroup gains a write mask bus with a lane count; the port creator, liberty exporter (a bus type per mask, setup/hold against the port clock), LEF exporter and the single-port Verilog model (per-lane writes) carry it; MemoryConfig takes `pin_names` and `mask_lanes`; SinglePortRAM counts the lanes among its pins. A memory without a mask emits byte-identically to before: the golden-file flow tests pass unchanged. Pin tracks. FakeRAM sizes a macro from its bit cells and then fails when the pins do not fit the left edge, which a 128x76 memory with 76 mask lanes does. The backend computes the height the pins need, for the column mux factor FakeRAM picks for that memory, and passes the difference as additional_height instead of leaving each macro to fail on its own. test/spsram_mask_test.py covers the declared names and the mask in the liberty and LEF views, the per-lane writes of the Verilog model, a per-bit mask getting a track per pin, a mask that does not divide the word being refused, and a memory declared as separate ports being refused. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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This pull request introduces support for custom pin names and write-mask lanes in single-port RAM generation for the ORFS asap7 backend, updating memory configuration, port creation, and exporters (LEF, Liberty, and Verilog) to handle these features. Feedback suggests adding defensive checks in single_port_pins to prevent potential exceptions when parsing memories.json.
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🔍 QoR checkMetrics reflect the PR merge build — i.e. what will land on the target branch. Commit 62 design(s) checked — 0 with regression(s), 0 without a comparable baseline. |
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AUTO_MEMORIESon asap7 turns each memory into a FakeRAM macro, but the macro always had FakeRAM's own pin names (rd_out,addr_in,we_in,wd_in,clk,ce_in) and no write mask. The module the flow blackboxes has the memory's own names, such as firtool'sRW0_clk,RW0_addr,RW0_en,RW0_wmode,RW0_wdata,RW0_rdataandRW0_wmask. So the liberty view could not link to the netlist, and a masked memory had nothing to map its mask onto.wmaskbus, per-lane writescoralnpu and XiangShan both need masks: coralnpu's two TCMs are byte-masked, and XiangShan's firtool memories carry 57-bit lanes and per-bit masks in the branch predictor's tables.
One commit: FakeRAM asap7 builds the macro from the pins
memories.jsondeclares, write mask lanes included, and grows the macro so every pin gets a track. The height is part of the same change because the extra pins come from the mask lanes.Tests: the new
tools/FakeRAM2.0/test/spsram_mask_test.pychecks the declared names and the mask in the liberty and LEF views, per-lane writes in the Verilog model, a per-bit mask getting a track per pin, that a mask which does not divide the word is refused, and that a memory declared as separate ports is refused. The existing FakeRAM tests, golden-file flow tests included, pass unchanged.🤖 Generated with Claude Code