Fix misaligned stores in the RISC-V vector JIT

[thomasbuilds]

generateProgramVectorRV64 patches instructions into the generated code through uint32_t* pointers, but that code contains compressed instructions, so these addresses are only guaranteed to be 2-byte aligned. With -fsanitize=alignment, randomx-benchmark --verify --jit --softAes on RISC-V with the vector extension reports:

src/jit_compiler_rv64_vector.cpp:363:16: runtime error: store to misaligned address 0x2aaabbec4f9a for type 'uint32_t', which requires 4 byte alignment
src/jit_compiler_rv64_vector.cpp:912:7: runtime error: store to misaligned address 0x2aaabbec4f9e for type 'uint32_t', which requires 4 byte alignment

memcpy through a uint32_t*, as for mx_xor, isn't enough: Clang still assumes 4-byte alignment and emits sw. This uses uint8_t* pointers and memcpy for all of these stores. The generated JIT code is unchanged.