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Fix RISC-V build with GCC 13 and Clang 18/19 - #350
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GCC 14 is the minimal requirement for RISC-V builds |
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yeah forgot about this |
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tevador#350 (an inline-assembly fallback for the Zvkned intrinsics) was closed on 2026-10-14 with "GCC 14 is the minimal requirement for RISC-V builds". C-F3 is therefore decided, not open: the report no longer recommends a fallback. The Clang requirement was wrong: Clang 18.1 and 19.1 declare __riscv_vaesem_vv_u32m1 and __riscv_vaesdm_vv_u32m1 only with -menable-experimental-extensions; Clang 20.1 builds the library and passes the suite under qemu (VLEN 256, Zvkned). README now says GCC 14+ or Clang 20+. The audit's RISC-V builds used GCC 13 with an inline-assembly shim for the two intrinsics. Rebuilt with GCC 14.2 and no shim, the final tree passes the suite on the scalar JIT, at VLEN 128 and with Zvkned at VLEN 256, 512 and 1024, and the C-F2 differential harness gives 204/204 on the scalar JIT and at VLEN 128, 256 and 512. C-F5 (no overflow check in the vector SuperscalarHash buffers) was already fixed with O-4 in round 2; it is no longer listed as a recommendation. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01Mj5ZB66Pd5vxCkgehReFDs
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PR tevador#350 showed that the audit had not reviewed upstream's closed pull requests and issues. They were reviewed (tevador#300-tevador#364 and the recent issues) and the results are in AUDIT_v2_2026-10.md section 8: - tevador#352: the maintainers acknowledged C-F6 (RISC-V soft-AES index 255 at VLEN >= 2048) and declined a per-instruction mask; C-F6 now records this, and the recommendation is a one-time VLEN check. - tevador#336: a maintainer argued against describing the SuperscalarHash generator in full in the docs; ALG-7 and recommendation 4 now say that chapter 6.4 is a proposal and name the alternative. - The same external review found three wrong comments, fixed here: the x86 v2 light-mode template modifies "ma", not "mx"; the RISC-V vector light-mode loop updates mp; v17 is clobbered by vfwcvt into v16. - Upstream's v1.x branch (9b012ab), which Monero runs until the v2 fork, has B-1 and most of the Low fixes. B-1 reproduces there under qemu-aarch64: 6/6 wrong light-mode JIT hashes with the round 1 proof of concept, 0/6 with the patch. Also corrected in the report's bottom line: the large-page leak (E-4) only affected sizes that are not a multiple of the huge page size, and C-F1/C-F2 are not v1-era (they are in the 2026 RISC-V vector JIT). Comment-only code changes; the x86-64 and riscv64 (GCC 14) suites pass. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01Mj5ZB66Pd5vxCkgehReFDs
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aes_hash_rv64_zvkned.cppuses the Zvkned intrinsics__riscv_vaesem_vv_u32m1and__riscv_vaesdm_vv_u32m1. GCC provides them only from version 14, and Clang 18 and 19 only with-menable-experimental-extensionsso RISC-V builds fail with GCC 13 and Clang 18 (Ubuntu 24.04's defaults) and with Clang 19 (Debian 13's default).This PR checks for the intrinsics in CMake. When they're unavailable the two AES helpers use inline assembly for
vaesem.vvandvaesdm.vvinstead so hardware AES still works. Builds with GCC 14+ and Clang 20+ are unchanged.