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tezro: add the SGI Tezro, with the V12 and up to four processors - #409

Draft

jamesbraid wants to merge 67 commits into

techomancer:mainfrom

jamesbraid:tezro

Draft

tezro: add the SGI Tezro, with the V12 and up to four processors#409
jamesbraid wants to merge 67 commits into
techomancer:mainfrom
jamesbraid:tezro

Commits on Oct 30, 2026
- bedrock: add the node I/O, network, crossbar and local-bus blocks
  jamesbraid
  committed
  03a6c6c
- bedrock_pi: add processor control and interrupts
  jamesbraid
  committed
  823fb80
- bedrock_flash: add the Fuel boot flash windows
  jamesbraid
  committed
  d6df118
- xbridge: add the two-head Fuel PCI host bridge
  jamesbraid
  committed
  72651b7
- l1: add the Fuel system controller
  jamesbraid
  committed
  755351c
- ohci: add the Lucent USB host controller and HID boot devices
  jamesbraid
  committed
  2d6f088
- cpu: take code and generation counters from the cache's bus
  jamesbraid
  committed
  901159d
- fuel: add the serial IP35 machine
  jamesbraid
  committed
  21cb05e
- odyssey: hold the refused-push test's slice until the test lets go
  jamesbraid
  committed
  9eb6fa3
- odyssey: let a widget-offset machine host the board
  jamesbraid
  committed
  6eff27b
- ip35: fit the VPro board in the Fuel's graphics slot
  jamesbraid
  committed
  68dd623
- docs: describe the Fuel machine
  jamesbraid
  committed
  0f8267d
- cpu: carry the R10000 family's uncached attribute through mapped accesses
  jamesbraid
  committed
  8a0c9eb
- bedrock_md: add the Fuel memory controller
  jamesbraid
  committed
  30ae76f
- isp1040: add the dual-channel ISP12160 part
  jamesbraid
  committed
  6979525
Commits on Oct 31, 2026
Commits on Nov 1, 2026
- bedrock_pi: let a board name the slots whose processors run
  jamesbraid
  committed
  239a642
- tezro: run every fitted processor
  jamesbraid
  committed
  ec5f8eb
- ip35: hold a processor at the PROM rendezvous and answer from its own PI
  jamesbraid
  committed
  434a54d
Commits on Nov 2, 2026
- tezro: test the one-node reads and the PROM's crossbar check, update the guide
  jamesbraid
  committed
  b2ee636
Commits on Nov 6, 2026
- cpu: add the R16000 parts
  jamesbraid
  committed
  4ea78bc
Commits on Nov 7, 2026
- pci: hold a function's header, interrupt and DMA in one PciFunctionState
  jamesbraid
  committed
  99f25fe
- mace_pci: drop the touched and probed report
  jamesbraid
  committed
  d022ddb
- pci: add the interrupt combiner
  jamesbraid
  committed
  c7b59bb
- pci: add the decode table and BAR runs
  jamesbraid
  committed
  5d7194a
- pci_host: add ByteOrder and the BAR bus device
  jamesbraid
  committed
  44b2a51
- pci: add PciBus
  jamesbraid
  committed
  d5181a1
- mace_pci: own the PCI bus
  jamesbraid
  committed
  3fe2816
- bridge: own the PCI bus
  jamesbraid
  committed
  1a4a578
- bridge: reset a PCI device when Control drops its reset pin
  jamesbraid
  committed
  c1c111e
- pci: split the module into config.rs and function.rs
  jamesbraid
  committed
  b210b7b
- aic7880: put the SCSI targets back on load
  jamesbraid
  committed
  6c42fbc
- pci: rename PciBusDevice to PciFunction
  jamesbraid
  committed
  939c461
- pci: test that a function's load overwrites a used instance
  jamesbraid
  committed
  6c5f4c8
- pci: add a 64-bit memory BAR
  jamesbraid
  committed
  c8d49a2
- docs: describe the PCI layer
  jamesbraid
  committed
  603e2af
- bridge: send type 1 configuration cycles through the 0x028000 aperture
  jamesbraid
  committed
  ef2072b
- pci: read the expansion ROM base register as zero
  jamesbraid
  committed
  ec26604
- pci: log configuration cycles under the pci log module
  jamesbraid
  committed
  7fccb88
- ip30: log Bridge and HEART accesses under the bridge and heart modules
  jamesbraid
  committed
  ce1ac49
- pci: add a PCI-to-PCI bridge function
  jamesbraid
  committed
  b3061f3
- ip30: reach PCI memory through the Bridge's 2 GB window
  jamesbraid
  committed
  8db9c67
- docs: bring the PCI notes up to date and add the PCI plan
  jamesbraid
  committed
  d4304d7
Commits on Nov 8, 2026
- ppmem: give each CPU a cached view of memory
  jamesbraid
  committed
  76a925f
- jitv2: compile no page a CPU's cache holds lines in
  jamesbraid
  committed
  56e2a8c
- cpu: keep valid primary data and secondary lines in the CPU's cached view
  jamesbraid
  committed
  e6754c4
- cpu: keep valid primary instruction lines in the CPU's cached view
  jamesbraid
  committed
  e4a901d
- ip32: retire the POST stack page
  jamesbraid
  committed
  66643f9
- ppmem: let a machine hold cache lines where no memory is mapped yet
  jamesbraid
  committed
  0519fe4
- ip35: let lines stand in the Fuel CPU's bank slots
  jamesbraid
  committed
  1c16d9c
Commits on Nov 9, 2026
- pic: add the PCI host bridge
  jamesbraid
  committed
  4c482ae
- pci: let a function take a whole-dword configuration write
  jamesbraid
  committed
  9293d64
Commits on Nov 10, 2026
- l1: carry a node board's CPU configuration in its board record
  jamesbraid
  committed
  71906b4

Commits

Commits on Oct 30, 2026

Commits on Oct 31, 2026

Commits on Nov 1, 2026

Commits on Nov 2, 2026

Commits on Nov 6, 2026

Commits on Nov 7, 2026

Commits on Nov 8, 2026

Commits on Nov 9, 2026

Commits on Nov 10, 2026