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@pulp-platform

pulp-platform

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  1. Deeploy Deeploy Public

    DNN Compiler for Heterogeneous SoCs

    Python 78 49

  2. carfield carfield Public

    A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

    Tcl 132 37

  3. cheshire cheshire Public

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

    Verilog 372 120

  4. snitch_cluster snitch_cluster Public

    An energy-efficient RISC-V floating-point compute cluster.

    C 149 117

  5. axi axi Public

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog 1.7k 374

  6. ara ara Public

    The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

    C 549 205

Repositories

Showing 10 of 332 repositories
  • croc Public

    A PULP SoC for education, easy to understand and extend with a full flow for a physical design.

    pulp-platform/croc's past year of commit activity
    SystemVerilog 278 138 3 (1 issue needs help) 8 Updated Sep 30, 2026
  • pulp_cluster Public

    The multi-core cluster of a PULP system.

    pulp-platform/pulp_cluster's past year of commit activity
    SystemVerilog 118 35 5 2 Updated Sep 30, 2026
  • artistic Public

    An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders

    pulp-platform/artistic's past year of commit activity
    Python 31 Apache-2.0 6 3 1 Updated Sep 30, 2026
  • softex Public
    pulp-platform/softex's past year of commit activity
    SystemVerilog 18 5 1 0 Updated Sep 30, 2026
  • neureka Public

    2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters

    pulp-platform/neureka's past year of commit activity
    SystemVerilog 40 8 5 9 Updated Sep 30, 2026
  • redmule Public

    GEMM and GEMM-Ops accelerator for PULP systems

    pulp-platform/redmule's past year of commit activity
    SystemVerilog 122 28 3 3 Updated Sep 30, 2026
  • hci Public

    Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores

    pulp-platform/hci's past year of commit activity
    SystemVerilog 17 21 6 2 Updated Sep 30, 2026
  • spatz Public

    Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

    pulp-platform/spatz's past year of commit activity
    C 174 Apache-2.0 53 5 16 Updated Sep 30, 2026
  • mempool Public

    A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.

    pulp-platform/mempool's past year of commit activity
    C 330 Apache-2.0 61 3 6 Updated Sep 30, 2026
  • cheshire Public

    A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

    pulp-platform/cheshire's past year of commit activity
    Verilog 372 120 21 31 Updated Sep 30, 2026