🎓 M.S. student in Computer Engineering at Texas A&M University
🔧 Pre-silicon verification engineer with 3+ years of industry experience across Intel, Siemens EDA, and HPE Aruba Networking
🧠 Researching LLM-driven verification automation, combining generative AI with formal methods
- Intel – Pre-Silicon Verification Engineer Intern (2026)
- Texas A&M University – Graduate Researcher & Teaching Assistant
- Intel – IP Logic Design Engineer (2024–2025)
- Siemens EDA – Design and Verification Engineer (2023–2024)
- HPE Aruba Networking – Verification Engineer (2022–2023)
- University of Costa Rica – Circuit Design Instructor
- LLM-Driven Assertion Generation with Formal Qualification — Python, SystemVerilog, JasperGold
An LLM-agent framework for generating SystemVerilog assertions and using UVM environment. - Functional Verification of MESI Protocol in a Quad-Core Multiprocessor — SystemVerilog, UVM
UVM environment with SVA to verify cache coherence across per-core MESI L1 caches, a shared L2, and memory.
📄 Publication: Harnessing Design History and Machine Learning for Precise Delay Estimation in Open-Source EDA — CONCAPAN XLII, 2024
I'm open to full-time roles starting 2027 and collaborative projects in:
- Design Verification (UVM, SVA, Formal)
- Pre-Silicon Validation & Debug
- Machine Learning / LLMs for Hardware Verification
- Languages: Python, SystemVerilog, C, C++, TCL, Perl, Bash
- Methodologies: UVM, SVA, Functional Coverage, Constrained-Random Verification, Formal Property Verification
- Simulation & Debug: Synopsys VCS/Verdi, Cadence SimVision, Mentor Questa
- Formal & Signoff: Cadence JasperGold (FPV), Synopsys VC SpyGlass CDC
- UCIe, Cache Coherence (MESI), CDC/RDC, Power Intent (UPF), RTL Design
- Linux, Git, Vim, VSCode, JIRA, Large Language Models
📫 Connect with me on LinkedIn
Feel free to reach out for opportunities or collaboration!