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embeddedci 2.13.1, embeddedci-openhtf 2.3.1; host-clock rate tests allow 3% - #43
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…low 3% - embeddedci 2.14.0: Capabilities.scope False on the digital board (#42), DAC waveforms default to the 3.3 V output (#39). - embeddedci-openhtf 2.4.0: its signal phases default to dac_path 3v3 (#39). - e2e: the LA/ADC host-clock rate tests allow 3% instead of 0.5%. Over Wi-Fi the fit scattered to 0.983x/1.009x on a pod whose clock is fine; a wrong rate is off by 5-25%. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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Release PR for the unreleased SDK changes, plus a test fix. Patch versions (the maintainer's preference).
Capabilities.scopeis False on the digital-only board (Capabilities.scope is False on the digital-only board #42); DAC waveforms default to the 3.3 V output (DAC waveforms default to the 3.3 V output, not 5 V #39).signal_generate/signal_generate_phase/loopback_measure_phasedefault todac_path="3v3"(DAC waveforms default to the 3.3 V output, not 5 V #39).HOST_CLOCK_REL) instead of 0.5%. Over Wi-Fi the fit scattered to 0.983x and 1.009x on benchpod-bf123b, whose clock is fine (2/2 over the USB network). Firmware that reports the requested rate instead of the achieved one is off by 5-25%, so 3% still catches that.After merge: tag
embeddedci-v2.13.1andembeddedci-openhtf-v2.3.1, then the MCP 2.13.1 release PR (pin >=2.13.1).🤖 Generated with Claude Code