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RTEMS support - #2392
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Cross-compile AtomVM as an RTEMS application, embed a host-packed
AVM, and boot on SIS. This is the first non-Unix RTOS target besides
the MCU ports, so applications cannot load .avm files from disk.
Keep SMP, JIT, and sockets off until a later BSP has libbsd. CI
caches the sparc/erc32 toolchain and checks {atomvm_rtems_boot,rtems}.
Signed-off-by: Peter M <petermm@gmail.com>
Keep a single RTEMS platform and add the arm/imx7 BSP as a second bring-up target. QEMU -kernel of an ELF leaves r2=0, so the helper raw-loads a patched Linux imx7d-sdb DTB and sets the U-Boot FDT pointer via gdb. CI builds both erc32 and imx7. The imx7 DTB is compiled from a sparse checkout of Linux v6.1, including include/uapi/linux for linux-event-codes.h, avoiding unsupported armhf apt indexes on Noble amd64 runners. Signed-off-by: Peter M <petermm@gmail.com>
Implement the RTEMS peripheral HAL modules and native NIF collections. Wire them into the platform build and atomvmlib archive, document the supported i.MX7 and erc32 behavior, and exercise NIF registration during boot tests. Signed-off-by: Peter M <petermm@gmail.com>
Link rtems-libbsd on arm/imx7, initialize ffec0 with DHCP, and enable BSD socket NIFs with poll-based select. CI covers DHCP, DNS, TCP, a guest echo server, hostfwd on port 8080, and erc32 enotsup. Signed-off-by: Peter M <petermm@gmail.com>
Signed-off-by: Peter M <petermm@gmail.com>
Signed-off-by: Peter M <petermm@gmail.com>
Add a GRiSP 2 board profile using the existing RTEMS 6.2 arm/imx7 BSP and LibBSD toolchain. Package a bootloader-ready image with a validated device tree, pinned DTB sources and hardware smoke tests. Load app.avm from the SD card's FAT partition at boot so applications can be replaced without rebuilding the firmware. Bound file size and discovery time, validate AVM/BEAM container bounds, and fall back to the embedded application when the replacement cannot be loaded. Keep runtime failures visible and use capability names for shared storage and driver code. Complete atom/module table and import teardown, including partially built modules, so failed startup releases memory before fallback. Check failed NIF lookups before accessing their descriptors. Extend the existing imx7 CI job with board artifacts and host regression tests. Document image installation, application replacement and DTB rebuilds. Validation: - Native core tests and the full Erlang test suite passed. - Loader and 256 KiB fallback tests passed under ASan/UBSan; fallback was checked with SMP on and off and detects the original teardown leak. - Native boot, image packaging, DTB override and workflow lint checks passed. - Full RTEMS cross-build and physical board validation remain pending. Signed-off-by: Peter M <petermm@gmail.com>
Upload a commit-qualified ZIP with boot files at its top level and name the debug executable with an .elf extension. Include the barebox boot entry needed to discover the image and device tree, source/build links, and the device-tree sources and license notices. Document SD installation, serial verification, replacing app.avm, and installing the earlier CI artifact layout. Include the guide in the ZIP. Validation: exercised the workflow packaging step against firmware from CI run 33965512962; checked binary identity, U-Boot checksums, boot-entry paths and ZIP integrity. Actionlint, REUSE lint (1510 files), and git diff --check pass. Physical board boot remains unverified. Signed-off-by: Peter M <petermm@gmail.com>
Implement the RTEMS SPI HAL module and native NIF collection over
RTEMS dev/spi/spi.h with auto-registration of i.MX SPI buses. Wire
them into the platform build and atomvmlib archive, document the
supported i.MX7 and GRiSP 2 Pmod SPI behavior, and exercise NIF
registration in boot and board tests.
Non-i.MX targets (SPARC erc32 and ARM RealView) return {error, enotsup}.
Support per-device Chip Select (CS) via the RTEMS GPIO driver.
Validation:
- Host build: spi.erl, test_boot.erl, and test_grisp2.erl compiled cleanly
with +warnings_as_errors and packed into atomvmlib-rtems.avm.
- Test suite: full test-erlang suite passed (0 failures).
- REUSE lint (1538 files) and git diff --check passed.
Signed-off-by: Peter M <petermm@gmail.com>
Extend the RTEMS I2C driver and Erlang HAL module with:
- 10-bit addressing (128..1023) automatically applying I2C_M_TEN.
- Bus probing via i2c:is_device_ready/2,3,4 issuing 0-byte transfers
and translating NACK conditions (ENXIO/EIO) to {error, nack}.
- Bus scanning via i2c:scan/1,3 across 7-bit and 10-bit address ranges
(default 16#08..16#77).
- Atomic multi-message repeated-start transfers via i2c:transfer/2,3.
- Explicit register address width ({mem_add_size, 8 | 16}) via
read_bytes/5 and write_bytes/5.
- Bus retries configuration via {retries, N} in init/1 and open/1.
- Updated test_boot, test_grisp2, and RTEMS documentation.
Validation:
- Compilation: i2c.erl, test_boot.erl, test_grisp2.erl compiled cleanly
and packaged into atomvmlib-rtems.avm, rtems_boot_test.avm, and
rtems_grisp2_test.avm.
- Test suite: full test-erlang passed (0 failures).
- REUSE lint (1538 files) and git diff --check passed.
Signed-off-by: Peter M <petermm@gmail.com>
Extend the RTEMS GPIO driver and Erlang HAL module with:
- Hardware interrupts and notifications:
* Implemented ISR with pending bit check and W1C acknowledgment.
* Lockless ring queue for safe interrupt transfer from hard-ISR to task context.
* Task wakeup via RTEMS_EVENT_0 in sys_poll_events.
* Task-context dispatch of {gpio_interrupt, Pin} notifications.
* Support for trigger modes: rising, falling, both, low, high, none.
* set_int/3, set_int/4, remove_int/2, and attach/detach helpers.
* Process monitoring in gpio_loop with auto-cleanup of interrupts on 'DOWN'
or close/stop.
- Configurable internal pull resistors via IOMUXC pad control:
* Supported modes: up (100k pull-up), down (100k pull-down), floating (disabled).
* Returns {error, enotsup} for unsupported up_down.
- Open-drain output mode (output_od):
* Hardware ODE bit configuration in IOMUXC pad control.
* Dual-layer software high-Z emulation fallback in digital_write.
- Dynamic pinmuxing via gpio:set_pin_mux/2.
- Device tree IRQ and pinctrl-0 resolution with fallback to bank tables.
- Graceful {error, enotsup} handling for non-i.MX targets (ERC32 and RealView).
- Updated test_boot, test_grisp2, and RTEMS documentation.
Validation:
- Compilation: gpio.erl, test_boot.erl, test_grisp2.erl compiled cleanly
and packaged into atomvmlib-rtems.avm, rtems_boot_test.avm, and
rtems_grisp2_test.avm.
- Test suite: full test-erlang passed (0 failures).
- REUSE lint (1538 files) and git diff --check passed with zero errors.
Signed-off-by: Peter M <petermm@gmail.com>
- Support RTEMS 7.0 (main) alongside RTEMS 6.2 in the CMake toolchain - Add ESP32-C3 (riscv/esp32c3db) board option and RV32IMC architecture flags - Scale Init and extra task stack sizes for ESP32-C3 internal 320 KiB SRAM - Add direct-boot flat binary image generation (objcopy -O binary) - Provide flashing target via esptool.py and simulation target via esp-emulator - Add automated CI matrix build and boot test step using esp-emulator - Update RTEMS platform documentation with build, flash, and emulation instructions Signed-off-by: Peter M <petermm@gmail.com>
- Add build-rtems7-toolchain.sh helper to build RSB and RTEMS 7 RISC-V BSP natively - Add Dockerfile.rtems7-esp32c3 providing prebuilt RTEMS 7 RISC-V toolchain and esp-emu - Add docker-build-esp32c3.sh for single-command containerized build and simulation - Document Docker and automated local build workflows in RTEMS platform guide Signed-off-by: Peter M <petermm@gmail.com>
Signed-off-by: Peter M <petermm@gmail.com>
Signed-off-by: Peter M <petermm@gmail.com>
Signed-off-by: Peter M <petermm@gmail.com>
Signed-off-by: Peter M <petermm@gmail.com>
Signed-off-by: Peter M <petermm@gmail.com>
Signed-off-by: Peter M <petermm@gmail.com>
- Add custom LibBSD buildset (grisp2-libbsd.ini) enabling dev_usb_wlan,
dev_wlan_rtwn, net80211, and usr_sbin_wpa_supplicant.
- Update Dockerfile.rtems6-grisp2 to build LibBSD with the GRiSP 2 Wi-Fi
buildset via Waf directly against the ARM RTEMS 6 toolchain.
- Add LibBSD nexus sysinit and module references in rtems_bsd_config.c
for Realtek RTL8188EU USB wireless driver (rtwn_usb), firmware
(rtwn_rtl8188eufw), and 802.11 crypto modules.
- Implement rtems_wifi subsystem (wifi.c/wifi.h) to clone wlan0 over rtwn0,
manage the WPA supplicant watcher task, and track link states.
- Support multi-interface DHCP in dhcpcd.conf across Ethernet and Wi-Fi,
dispatching DHCP lease events to the Wi-Fi subsystem.
- Implement AtomVM network port driver (network_driver.c) translating
{start, [{sta, ...}]} and posting sta_connected, sta_got_ip, and
sta_disconnected events to Erlang processes.
- Add wifi_start/2, wifi_stop/0, and wifi_status/0 NIFs in network_nifs.c
and atomvm_rtems.erl.
- Add high-level Wi-Fi functions in grisp.erl (wifi_connect/2,3,
wifi_disconnect/0, wifi_status/0, wifi_wait/0,1).
- Support automatic boot-time Wi-Fi connection if wpa_supplicant.conf
exists on the SD card (/media/mmcsd-0-0/wpa_supplicant.conf).
- Add example wpa_supplicant.conf and document Wi-Fi setup in INSTALL.md
and README.md.
Signed-off-by: Peter M <petermm@gmail.com>
- Update .github/workflows/rtems-build.yaml to configure and build LibBSD for arm/imx7 using waf and the grisp2-libbsd.ini buildset. - Bump the toolchain cache key to libbsd-wifi to avoid restoring pre-Wi-Fi cached libbsd.a archives. - Include wpa_supplicant.conf.example in the uploaded GRiSP 2 SD-card bundle. Signed-off-by: Peter M <petermm@gmail.com>
The sis (Simple Instruction Simulator) package in RSB 7/rtems-riscv fails to build on aarch64 Linux hosts. It is an obsolete SPARC/ERC32 simulator that is completely unused for ESP32-C3 targets (which use esp-emulator or real hardware). Strip devel/sis-2-1 from 7/rtems-riscv.bset before building the toolchain in Docker and host scripts, and add an optional --platform flag to docker-build-esp32c3.sh. Signed-off-by: Peter M <petermm@gmail.com>
Allow RTEMS_BT on C5 and provide the controller configuration, NPL backend, OS callbacks and stack lifecycle alongside the C3 implementation. Keep one configured connection and compact packet pools within C5's shared SRAM. Make NPL objects reusable, cancel queued callout expirations safely, reject stale timer callbacks and query semaphore counts under the RTEMS core lock. Unwind failed controller startup and use the shared PHY tracking service. Add the advertising/Wi-Fi coexistence test and standalone NPL regressions. Validate sanitizer tests and an independent C5 build without the VHCI API. The hardware checks pass advertising across 24 HTTP requests and Wi-Fi restart, plus controller lifecycle/failure recovery with stable resources. Document the vendor assertion encountered by the extra emulator advertising check and the remaining host/connection validation limits. Signed-off-by: Peter M <petermm@gmail.com>
Add the native ESP-IDF-compatible VHCI interface for attaching a host without starting the advertising smoke test. Keep startup modes mutually exclusive and make repeated starts of the same mode idempotent. Route H4-framed controller events and flattened ACL packets to the host, propagate receive callback results, and wrap outbound ACL data in controller mbufs. Clear host callbacks during teardown and rely on the shared PHY tracking service after the VHCI startup task exits. Cross-link every public VHCI entry point with the pinned controller and rebuild the normal application. Native callback/lifecycle checks pass; complete host, pairing and ACL traffic validation remains future work. Signed-off-by: Peter M <petermm@gmail.com>
Collect undeliverable task-driver messages and dispose them after releasing the process-table lock, allowing resource destructors to safely access processes. Use the existing unsent-message cleanup to release payload references as well as message storage. Add regression coverage for multiple normal messages and term signals whose recipient exits before deferred delivery. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com> (cherry picked from commit 98ffe7b) Signed-off-by: Peter M <petermm@gmail.com>
Expose ble_vhci:init/0, send/3 and close/1 with the API aliases used by esp32-ble-vhci. Run controller lifecycle in a native worker, monitor the owner, and deliver H4 packets through the shared task-driver queue. Validate command/ACL lengths, report transport failures, and shut down on receive overflow. Reinitialize the baseband on each enable so RF works after close/reopen. Add API and Wi-Fi coexistence tests and document validation and SRAM limits. Mailbox tests pass with SMP and no-SMP ASan/UBSan; the C5 API and fault fixture pass in esp-emu, including teardown. Signed-off-by: Peter M <petermm@gmail.com>
Add AVM_ENABLE_BLE_VHCI_NIF, defaulting to OFF and requiring C5 with RTEMS_BT enabled. Only compile and register the VHCI NIF when selected, while retaining the native transport and controller smoke test. Document the option and forward it through the hardware-test build instructions. Verify disabled source/symbol exclusion and undef calls, enabled C5 API/teardown in esp-emu, and invalid configuration rejection. Signed-off-by: Peter M <petermm@gmail.com>
Add RTEMS 7 Board Support Package (riscv/esp32p4db) and AtomVM platform integration for the dual-core RISC-V ESP32-P4 chip: - Add RTEMS 7 kernel patch (0035) and rtems-lwip port patch (0008) for riscv/esp32p4db with SMP enabled. - Generate ROM symbol PROVIDE aliases in esp32p4.rom.ld. - Integrate peripheral drivers: HP GPIO, ADC (channels 0-7 unit 1, 0-5 unit 2), 8-channel LEDC with HP_SYS_CLKRST clock enable, TIMG0/RTC_CNTL WDT, TRNG sys atom (2 cores), flash cache invalidation, and LP_TIMER/PMU sleep registers. - Add zeroed padding in .bsp_start_data preventing false-positive ESP bootloader image detection at flash offsets 0x1000/0x2000 in esp-emu. - Add docker-build-esp32p4.sh convenience build and emulation script. - Add riscv/esp32p4db to GitHub Actions CI matrix with SMP multi-core tests enabled and Wi-Fi conditionally bypassed. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Revision 1 needs different ROM, SRAM, clock and CLIC configuration from revision 3. Select a separate BSP with --rev1, keep v3 as the default, and reject incompatible silicon before selecting a stack or writing RAM. Keep v1 allocations in the lower SRAM bank to preserve ROM data and the upper cache partition. Omit its extra stack allowance so the unified workspace fits without reducing task limits. Generate the ROM table from ESP-IDF release/v6.1 eco0_4 and API exports: python3 .amp/in/p4-v1/generate_rom.py Generate BSP patch 0036 from the applied RTEMS baseline with git diff. Wokwi boot, SMP and peripheral tests pass on v1 and v3. Verify ROM exports, SRAM bounds, cross-revision rejection and CMake mismatch detection. Physical-board validation remains outstanding. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Add RTEMS 7 Board Support Package (riscv/esp32h2db) and AtomVM platform integration for the single-core RISC-V ESP32-H2: - Add RTEMS 7 kernel patch (0037) with rv32imac code, the ilp32 ABI, the unified 320 KiB HP SRAM and the H2's 65 interrupt sources. - Generate ROM symbol PROVIDE aliases in esp32h2.rom.ld. - Calibrate the fixed 96 MHz BBPLL from the 32 MHz crystal through the analog I2C master and select a 96 MHz CPU with a 32 MHz AHB. Leave the CPU on the crystal when calibration does not complete, and keep the flash interface on the crystal because a direct-boot image has no second stage to retime the flash chip. - Integrate peripheral drivers: ADC1 on GPIO1-GPIO5, six 20-bit LEDC channels, I2C, SPI, GPIO, TIMG0/LP watchdog, TRNG, and RTC storage sized for the 4 KiB LP RAM. - Add light sleep through the C6 PMU sleep group with the H2's register offsets, the USB-Serial/JTAG pad suspend and XTAL transition, and LP_AON EXT1 wakeup for GPIO7-GPIO14. - Skip Wi-Fi and lwIP for this part: esp32_chip_info advertises Bluetooth LE only and the network NIF reports a failed port. - Add docker-build-esp32h2.sh, the esp32h2-bsp.ini BSP configuration, Wokwi support and a CI matrix entry without Wi-Fi or SMP. Wokwi and esp-emulator pass the boot smoke test, including flash, NVS and the file system. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
The ESP32-C6 and ESP32-H2 deliver their PLIC channels through the core's machine interrupt enable CSR: mie bit n gates channel n. ESP-IDF raises those bits in its ROM esprv_intc_int_enable(), which programs the PLIC enable and the CPU side together. The BSP programmed only the PLIC. On the H2 that masked every interrupt at the core while the PLIC reported the channel as pending: the SYSTIMER target 0 alarm set INT_RAW, the interrupt matrix routed source 45 to channel 16, the PLIC showed channel 16 in EIP status with priority 15 above a threshold of 1, and the core never took the trap. The scheduler tick therefore never advanced, so timer:sleep/1 never returned. Add patch 0038, which raises the mie bits with the PLIC enable when the facility enables all channels. The H2 boot smoke test now passes on an ESP32-H2-DevKitM-1: the 1 kHz tick advances, timer:sleep(1500) returns after 1529 ms and rtems_task_wake_after(10) after 11 ms. Wokwi boot tests still pass on H2 and C6. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
The platform forced the reported chip size up to 4 MiB, because the ROM's size field is only a default of 2 MiB on parts of every size, so esp:flash_get_size() returned 4194304 on the 2 MiB ESP32-H2 board. NVS and the filesystem were hard-coded at 0x3C0000 and 0x3E0000, which only worked there because the flash addresses wrapped back into the chip. Decode the JEDEC capacity byte from rom_spiflash_legacy_data->chip.device_id, the identification ESP-IDF's bootloader also uses, and keep the 4 MiB layout when the identifier cannot be decoded. Place the 128 KiB NVS and filesystem partitions in the last 256 KiB of the detected size: the 4 MiB offsets stay as they are and a 2 MiB part moves to 0x1C0000 and 0x1E0000. The boot test now checks the low-level flash path at the size-derived NVS offset instead of a hard-coded 0x3C0000, and runs from 1 MiB upwards. flash_fs.c and nvs_driver.c build for every board, so the offsets sit behind accessors that return zero in the non-ESP32 branch of flash_driver.c, like the existing flash stubs there. On the H2 esp:flash_get_size() returns 2097152, NVS and JFFS2 work at the new offsets and the boot smoke test passes. Wokwi boot tests pass on H2, C6 and P4. Building the platform sources with the ESP32 board defines removed confirms the non-ESP32 configuration resolves all of its symbols. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
The RTEMS matrix only ran the boot test on the pinned esp-emulator, which does not model everything the boards do. Run the same test on Wokwi as well, through src/platforms/rtems/tools/run-wokwi.sh, for every ESP32 board in the matrix. Wokwi needs a token, so a small job checks for the WOKWI_CLI_TOKEN secret and the matrix job depends on it: without the secret, such as on pull requests from forks, the tests are skipped instead of failing. The serial log is uploaded when the test fails. The C3, C5, C6, H2, S31 and P4 boot tests pass with this command, and the install-and-run sequence was exercised from a clean HOME. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
The H2 note claimed the flash interface stays on the crystal at 32 MHz. The board disagrees: PCR_MSPI_CONF reads 0x35, so the ROM has already enabled the flash PLL clock and selected PLL_F64M, PCR_MSPI_CLK_CONF is 0 (divider 1) and SPI_MEM_CLKCNT_N is 0, which puts the SPI clock at 64 MHz with the CS setup and hold bits already set. That is the same clock and timing ESP-IDF's second stage selects for its default 64 MHz flash configuration, so neither the BSP comment nor the README should describe a bandwidth trade-off that does not exist. Erase, write and read back pass at 0x1F0000 and in the last sector, 0x1FF000, at that clock, together with the NVS and JFFS2 tests. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Match ESP-IDF voltage, PLL and SRAM execution prerequisites before selecting the H2 clock. Initialize PMU sleep state and restore analog, clock and cache state before returning to flash. Match the application ISA to the rv32imac BSP: omitting atomics changes RTEMS per-CPU layout and corrupts scheduler state during sleep accounting. Use physical GPIO7-14 wake masks and correct SYSTIMER and USB addresses. Allow scheduling latency in the peripheral timer-delivery check without changing VM receive semantics. Document fresh-build requirements and physical two-cycle timer-wakeup validation, with remaining limits. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Initialize chip-specific voltage and regulator ownership before high-speed clock selection, following ESP-IDF calibration and P4 DCDC sequencing. Normalize LP active controls before retaining regulator state for sleep. Suspend external-memory caches with the matching ROM APIs and preserve branch prediction on participating harts. Keep SMP parking and RTC polling SRAM-safe, retain required clocks and PLLs, and restore cache access only after the eFuse completion barrier. Correct P4 GPIO wake registers and pad sequencing, accept GPIO0-15, and cover mask boundaries in the boot test. Document the SDK rebuild requirement and deliberate retained-power differences from full ESP-IDF sleep policy. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Replace retained ACTIVE-state templates with chip-specific RTC/PMU sleep configuration, calibrated timing and bias settings, and XTAL transitions with source-aware PLL and CPU clock restoration. Suspend enabled UARTs and USB Serial/JTAG around clock transitions. Keep cache-off entry and restoration in SRAM/ROM, correct P4 wake status and modern PMU rejection enables, and preserve RTEMS scheduler accounting. Separate pre-entry expiry, hardware rejection and wakeup. Never roll back an unresolved hardware request. Cover tiny-interval expiry and document the retained-register profile and remaining hardware validation limits. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Match ESP-IDF unconditional analog bias setup, calibration delay, and RTC clock initialization on S31: - Replace CPLL calibration settle loop in patch 0030 with IDF’s 10 us ROM delay (ets_delay_us(10)). - Route regi2c writes dynamically across DIG_REG (bit 13), BIAS (bit 4), and MPLL (bit 12), assigning a fresh read-selection mask for each slave. - Unconditionally configure MPLL IR_CAL_EXT_CAP=3, BIAS DREG_1P1=12, and BIAS DREG_1P1_PVT=12 before clock configuration, matching bootloader. - Initialize RTC fast/slow clocks: tune RC_SLOW (SCK_DCAP=128), power RC_FAST in PMU (xpd_fosc=1, pd_osc=0) with 50 us delay, and select RC_FAST and RC_SLOW root clock sources with 3 us and 300 us delays. - Set sleep protect mode, but defer power-domain and memory force releases and modem/sysclk ICG updates to the sleep FSM initializer after its backing policies are configured. - Maintain and document RTEMS’s deliberate fixed-voltage/no-PVT profile with nominal active biases (26). Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Pin the installer and emulator release consistently for local, Docker and CI use. Make local installation consume the shared dependency pins. Document chip-specific emulator coverage and the C6 post-wake eFuse-IDLE stall, also reproduced with the unmodified reference ESP-IDF. Keep the hardware-backend check and scheduler fixture separate without weakening the wake barrier or skipping the failing scenario. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Install complete C6 HP/LP PMU defaults before releasing power-domain forces. Initialize oscillator tuning, RTC sources and calibration storage, power-on o-code, XTAL dividers and ROM-timed PLL settling against ESP-IDF 9a97f6c54ec638111ce55cd36581b3c192f15207. Preserve the BSP ACTIVE/MODEM policies during sleep preparation. Match the XTAL40/CPU160, RC_SLOW/RC_FAST, PVT-off profile while retaining RTEMS scheduler and peripheral ownership and bounded boot-calibration failures. Validate with source-derived PMU/RTC comparisons, seven-BSP strict builds and the C6 peripheral/scheduler fixture. Real timer sleep still stalls at the emulator eFuse-IDLE barrier, as the reference IDF does. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Initialize C3 RTC power, calibrated voltage, PLL and RTC clocks using the reference ESP-IDF startup profile. Preserve RTEMS peripheral ownership. Read the C3 RTC wake-status register directly instead of the ROM getter, matching IDF and fixing timer wake misreported as GPIO after deep sleep. Verified three deep-sleep cycles and the peripheral test on physical C3 revision v0.4. Document startup policy and hardware validation. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Read chip-specific RTC/PMU wake status instead of ROM getters and share IDF source masks and priority between deep and light sleep. Correct P4 timer and P4/S31 EXT1 decoding, report H2 comparator wakes as EXT1, and decode the remaining supported wake sources without enabling them. Keep inline status reads at the cache-off sleep boundary. Add cross-board regression coverage and document the reporting contract. Validated against local ESP-IDF in 8,047,655 modeled cases, compiled all seven BSP configurations, and tested C3 deep sleep and peripheral resumption on physical hardware. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Use raw PMU status so sleep completion is visible without interrupt masking. Match IDF ACTIVE regulator defaults and DCDC force handoff. Retain configured MPLL ownership across sleep attempts: rev3 PMU setup can power the PHY gate without configuring MPLL. Decoding that gate on every attempt incorrectly rejects the second sleep. Validated boot and strict peripheral tests on Wokwi P4 revisions 1.0 and 3.1 with the real sleep backend. BSP patch 0045 requires an SDK rebuild. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
The pinned esp-emulator hangs during timer light sleep on both targets, including with standalone ESP-IDF applications. Skip only these full boot runs on esp-emulator and retain their boot-marker checks on Wokwi. Install esp-emulator separately so fixture-based peripheral tests and Wi-Fi coverage continue to run on it. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Initialize eFuse-qualified PVT control for both P4 revisions after clock setup. Match IDF thresholds, calibration gaps, register ordering and settling delays. Hand voltage regulation to PMU before sleep and restore PVT after clocks and cache on every returning path, including sleep rejection and aborts. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Replace iterative bring-up and fixup patches with ordered topical series so dependency changes are easier to review and regenerate. Keep pinned revisions and resulting source trees unchanged. Preserve original authorship and license notices, and update references to the consolidated topics. Verified identical final Git trees for all three dependencies, full configure/build/install for all seven ESP32 BSPs, and 145 Wi-Fi glue object compilations. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Register a BSP-owned /dev/gpio controller and migrate the ESP32 NIFs from legacy BSP calls and direct register access to the generic API. Preserve pin aliases, output latches, listener callbacks and shared peripheral arbitration; release GPIO resources during deinitialization. Correct the C5 GPIO register layout and matrix selector against ESP-IDF. Extend boot coverage for readback, reconfiguration and pin reclamation. Keep mode/pull updates documented as non-glitch-free. Verified all seven BSP/application builds and Wokwi boot suites, native sanitizer coverage and three physical C5 GPIO test runs. The extended C5 open-drain readback discrepancy also reproduces with standalone ESP-IDF in Wokwi, but passes on hardware; no production test is disabled. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
Share the generic device-API NIF path across GPIO-enabled RTEMS targets. Add an FDT-discovered i.MX controller with polarity, latch preservation, open-drain and interrupt lifecycle support. Preserve configuration and callbacks across reconfiguration and roll back failed changes. Backport unmodified upstream generic GPIO sources when the RTEMS 6 SDK lacks the API, without changing its toolchain, BSP or LibBSD version. Extend GRiSP 2 GPIO tests and document controller semantics and limits. Verified seven ESP32 BSPs and boot/GPIO simulator suites, i.MX7 QEMU boot and real-NIF GPIO tests, synthetic GRiSP 2 LED checks, and native i.MX6/i.MX7 sanitizer coverage. Physical i.MX hardware remains untested; C6 simulator validation excludes its cached optional Wi-Fi archive. Signed-off-by: Peter Madsen-Mygdal <petermm@gmail.com>
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These changes are made under both the "Apache 2.0" and the "GNU Lesser General
Public License 2.1 or later" license terms (dual license).
SPDX-License-Identifier: Apache-2.0 OR LGPL-2.1-or-later