All pull requests

Pull requests

• xtensa: Fixes needed to run ESP-IDF on the esp32 core

  #49·oguzkaganyaglioglu opened Oct 14, 2026·

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• ppc: Extend VLE execution and add e200z4d

  #48·iglooom opened Oct 10, 2026·6 of 9 tasks·

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• infrastructure: use glibc symbol versioning only on glibc

  #47·maribu opened Oct 8, 2026·

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• tcg: fix compilation on musl C lib

  #46·maribu opened Oct 8, 2026·

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• RISCV: integrate translator fixes for Renode reports #958-#962

  #44·carlosqwqqwq opened Sep 7, 2026·

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• xtensa: register FP opcodes for ESP32 and ESP32-S3

  #43·hinaultd opened Aug 25, 2026·

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• xtensa: fix OOB TLB entry access

  #42·hinaultd opened Aug 20, 2026·

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• xtensa: add SALT/SALTU opcodes to esp32/esp32s3 core

  #41·hinaultd opened Aug 19, 2026·

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• riscv: remove obsolete SFENCE.VM branch from gen_system

  #40·carlosqwqqwq opened Aug 11, 2026·

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• riscv: reject scalar M instructions without the M extension

  #39·carlosqwqqwq opened Aug 11, 2026·

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• riscv: gate Zcb instructions on their required extensions

  #38·carlosqwqqwq opened Aug 11, 2026·

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• riscv: accept dual-owner bitmanip instructions with either extension

  #37·carlosqwqqwq opened Aug 11, 2026·

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• riscv: canonicalize malformed half operands for fclass.h

  #36·carlosqwqqwq opened Aug 11, 2026·

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• arm/translate: allow MOV.W Rd,SP (Thumb2 T3) on non-MVE M-profile cores

  #34·Chapoly1305 opened Jul 27, 2026·

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• riscv: Fix pack, packh and packw instructions

  #32·whensun opened Jun 29, 2026·

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• Fix TLB flush to invalidate all 1K sub-pages within 4K page

  #22·garybeihl opened Mar 19, 2026·

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• arm: Fix VFP feature flags for Cortex-A7 and Cortex-A15

  #21·garybeihl opened Mar 19, 2026·

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• Add support for mtvt CSR in RISCV32 architecture

  #17·Maleehaakbar opened Dec 3, 2024·

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• cortex-m7: MPU: Add support for PPB region address handling

  #15·xndcn opened Jul 25, 2024·

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