[oharboe]

Synthesize asap7/aes-block with slang, the better frontend: yosys's own Verilog frontend is on its way out.

• --ignore-timing for the aes sources' #1 delays, as asap7/aes-mbff has, in config.mk and block.mk.
• Fixed DIE_AREA/CORE_AREA for the parent and both blocks, with headroom: aes-block smoke-tests BLOCKS, and at CORE_UTILIZATION its macros sit at the edge of what mpl packs, so a small change in synthesis (here slang's slightly smaller netlist) flips it into MPL-0003.
• The design's purpose, a smoke test of BLOCKS and not of macro placement, stated in config.mk.

Tested: the parent and both blocks build to final with slang.

🤖 Generated with Claude Code

[gemini-code-assist]

Code Review

This pull request switches the synthesis HDL frontend to slang and configures absolute die and core areas for the aes-block design to ensure stable smoke tests. A review comment suggests explicitly checking for aes_sbox using else ifeq instead of a default else block in block.mk to prevent maintenance hazards if new blocks are added in the future.

[oharboe]

@maliberty Switch to slang and lock down die/core area.

Improved QoR from slang caused die area to shrink when using CORE_UTILIZATION, which caused a phantom MPL error.

[openroad-ci]

🔍 QoR check

Metrics reflect the PR merge build — i.e. what will land on the target branch.

Commit e81d764 · Jenkins build #3 · Baseline: build · View build on dashboard

62 design(s) checked — 0 with regression(s), 0 without a comparable baseline.

[maliberty]

CORE_UTILIZATION then gives a core too small for the macros, a phantom MPL-0003 sounds like a bug to fix rather than hide.

[oharboe]

CORE_UTILIZATION then gives a core too small for the macros, a phantom MPL-0003 sounds like a bug to fix rather than hide.

The parent gets smaller, but the macros dont.

But fair point, it could do with some double checking. If it is broken, then it needs an issue and a fix which is in mpl maintainer court.

If not, then it can merge as is.

Either way: requires a maintainers eye to see if this is an mpl bug or not and this PR is a reproduction case.

Please advise.

[oharboe]

@maliberty MPL-0003 here follows the core area, not the frontend: it is a change in die/core area, not a bug introduced by slang.

• The 21 macros with their halos cover 9,792 um² in every run. Macro placement fails while they take more than ~82 % of the core and passes below that; the nearest failing and passing cores differ by one 0.108 um site column.
• At the same core the two netlists agree: read_verilog and slang both fail at 11,875 um² (read_verilog's own CORE_UTILIZATION 47 core) and both pass at 12,028 um² (this PR's sizes).
• CORE_UTILIZATION 47 gives slang 11,857 um² and read_verilog 11,875 um². Both fail in the bazel-orfs build; the 113.801 um die this PR vendors gives 12,028 um², larger than either.

The tiling search giving up at 82 % is mpl's to judge separately; this PR is the reproducer, at any core between 11,875 and 11,922 um².

Synthesis, read_verilog vs slang

module	read_verilog	slang
aes_sbox (x20)	568 cells, 56.32 um²	568 cells, 56.32 um²	identical
aes_rcon	92 cells, 10.59 um²	92 cells, 10.59 um²	identical
aes_key_expand_128	841 cells, 116.67 um²	797 cells, 107.09 um²	-8.2 %
aes_cipher_top own logic	2,813 cells, 370.06 um²	2,759 cells, 366.26 um²	-1.0 %

Where slang differs:

• reg [31:0] w[3:0] in aes_key_expand_128.v: read_verilog warns Replacing memory \w with list of registers and splits it into four $dff; slang keeps one $mem_v2. After memory_map both are the same coarse logic (4 $dff, 4 $mux, 14 $xor), and aes_cipher_top's coarse logic is identical too (209 cells each). The area difference appears in ABC's mapping of the same logic, so it is incidental, not a better netlist.
• The <= #1 delays: read_verilog drops them silently, slang refuses them unless told to (--ignore-timing).

Equivalence, kepler-formal LEC, read_verilog netlist as gold, slang as gate, the parent with its blocks' netlists:

check	flops paired by name	outputs compared	SAT problem	verdict
aes_sbox	0	8	trivial (identical)	no difference
aes_rcon	12	56	trivial (identical)	no difference
whole design	530	1,189	27,209 vars, 71,792 clauses, UNSAT in 0.4 s	no difference
negative control: one NAND2 made a NOR2	530	1,189	SAT in 0.1 s	difference found

No retiming, so both frontends name every flop alike and the netlists go in as synthesised. kepler-formal at acb85ea8, with two carried patches: one logs the problem size, the other (a skip for clock-gated flops) is not enabled here.

Floorplans at this PR's sizes, both after macro placement (odb-debug, headless):

slang	read_verilog

Arms

arm	frontend	sizing	core (um²)	macro placement
A	read_verilog	CORE_UTILIZATION 47	11,874.9	MPL-0003
B	slang	CORE_UTILIZATION 47	11,857.2	MPL-0003
C	slang	this PR	12,028.4	passes
D	read_verilog	this PR	12,028.4	passes
sweep	slang	core upper right 111.2 ... 111.7 um	11,874.9 / 11,916.1 / 11,922.0 / 11,933.8 / 11,975.1 / 11,986.9	fail / fail / fail / pass / pass / pass

One run per point; built with bazel-orfs on ORFS 9c431405.

[oharboe]

@maliberty Good pushback, I did the yak-shave: The-OpenROAD-Project/bazel-orfs#1290.

TL;DR Good to go.

aes-block is the smoke test of BLOCKS, not of macro placement. At CORE_UTILIZATION 47 its macros sit at the edge of what mpl packs (~82 % of the core), so any small change upstream of mpl flips it into MPL-0003. Here that change was slang's slightly smaller netlist; read_verilog at the same setting fails too in the bazel-orfs build. A fixed die/core with headroom keeps mpl out of this test. The purpose is now stated in config.mk.