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flow: Add new public designs #4547
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Merged
maliberty
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The-OpenROAD-Project:master
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The-OpenROAD-Project-staging:secure-register-new-designs
Oct 2, 2026
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| export PLATFORM = asap7 | ||
| export DESIGN_NAME = picorv32 | ||
|
|
||
| export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/picorv32/*.sv)) | ||
| export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc | ||
|
|
||
| export ASAP7_USE_VT = RVT LVT SLVT | ||
|
|
||
| # Synthesis | ||
| export SYNTH_OPERATIONS_ARGS = -booth | ||
| export REMOVE_ABC_BUFFERS = 1 | ||
| export SYNTH_RETIME_MODULES = $(DESIGN_NAME) | ||
| export SYNTH_HDL_FRONTEND = slang | ||
| export LEC_CHECK = 0 | ||
|
|
||
| # Floorplan | ||
| export CORE_UTILIZATION = 60 | ||
| export CORE_ASPECT_RATIO = 1 | ||
| export CORE_MARGIN = 2 | ||
|
|
||
| export TNS_END_PERCENT = 100 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,10 @@ | ||
| set_units -time ps -capacitance fF -resistance kOhm -voltage V -current mA -power pW | ||
| current_design picorv32 | ||
|
|
||
| set clk_period 300 | ||
| set io_delay [expr 0.20 * $clk_period] | ||
| create_clock -name core_clock -period $clk_period [get_ports clk] | ||
| create_clock -name vclk_core -period $clk_period | ||
| set_max_fanout 16 [current_design] | ||
| set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks] | ||
| set_output_delay $io_delay -clock vclk_core [all_outputs] | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,112 @@ | ||
| { | ||
| "synth__canonical_netlist__hash": { | ||
| "value": "e4ff1176ec5b0f3d0fe6b92a6a8dfd6c2f841d84", | ||
| "compare": "==", | ||
| "level": "warning" | ||
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| "synth__design__instance__area__stdcell": { | ||
| "value": 2620.0, | ||
| "compare": "<=" | ||
| }, | ||
| "constraints__clocks__count": { | ||
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| }, | ||
| "placeopt__design__instance__area": { | ||
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| }, | ||
| "placeopt__design__instance__count__stdcell": { | ||
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| }, | ||
| "detailedplace__design__violations": { | ||
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| }, | ||
| "cts__design__instance__count__setup_buffer": { | ||
| "value": 2130, | ||
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| }, | ||
| "cts__design__instance__count__hold_buffer": { | ||
| "value": 2130, | ||
| "compare": "<=" | ||
| }, | ||
| "cts__timing__setup__ws": { | ||
| "value": -429.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__setup__tns": { | ||
| "value": -18000.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__hold__ws": { | ||
| "value": -20.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__hold__tns": { | ||
| "value": -80.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__antenna_diodes_count": { | ||
| "value": 100, | ||
| "compare": "<=" | ||
| }, | ||
| "globalroute__timing__setup__ws": { | ||
| "value": -461.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__setup__tns": { | ||
| "value": -22000.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__hold__ws": { | ||
| "value": -20.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__hold__tns": { | ||
| "value": -80.0, | ||
| "compare": ">=" | ||
| }, | ||
| "detailedroute__route__wirelength": { | ||
| "value": 87408, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__route__drc_errors": { | ||
| "value": 0, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__antenna__violating__nets": { | ||
| "value": 0, | ||
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| }, | ||
| "detailedroute__antenna_diodes_count": { | ||
| "value": 100, | ||
| "compare": "<=" | ||
| }, | ||
| "finish__timing__setup__ws": { | ||
| "value": -417.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__setup__tns": { | ||
| "value": -18600.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__hold__ws": { | ||
| "value": -20.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__hold__tns": { | ||
| "value": -80.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__design__instance__area": { | ||
| "value": 2885, | ||
| "compare": "<=" | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| export PLATFORM = asap7 | ||
| export DESIGN_NAME = tpu | ||
|
|
||
| export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/tpu/*.sv)) | ||
| export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc | ||
|
|
||
| export ASAP7_USE_VT = RVT LVT SLVT | ||
|
|
||
| # Synthesis | ||
| export SYNTH_HDL_FRONTEND = slang | ||
| export LEC_CHECK = 0 | ||
|
|
||
| # Floorplan | ||
| export CORE_UTILIZATION = 60 | ||
| export CORE_ASPECT_RATIO = 1 | ||
| export CORE_MARGIN = 2 | ||
|
|
||
| export TNS_END_PERCENT = 100 | ||
|
|
||
| # Routing | ||
| export MAX_ROUTING_LAYER = M9 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,10 @@ | ||
| set_units -time ps -capacitance fF -resistance kOhm -voltage V -current mA -power pW | ||
| current_design tpu | ||
|
|
||
| set clk_period 200 | ||
| set io_delay [expr 0.20 * $clk_period] | ||
| create_clock -name core_clock -period $clk_period [get_ports clk] | ||
| create_clock -name vclk_core -period $clk_period | ||
| set_max_fanout 16 [current_design] | ||
| set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks] | ||
| set_output_delay $io_delay -clock vclk_core [all_outputs] |
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Learn more about bidirectional Unicode characters
| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,112 @@ | ||
| { | ||
| "synth__canonical_netlist__hash": { | ||
| "value": "d93c1a668eaa8748f4ddbc8ed4ce3334d5b0ec1b", | ||
| "compare": "==", | ||
| "level": "warning" | ||
| }, | ||
| "synth__netlist__hash": { | ||
| "value": "b76c679a52aa60fd98a6195d467f06e647c75ad6", | ||
| "compare": "==", | ||
| "level": "warning" | ||
| }, | ||
| "synth__design__instance__area__stdcell": { | ||
| "value": 6020.0, | ||
| "compare": "<=" | ||
| }, | ||
| "constraints__clocks__count": { | ||
| "value": 2, | ||
| "compare": "==" | ||
| }, | ||
| "placeopt__design__instance__area": { | ||
| "value": 5926, | ||
| "compare": "<=" | ||
| }, | ||
| "placeopt__design__instance__count__stdcell": { | ||
| "value": 52923, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedplace__design__violations": { | ||
| "value": 0, | ||
| "compare": "==" | ||
| }, | ||
| "cts__design__instance__count__setup_buffer": { | ||
| "value": 4602, | ||
| "compare": "<=" | ||
| }, | ||
| "cts__design__instance__count__hold_buffer": { | ||
| "value": 4602, | ||
| "compare": "<=" | ||
| }, | ||
| "cts__timing__setup__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__setup__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__hold__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "cts__timing__hold__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__antenna_diodes_count": { | ||
| "value": 100, | ||
| "compare": "<=" | ||
| }, | ||
| "globalroute__timing__setup__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__setup__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__hold__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "globalroute__timing__hold__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "detailedroute__route__wirelength": { | ||
| "value": 119542, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__route__drc_errors": { | ||
| "value": 0, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__antenna__violating__nets": { | ||
| "value": 0, | ||
| "compare": "<=" | ||
| }, | ||
| "detailedroute__antenna_diodes_count": { | ||
| "value": 100, | ||
| "compare": "<=" | ||
| }, | ||
| "finish__timing__setup__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__setup__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__hold__ws": { | ||
| "value": -50.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__timing__hold__tns": { | ||
| "value": -200.0, | ||
| "compare": ">=" | ||
| }, | ||
| "finish__design__instance__area": { | ||
| "value": 6092, | ||
| "compare": "<=" | ||
| } | ||
| } |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,18 @@ | ||
| export PLATFORM = nangate45 | ||
| export DESIGN_NAME = picorv32 | ||
|
|
||
| export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/picorv32/*.sv)) | ||
| export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc | ||
|
|
||
| # Synthesis | ||
| export ABC_CLOCK_PERIOD_IN_PS = 900 | ||
| export SYNTH_RETIME_MODULES = $(DESIGN_NAME) | ||
| export SYNTH_HDL_FRONTEND = slang | ||
| export LEC_CHECK = 0 | ||
|
|
||
| # Floorplan | ||
| export CORE_UTILIZATION = 60 | ||
| export CORE_ASPECT_RATIO = 1 | ||
| export CORE_MARGIN = 2 | ||
|
|
||
| export TNS_END_PERCENT = 100 |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,10 @@ | ||
| set_units -time ns -capacitance fF -resistance kOhm -voltage V -current mA -power nW | ||
| current_design picorv32 | ||
|
|
||
| set clk_period 0.9 | ||
| set io_delay [expr 0.20 * $clk_period] | ||
| create_clock -name core_clock -period $clk_period [get_ports clk] | ||
| create_clock -name vclk_core -period $clk_period | ||
| set_max_fanout 16 [current_design] | ||
| set_input_delay $io_delay -clock vclk_core [all_inputs -no_clocks] | ||
| set_output_delay $io_delay -clock vclk_core [all_outputs] |
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