Next generation CGRA generator
Python 119 14
C++ 82 14
Python 61 11
SoC Based on ARM Cortex-M3
Verilog 40 18
Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.
Python 24 3
Papers, Posters, Presentations, Documentation...
20 5
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A polyhedral compiler for hardware accelerators
Fast PnR toolchain for CGRA
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