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Quil180/README.md

Hi, I'm Yousef Awad 👋

About Me

I'm a hardware design enthusiast passionate about digital design, FPGA development, and formal verification.

🔭 Currently Working On

  • Digital design projects using Verilog and SystemVerilog
  • FPGA development and verification
  • Learning formal verification methods

🛠️ Technologies & Tools

SystemVerilog Verilog Vivado Cadence Verilator Formal Verification UVM/OVM Constrained Randomized Tests C/C++ Rust

📫 How to Reach Me

LinkedIn Email

📊 GitHub Stats (incase you are interested)

Quil180's GitHub stats

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  1. nixos-config nixos-config Public

    This repository contains my personal modular NixOS configuration for seamless system setup and management. It includes installation scripts, user-specific settings, system-wide configurations, pack…

    Nix 1

  2. IEEE-UCF/2025-AMDHardware IEEE-UCF/2025-AMDHardware Public

    Python 1

  3. CyndaQuilLanguage CyndaQuilLanguage Public

    CyndaQuil is a statically-typed, compiled programming language focused on high performance, memory safety, and modern syntax. It features structured exception handling, strict grammar rules, and ef…

    C++ 3

  4. peytonlynnbarnes/sec_bot peytonlynnbarnes/sec_bot Public

    Python 2 1