madspace: fix SIMD mode

[theoheimel]

Parts of the madspace SIMD mode gave wrong results, and where it did work it was slower than it should be. This PR fixes it so that every SIMD mode reproduces the scalar results. It also makes the vectorized kernels fast, aligns mode selection with madmatrix, and adds tests that run in every mode.

• fix bugs so that the results match the scalar computation
• add tests so this doesn't break again
• make the run card parameter for the madspace SIMD mode consistent with the one for madmatrix
• performance: replace strided loads with contiguous ones, falling back to scalar where that isn't possible
• add an avx512y mode, like madmatrix

SIMD mode selection (user-facing, breaking)

• The run card option simd_vector_size is replaced by madspace_cpu_mode. It takes auto, scalar, simd_128 (ARM), simd_256 (AVX2), avx512y or simd_512, matching the names used by cpu_mode for madmatrix. It defaults to auto and invalid values are rejected. It is also a gridpack option (--madspace_cpu_mode).
• auto picks simd_512, then simd_256 on x86. On ARM it picks scalar, because the vectorized mode is currently slower there (about 20% for g g > t t~ g g with dummy matrix elements on an Apple M3). avx512y is never chosen automatically, since it was slower than simd_512 in the x86 benchmarks.
• API: set_simd_vector_size(int) is replaced by set_simd_mode(str) and supported_simd_modes(). The environment variable SIMD_VECTOR_SIZE is replaced by MADSPACE_SIMD_MODE.
• The C++ default with nothing set is auto, like the run card.
• set_simd_mode checks the mode right away and throws if the CPU backend was already loaded with a different mode; previously the call was silently ignored.
• Backend libraries are now named after their modes (libmadspace_cpu_simd_256, ...). ARM is detected from the target processor instead of APPLE.

New avx512y mode

AVX512 F/VL/DQ instructions with 256-bit vectors, like the madmatrix avx512y mode (simd_x86_256y.hpp). It uses mask registers, native 64-bit gathers and scatters, and cvttpd_epi64. The build enables AVX2 and FMA explicitly so that it compiles with GCC.

Performance: contiguous SIMD loads and stores

• The lanes of a vector are consecutive batch entries, so they are read and written with plain unaligned vector loads and stores instead of gathers and scatters.
• A kernel only runs vectorized if every batched argument has batch stride one. Otherwise the whole batch falls back to the scalar kernel, so results never depend on a strided path.
• Inputs that are marked single in instruction_set.yaml (masses, widths, cut bounds, channel tables, ...) now have their own kernel parameter types, FSIn/ISIn, and are read with broadcast loads. A generated kernel_checks.inc checks at compile time that the kernel signatures match the yaml; a mismatch would silently force the scalar path.
• Literals are stored padded to the vector width, so the vectorized kernels can read them like batched tensors. When they are returned as runtime outputs, they are returned unpadded.
• External arguments of the CPU runtime (inputs and output gradients, e.g. row-major numpy arrays or expanded torch gradients) are made batch-contiguous once on entry. This keeps the results independent of the caller's memory layout.
• Unused gradients of literal and integer inputs are written to batch-sized scratch memory. Otherwise they would be broadcast outputs, which force the scalar kernel on a single thread.
• With a single flavor, graph building skips gathers from constant flavor tables and multiplications by a weight that is always one.

Bug fixes

SIMD backends:

• ARM fma had its arguments in the wrong order.
• BVec(bool) was wrong on ARM and AVX2.
• AVX2 integer add, subtract and negate used 32-bit instructions on 64-bit lanes.
• Converting doubles to integers rounded instead of truncating, on AVX2 and AVX512.
• vscatter on AVX2 used an aligned store on an unaligned buffer.

Kernels and graph:

• The backward of sqrt had the wrong sign.
• The backward of reduce_product did not count zeros correctly.
• The probs gradient of sample_discrete_probs_inverse was overwritten instead of accumulated.
• cut_all/cut_any read their bounds through a view of the wrong rank.
• The t-channel cut bounds in the inverse could be NaN for massless particles (negative squared masses from rounding).
• The header generator marked every instruction as differentiable.
• sub(0, x) was wrongly folded to x. Stacks of scalar literals are now folded into a single literal.

Runtime and driver:

• contiguous_dims counted non-leading contiguous dimensions.
• tensor_add into a broadcast target (e.g. the gradient of a global) only added the first batch entry.
• Use-after-free of matrix element inputs with the dummy matrix element in multithreaded runs.
• Event files: the header-shape check was inverted, the header size was always zero, and the header was rewritten when loading a file instead of when appending to it. The event field type is now an enum.
• Freezing the max weight depended on thread timing, so seeded runs weren't reproducible. It now uses the expected unweighted count of the generate stages, which commit in a fixed order.

Tests

• madspace/tests/run_simd_modes.py runs the unit tests once for each SIMD mode the machine supports. The wheel CI now builds with SIMD enabled and uses it.
• test_simd_layout.py checks that the results don't depend on the memory layout (row/column-major inputs, broadcast tensors, small and large literals, literal outputs), and covers single inputs, constant folding and gradients into broadcast globals. The layout and graph tests are cpu_only. The gradient tests also run on the GPU CI device.
• New mg7 acceptance tests (test_*_simd_consistency_mg7): seeded generation in every supported mode. VEGAS cross sections must agree with scalar up to rounding, madnis ones within their uncertainties, and gridpacks trained in scalar mode must reproduce in every mode.
• test_process_inverse now uses a mapping with a mild pt cut, because the inverse without cuts is ill-conditioned for extremely soft gluons.