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Fix Efinix reload payload length and test exact wire bytes offline - #84
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The Efinix reload branch initializes two six-byte LBP16 records but sends the shared fourteen-record buffer. This transmits 72 indeterminate trailing bytes in the same payload. Give each FPGA branch its own correctly sized buffer: Efinix sends only the ordered image-select/config-enable and config-start writes, while Xilinx retains its complete 84-byte ICAP sequence. Existing firmware thresholds,
fallback_flag == 1, byte order and checked-helper abort handling are preserved.Adds
make check, a focused offline fixture linked to the actuallbp16.cwith fake Ethernet/serial callbacks. It compares literal query and complete payload bytes, firmware refusals, routing/order, and errors/zero/short transfers at all three I/O stages. No socket, device or mesaflash CLI is invoked.Validation on an ARM64 Azure VM with GCC 13.3.0 and the default
-Wall -Wextra -Werrorbuild: full project build passed; original upstream source compiled and failed exactly six Efinix length assertions across 50 cases; patched source passed all 50 cases. The 44 unchanged controls include Xilinx payloads, firmware refusals and expected SIGABRT behavior. Hardware reload, boot selection, firmware acceptance and recovery were not exercised.Base:
11e6f8571cc79d3acae57274aa57c4b99d26cb3f.