Issues

• 0x00 and 0xFF give IndexOutOfBounds errors

  CIDARLAB/NetlistSynthesizer#20 · Filter by author bder opened on Nov 13, 2014

• two compiler warnings

  CIDARLAB/NetlistSynthesizer#18 · Filter by author bder opened on Jul 31, 2014

• 0x16 precompute gives 10 gates instead of 9.

  bug
  CIDARLAB/NetlistSynthesizer#17 · Filter by author bder opened on Jul 23, 2014

• Check espresso

  CIDARLAB/NetlistSynthesizer#16 · Filter by author PrashantVaidyanathan opened on Jul 22, 2014 · NetSynth Tests

• check abc

  CIDARLAB/NetlistSynthesizer#15 · Filter by author PrashantVaidyanathan opened on Jul 22, 2014 · NetSynth Tests

• Check double inverters

  CIDARLAB/NetlistSynthesizer#14 · Filter by author PrashantVaidyanathan opened on Jul 22, 2014 · NetSynth Tests

• Test 2 nots to nor

  CIDARLAB/NetlistSynthesizer#13 · Filter by author PrashantVaidyanathan opened on Jul 22, 2014 · NetSynth Tests

• Create a test function for all n input circuits and verify correctness

  CIDARLAB/NetlistSynthesizer#12 · Filter by author PrashantVaidyanathan opened on Jul 22, 2014 · NetSynth Tests

• for precompute synthesis, a dangling OUTPUT gate exists name WireX

  CIDARLAB/NetlistSynthesizer#10 · Filter by author bder opened on Jul 22, 2014

• Change runABC to accept filepath instead of file name (esp for Blif files)

  enhancement
  CIDARLAB/NetlistSynthesizer#6 · Filter by author PrashantVaidyanathan opened on May 7, 2014
  

• Parse Structural Verilog to Netlist has issues with multiple outputs.

  bug
  CIDARLAB/NetlistSynthesizer#5 · Filter by author PrashantVaidyanathan opened on Apr 28, 2014
  5