From 4f203d85a90f199fffcc5711d63a08da3180e19a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 15 Oct 2026 13:23:42 +0200 Subject: [PATCH 1/3] asap7/aes-block: synthesize with slang, at absolute sizes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit yosys's own Verilog frontend is on its way out for SystemVerilog; aes-block now reads its sources with slang, the parent (config.mk) and its blocks (block.mk) alike. TL;DR the snags: - The aes sources write their registers with `<= #1`, which slang refuses as unsynthesizable timing control ("Compilation failed" at canonicalization); read_verilog ignored the delays silently. --ignore-timing does the same under slang, as asap7/aes-mbff has. The blocks need it too: a block runs from block.mk alone, while the parent blackboxes it, so a parent-only setting leaves aes_rcon failing on its own. - slang's netlist is 1.3 % smaller (5,592 vs 5,667 um^2), so CORE_UTILIZATION 47 gave a smaller core, and rtl_macro_placer found no valid tiling for its 21 macros (MPL-0003). The parent and each block now have DIE_AREA/CORE_AREA, today's result of their utilizations with read_verilog. Absolute sizes keep the macros fitting as yosys and OpenROAD improve: aes-block is the smoke test of BLOCKS plus macro placement, not of utilization. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- flow/designs/asap7/aes-block/block.mk | 19 ++++++++++++++++--- flow/designs/asap7/aes-block/config.mk | 13 ++++++++++--- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/flow/designs/asap7/aes-block/block.mk b/flow/designs/asap7/aes-block/block.mk index 841f0405bdb..d0a1571c16e 100644 --- a/flow/designs/asap7/aes-block/block.mk +++ b/flow/designs/asap7/aes-block/block.mk @@ -3,11 +3,24 @@ export PLATFORM = asap7 export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v)) export SDC_FILE = ./designs/$(PLATFORM)/aes/constraint.sdc +export SYNTH_HDL_FRONTEND = slang +# ignore unsynthesizable timing controls (the sources' #1 delays) +export SYNTH_SLANG_ARGS += --ignore-timing + export ABC_AREA = 1 -export CORE_UTILIZATION = 40 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 2 +# Absolute sizes, today's result of CORE_UTILIZATION 40 with yosys's +# Verilog frontend, so the parent's macros keep their size as yosys and +# OpenROAD improve: aes-block is the smoke test of BLOCKS plus macro +# placement, not of utilization. +ifeq ($(DESIGN_NAME),aes_rcon) +export DIE_AREA = 0 0 9.144 9.144 +export CORE_AREA = 2.052 2.160 7.128 7.020 +else +export DIE_AREA = 0 0 15.866 15.866 +export CORE_AREA = 2.052 2.160 13.824 13.770 +endif + export PLACE_DENSITY = 0.70 export MAX_ROUTING_LAYER ?= M5 diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk index a6574cb03fc..d58e6cc4c4f 100644 --- a/flow/designs/asap7/aes-block/config.mk +++ b/flow/designs/asap7/aes-block/config.mk @@ -6,11 +6,18 @@ export DESIGN_NICKNAME = aes-block export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v)) export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc +export SYNTH_HDL_FRONTEND = slang +# ignore unsynthesizable timing controls (the sources' #1 delays) +export SYNTH_SLANG_ARGS += --ignore-timing + export ABC_AREA = 1 -export CORE_UTILIZATION = 47 -export CORE_ASPECT_RATIO = 1 -export CORE_MARGIN = 2 +# Absolute sizes, today's result of CORE_UTILIZATION 47 with yosys's +# Verilog frontend, so the macros keep fitting as yosys and OpenROAD +# improve: this design is the smoke test of BLOCKS plus macro placement, +# not of utilization. +export DIE_AREA = 0 0 113.801 113.801 +export CORE_AREA = 2.052 2.160 111.780 111.780 export BLOCKS ?= aes_rcon aes_sbox export SYNTH_HIERARCHICAL = 1 From 2285436a4d8200d029a2ba66e88ad83b5d2d8b52 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Thu, 15 Oct 2026 13:43:59 +0200 Subject: [PATCH 2/3] asap7/aes-block: name aes_sbox's size, an unnamed block gets none MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A new block fell into the else arm and silently got aes_sbox's size. Each block is now named; one that is not has no size and stops at floorplan. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- flow/designs/asap7/aes-block/block.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/flow/designs/asap7/aes-block/block.mk b/flow/designs/asap7/aes-block/block.mk index d0a1571c16e..dfb43cf3d62 100644 --- a/flow/designs/asap7/aes-block/block.mk +++ b/flow/designs/asap7/aes-block/block.mk @@ -16,7 +16,7 @@ export ABC_AREA = 1 ifeq ($(DESIGN_NAME),aes_rcon) export DIE_AREA = 0 0 9.144 9.144 export CORE_AREA = 2.052 2.160 7.128 7.020 -else +else ifeq ($(DESIGN_NAME),aes_sbox) export DIE_AREA = 0 0 15.866 15.866 export CORE_AREA = 2.052 2.160 13.824 13.770 endif From aa1185473b0d9e9435ce1b5265d72ba070c28aba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20Harboe?= Date: Sat, 17 Oct 2026 08:47:50 +0200 Subject: [PATCH 3/3] asap7/aes-block: state the design's purpose, a smoke test of BLOCKS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit aes-block tests hierarchical synthesis, hardened blocks and their macros in the parent, not macro placement or utilization. Say so in config.mk, where the fixed die is set, and point block.mk at it. The old comment called the parent's die "today's result of CORE_UTILIZATION 47" with read_verilog; it is larger than that (12,028 vs 11,875 um^2 core), by design: headroom keeps the macros off the edge of what macro placement can pack. Co-Authored-By: Claude Opus 5.5 Signed-off-by: Øyvind Harboe --- flow/designs/asap7/aes-block/block.mk | 5 +---- flow/designs/asap7/aes-block/config.mk | 9 +++++---- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/flow/designs/asap7/aes-block/block.mk b/flow/designs/asap7/aes-block/block.mk index dfb43cf3d62..e8017ed6433 100644 --- a/flow/designs/asap7/aes-block/block.mk +++ b/flow/designs/asap7/aes-block/block.mk @@ -9,10 +9,7 @@ export SYNTH_SLANG_ARGS += --ignore-timing export ABC_AREA = 1 -# Absolute sizes, today's result of CORE_UTILIZATION 40 with yosys's -# Verilog frontend, so the parent's macros keep their size as yosys and -# OpenROAD improve: aes-block is the smoke test of BLOCKS plus macro -# placement, not of utilization. +# Fixed sizes so the parent's macros keep their size: see config.mk. ifeq ($(DESIGN_NAME),aes_rcon) export DIE_AREA = 0 0 9.144 9.144 export CORE_AREA = 2.052 2.160 7.128 7.020 diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk index d58e6cc4c4f..def252a38a9 100644 --- a/flow/designs/asap7/aes-block/config.mk +++ b/flow/designs/asap7/aes-block/config.mk @@ -12,10 +12,11 @@ export SYNTH_SLANG_ARGS += --ignore-timing export ABC_AREA = 1 -# Absolute sizes, today's result of CORE_UTILIZATION 47 with yosys's -# Verilog frontend, so the macros keep fitting as yosys and OpenROAD -# improve: this design is the smoke test of BLOCKS plus macro placement, -# not of utilization. +# aes-block is the smoke test of BLOCKS: hierarchical synthesis, two +# hardened blocks, and their macros placed in the parent. It is not a +# test of macro placement or of utilization. The die is fixed, with +# headroom, so that changes in synthesis or OpenROAD do not move this +# design onto the edge of what macro placement can pack. export DIE_AREA = 0 0 113.801 113.801 export CORE_AREA = 2.052 2.160 111.780 111.780