diff --git a/flow/designs/asap7/aes-block/block.mk b/flow/designs/asap7/aes-block/block.mk
index 841f0405bd..e8017ed643 100644
--- a/flow/designs/asap7/aes-block/block.mk
+++ b/flow/designs/asap7/aes-block/block.mk
@@ -3,11 +3,21 @@ export PLATFORM               = asap7
 export VERILOG_FILES = $(sort $(wildcard ./designs/src/aes/*.v))
 export SDC_FILE      = ./designs/$(PLATFORM)/aes/constraint.sdc
 
+export SYNTH_HDL_FRONTEND     = slang
+# ignore unsynthesizable timing controls (the sources' #1 delays)
+export SYNTH_SLANG_ARGS += --ignore-timing
+
 export ABC_AREA               = 1
 
-export CORE_UTILIZATION       = 40 
-export CORE_ASPECT_RATIO      = 1
-export CORE_MARGIN            = 2
+# Fixed sizes so the parent's macros keep their size: see config.mk.
+ifeq ($(DESIGN_NAME),aes_rcon)
+export DIE_AREA               = 0 0 9.144 9.144
+export CORE_AREA              = 2.052 2.160 7.128 7.020
+else ifeq ($(DESIGN_NAME),aes_sbox)
+export DIE_AREA               = 0 0 15.866 15.866
+export CORE_AREA              = 2.052 2.160 13.824 13.770
+endif
+
 export PLACE_DENSITY          = 0.70
 
 export MAX_ROUTING_LAYER       ?= M5
diff --git a/flow/designs/asap7/aes-block/config.mk b/flow/designs/asap7/aes-block/config.mk
index a6574cb03f..def252a38a 100644
--- a/flow/designs/asap7/aes-block/config.mk
+++ b/flow/designs/asap7/aes-block/config.mk
@@ -6,11 +6,19 @@ export DESIGN_NICKNAME        = aes-block
 export VERILOG_FILES = $(sort $(wildcard $(DESIGN_HOME)/src/aes/*.v))
 export SDC_FILE      = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
 
+export SYNTH_HDL_FRONTEND     = slang
+# ignore unsynthesizable timing controls (the sources' #1 delays)
+export SYNTH_SLANG_ARGS += --ignore-timing
+
 export ABC_AREA               = 1
 
-export CORE_UTILIZATION       = 47
-export CORE_ASPECT_RATIO      = 1
-export CORE_MARGIN            = 2
+# aes-block is the smoke test of BLOCKS: hierarchical synthesis, two
+# hardened blocks, and their macros placed in the parent. It is not a
+# test of macro placement or of utilization. The die is fixed, with
+# headroom, so that changes in synthesis or OpenROAD do not move this
+# design onto the edge of what macro placement can pack.
+export DIE_AREA               = 0 0 113.801 113.801
+export CORE_AREA              = 2.052 2.160 111.780 111.780
 
 export BLOCKS ?= aes_rcon aes_sbox
 export SYNTH_HIERARCHICAL = 1