diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index c382a1bd..07274f62 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -2,7 +2,8 @@ # SPDX-License-Identifier: Apache-2.0 # # CI for the three-step flow (cbuild setup, create_ai_layer.py, cbuild) -# followed by an FVP run, with each of the three toolchains. +# followed by an FVP run that checks the generated face against the host +# reference, with each of the three toolchains. name: Build and Run on: @@ -17,11 +18,73 @@ env: TARGET: SSE-320-U85 jobs: + # Step 1 and 2 of the flow, once: the AI layer is the same for every + # toolchain and both target-types. The model data + # (ai_layer/model_pte_data.inc) is generated here rather than committed; + # the job also renders the host's + # fake-quant reference image of the boot demo for the FVP check below. + export: + name: Create the AI layer + runs-on: ubuntu-latest + + steps: + - name: Checkout repo + uses: actions/checkout@v7 + + - name: Install tools + uses: ARM-software/cmsis-actions/vcpkg@v1 + + # cbuild setup of CMSIS-Toolbox 2.15 configures the CMake project, which + # probes the solution's compiler (AC6). + - name: Activate Arm tool license + uses: ARM-software/cmsis-actions/armlm@v1 + + - name: Cache packs + uses: actions/cache@v6 + with: + key: cmsis-packs-${{ hashFiles('*.csolution.yml') }} + path: /home/runner/.cache/arm/packs + + # torch + executorch is a multi-gigabyte install and otherwise dominates + # the job. Keyed on the requirements files so a pin change rebuilds it. + - name: Cache model-export venv + uses: actions/cache@v6 + with: + key: venv-${{ runner.os }}-${{ hashFiles('requirements*.txt', 'setup_venv.py') }} + path: .venv + + - name: Cache pico-faces checkpoints + uses: actions/cache@v6 + with: + key: pico-faces-${{ hashFiles('setup_venv.py') }} + path: model/pico_faces + + - name: Create model-export venv and fetch the checkpoints + run: ./setup_venv.sh + + - name: Generate the MLOps information + run: cbuild setup ${SOLUTION}.csolution.yml --active ${TARGET} --packs + + - name: Create the AI layer + run: python3 create_ai_layer.py ${SOLUTION}.cbuild-mlops.yml + + - name: Render the host reference of the boot demo + run: python3 model/verify_export.py --stage fakequant --seed 3 --class 1 --w 4 --k 4 --out reference/pf_fakequant.png + + - name: Upload the AI layer + uses: actions/upload-artifact@v4 + with: + name: ai-layer + path: | + ai_layer/ + reference/ + # Full build plus an FVP run, once per toolchain. Linux only: the FVP needs # an Arm user-based license, so matrixing this across hosts is not cheap. build-and-run: name: Build and run on Corstone-320 (${{ matrix.toolchain }}) runs-on: ubuntu-latest + needs: export strategy: fail-fast: false @@ -32,6 +95,11 @@ jobs: - name: Checkout repo uses: actions/checkout@v7 + - name: Download the AI layer + uses: actions/download-artifact@v4 + with: + name: ai-layer + - name: Install tools uses: ARM-software/cmsis-actions/vcpkg@v1 @@ -41,7 +109,8 @@ jobs: # The FVP loads the runner's libpython3.11, whose standard library is # not where that build's prefix says; the model then dies at start-up # with "Fatal Python error: init_fs_encoding". PYTHONHOME (set on the - # FVP step only) points it at a complete Python 3.11. + # FVP step only) points it at a complete Python 3.11, which also runs + # the image comparison. - name: Set up Python 3.11 for the FVP uses: actions/setup-python@v5 with: @@ -53,25 +122,8 @@ jobs: key: cmsis-packs-${{ hashFiles('*.csolution.yml') }} path: /home/runner/.cache/arm/packs - # torch + executorch is a multi-gigabyte install and otherwise dominates - # the job. Keyed on the requirements files so a pin change rebuilds it. - - name: Cache model-export venv - uses: actions/cache@v6 - with: - key: venv-${{ runner.os }}-${{ hashFiles('requirements*.txt', 'setup_venv.py') }} - path: .venv - - - name: Create model-export venv - run: ./setup_venv.sh - - - name: Generate the MLOps information - run: cbuild setup ${SOLUTION}.csolution.yml --active ${TARGET} --packs - - - name: Create the AI layer - run: python3 create_ai_layer.py ${SOLUTION}.cbuild-mlops.yml - - name: Build - run: cbuild ${SOLUTION}.csolution.yml --active ${TARGET} --toolchain ${{ matrix.toolchain }} + run: cbuild ${SOLUTION}.csolution.yml --active ${TARGET} --toolchain ${{ matrix.toolchain }} --packs - name: Run on the FVP env: @@ -80,7 +132,7 @@ jobs: IMAGE=$(find out -name "${SOLUTION}.axf" -o -name "${SOLUTION}.elf" | head -1) echo "Running ${IMAGE}" # stdio is retargeted to semihosting, so the output arrives on the - # FVP's own stdout. + # FVP's own stdout; the application ends the simulation itself. FVP_Corstone_SSE-320 \ -f board/Corstone-320/fvp_config.txt \ -a "${IMAGE}" \ @@ -90,6 +142,15 @@ jobs: echo "Checking simulation output" grep -q "Test_result: PASS" fvp_stdout.log + # The run writes the generated image to out/fvp_image.bin through + # semihosting; it has to match what the quantized graphs compute on the + # host (the NPU's integer arithmetic differs from the fake-quant graphs + # only by rounding). + - name: Compare the image with the host reference + run: | + python -m pip install --quiet numpy pillow + python model/verify_export.py --compare out/fvp_image.bin reference/pf_fakequant.png --min-psnr 35 + - name: Upload artifacts if: always() uses: actions/upload-artifact@v4 @@ -97,16 +158,17 @@ jobs: name: corstone-320-${{ matrix.toolchain }} path: | fvp_stdout.log + out/fvp_image.bin + out/fvp_result.txt out/**/*.axf out/**/*.elf - ai_layer/ # The same solution for the Alif Ensemble E8 DevKit (target-type DevKit-E8), - # once per toolchain. Build only: the hardware is not in CI. The shipped - # ai_layer/ is used, so no venv is needed. + # once per toolchain. Build only: the hardware is not in CI. build-devkit-e8: name: Build for the Alif Ensemble E8 DevKit (${{ matrix.toolchain }}) runs-on: ubuntu-latest + needs: export strategy: fail-fast: false @@ -117,6 +179,11 @@ jobs: - name: Checkout repo uses: actions/checkout@v7 + - name: Download the AI layer + uses: actions/download-artifact@v4 + with: + name: ai-layer + - name: Install tools uses: ARM-software/cmsis-actions/vcpkg@v1 @@ -126,14 +193,11 @@ jobs: - name: Cache packs uses: actions/cache@v6 with: - key: cmsis-packs + key: cmsis-packs-${{ hashFiles('*.csolution.yml') }} path: /home/runner/.cache/arm/packs - - name: Generate the MLOps information - run: cbuild setup ${SOLUTION}.csolution.yml --active DevKit-E8 --packs - - name: Build - run: cbuild ${SOLUTION}.csolution.yml --active DevKit-E8 --toolchain ${{ matrix.toolchain }} + run: cbuild ${SOLUTION}.csolution.yml --active DevKit-E8 --toolchain ${{ matrix.toolchain }} --packs - name: Upload artifacts if: always() @@ -142,6 +206,7 @@ jobs: name: devkit-e8-${{ matrix.toolchain }} path: | out/**/*.axf + out/**/*.elf out/**/*.hex # The export flow must work on all three host OSes -- that is the point of a @@ -186,6 +251,8 @@ jobs: # No cbuild-mlops.yml without cbuild; importing the script checks # that it parses under this interpreter. "${PY}" -c "import create_ai_layer; print('create_ai_layer.py OK')" + # The checkpoints setup_venv.py downloaded load on this host. + "${PY}" -c "import sys; sys.path.insert(0, 'model'); import model; model.load_checkpoint(); print('checkpoints OK')" - name: Report resolved versions shell: bash diff --git a/.gitignore b/.gitignore index b978bff9..93872e2a 100644 --- a/.gitignore +++ b/.gitignore @@ -3,9 +3,15 @@ __pycache__/ *.pyc -# The exported ExecuTorch program. create_ai_layer.py writes it next to the -# generated AI layer; the C array in ai_layer/model_pte.c is what gets built. +# The exported ExecuTorch program and the rows of its C array. create_ai_layer.py +# writes both into the generated AI layer; at ~2.8 MB (a ~14 MB C source) they +# are regenerated by "Create AI layer" rather than committed. The clayer, the +# headers and model_pte.c, which includes the rows, are committed. *.pte +ai_layer/model_pte_data.inc + +# The pico-faces checkpoints setup_venv.py downloads (see PICO_FACES_FILES). +model/pico_faces/ # CMSIS-Toolbox build outputs. RTE/ is tracked in full: the layers' configuration # files and the per-context RTE/__/ headers the toolbox writes. diff --git a/.vscode.d/tasks.json b/.vscode.d/tasks.json index d54dd232..d20011fa 100644 --- a/.vscode.d/tasks.json +++ b/.vscode.d/tasks.json @@ -29,7 +29,7 @@ }, { "label": "Create AI layer", - "detail": "Export model/model.py for the NPU in cmsis-executorch.cbuild-mlops.yml and write ai_layer/ (run a CMSIS build or 'cbuild setup' first)", + "detail": "Export model/model.py (pico-faces) for the NPU in cmsis-executorch.cbuild-mlops.yml and write ai_layer/ (run a CMSIS build or 'cbuild setup' first; takes a few minutes)", "type": "shell", "command": "${workspaceFolder}/.venv/bin/python", "args": ["create_ai_layer.py", "cmsis-executorch.cbuild-mlops.yml"], @@ -43,12 +43,14 @@ }, { "label": "Alif: Install M55_HP debug stubs (DevKit-E8, single core configuration)", - "detail": "Programs the ATOC/MRAM stubs with Alif SETOOLS so J-Link can load and debug the M55_HP core. Overwrites build/config/M55_HP_mram_cfg.json and build/images/M55_HP_mram_stub.bin in the SETOOLS tree, then runs app-gen-toc and app-write-mram; stops at the first failing step. Set SW4 to SEUART, set 'alif.setools.root' in your VS Code settings.", + "detail": "Programs the ATOC/MRAM stubs with Alif SETOOLS so J-Link can load and debug the M55_HP core. Selects the DevKit-E8's part in SETOOLS first (E8 AE822FA0E5597LS0, revision A0): app-gen-toc writes it into the ATOC, and the Secure Enclave does not boot an ATOC built for another part. The part and revision are written into SETOOLS' utils/global-cfg.db before tools-config runs, because tools-config refuses to start while another project's 'tools-config -p' without '-r' has left a revision the part does not have ('Revision is invalid!'). Overwrites build/config/M55_HP_mram_cfg.json and build/images/M55_HP_mram_stub.bin in the SETOOLS tree, then runs app-gen-toc and app-write-mram; stops at the first failing step. Set SW4 to SEUART, set 'alif.setools.root' in your VS Code settings.", "type": "shell", "command": [ "cp './.alif/M55_HP_mram_cfg.json' '${config:alif.setools.root}/build/config/M55_HP_mram_cfg.json' &&", "cp './.alif/M55_HP_mram_stub.bin' '${config:alif.setools.root}/build/images/M55_HP_mram_stub.bin' &&", "cd '${config:alif.setools.root}' &&", + "sed -i.bak -E -e 's|(\"Part#\": *\")[^\"]*|\\1E8 (AE822FA0E5597LS0) - 5.5 MRAM / 9.75 SRAM|' -e 's|(\"Revision\": *\")[^\"]*|\\1A0|' utils/global-cfg.db &&", + "./tools-config -p 'E8 (AE822FA0E5597LS0) - 5.5 MRAM / 9.75 SRAM' -r A0 &&", "./app-gen-toc -f 'build/config/M55_HP_mram_cfg.json' &&", "./app-write-mram -p ${input:discoverCOM}" ], @@ -57,6 +59,62 @@ "cp './.alif/M55_HP_mram_cfg.json' '${config:alif.setools.root}/build/config/M55_HP_mram_cfg.json'; if (-not $?) { exit 1 };", "cp './.alif/M55_HP_mram_stub.bin' '${config:alif.setools.root}/build/images/M55_HP_mram_stub.bin'; if (-not $?) { exit 1 };", "cd '${config:alif.setools.root}'; if (-not $?) { exit 1 };", + "(Get-Content utils/global-cfg.db -Raw) -replace '(\\x22Part#\\x22:\\s*\\x22)[^\\x22]*', '$1E8 (AE822FA0E5597LS0) - 5.5 MRAM / 9.75 SRAM' -replace '(\\x22Revision\\x22:\\s*\\x22)[^\\x22]*', '$1A0' | Set-Content utils/global-cfg.db -NoNewline; if (-not $?) { exit 1 };", + "./tools-config -p 'E8 (AE822FA0E5597LS0) - 5.5 MRAM / 9.75 SRAM' -r A0; if (-not $?) { exit 1 };", + "./app-gen-toc -f 'build/config/M55_HP_mram_cfg.json'; if (-not $?) { exit 1 };", + "./app-write-mram -p ${input:discoverCOM}" + ], + "options": { + "shell": { + "executable": "powershell.exe", + "args": [ + "-Command" + ] + } + } + }, + "linux": { + "options": { + "shell": { + "executable": "/bin/bash", + "args": [ + "-c" + ] + } + } + }, + "osx": { + "options": { + "shell": { + "executable": "/bin/bash", + "args": [ + "-c" + ] + } + } + }, + "problemMatcher": [] + }, + { + "label": "Alif: Install M55_HP debug stubs (AppKit-E8, single core configuration)", + "detail": "Programs the ATOC/MRAM stubs with Alif SETOOLS so J-Link can load and debug the M55_HP core. Selects the AppKit-E8's part in SETOOLS first (E8 AE822FA0E5597BS0, revision A0; answer 'y' if app-write-mram reports another revision): app-gen-toc writes it into the ATOC, and the Secure Enclave does not boot an ATOC built for another part. The part and revision are written into SETOOLS' utils/global-cfg.db before tools-config runs, because tools-config refuses to start while another project's 'tools-config -p' without '-r' has left a revision the part does not have ('Revision is invalid!'). Overwrites build/config/M55_HP_mram_cfg.json and build/images/M55_HP_mram_stub.bin in the SETOOLS tree, then runs app-gen-toc and app-write-mram; stops at the first failing step. Set SW4 to SEUART, set 'alif.setools.root' in your VS Code settings.", + "type": "shell", + "command": [ + "cp './.alif/M55_HP_mram_cfg.json' '${config:alif.setools.root}/build/config/M55_HP_mram_cfg.json' &&", + "cp './.alif/M55_HP_mram_stub.bin' '${config:alif.setools.root}/build/images/M55_HP_mram_stub.bin' &&", + "cd '${config:alif.setools.root}' &&", + "sed -i.bak -E -e 's|(\"Part#\": *\")[^\"]*|\\1E8 (AE822FA0E5597BS0) - 5.5 MRAM / 9.75 SRAM|' -e 's|(\"Revision\": *\")[^\"]*|\\1A0|' utils/global-cfg.db &&", + "./tools-config -p 'E8 (AE822FA0E5597BS0) - 5.5 MRAM / 9.75 SRAM' -r A0 &&", + "./app-gen-toc -f 'build/config/M55_HP_mram_cfg.json' &&", + "./app-write-mram -p ${input:discoverCOM}" + ], + "windows": { + "command": [ + "cp './.alif/M55_HP_mram_cfg.json' '${config:alif.setools.root}/build/config/M55_HP_mram_cfg.json'; if (-not $?) { exit 1 };", + "cp './.alif/M55_HP_mram_stub.bin' '${config:alif.setools.root}/build/images/M55_HP_mram_stub.bin'; if (-not $?) { exit 1 };", + "cd '${config:alif.setools.root}'; if (-not $?) { exit 1 };", + "(Get-Content utils/global-cfg.db -Raw) -replace '(\\x22Part#\\x22:\\s*\\x22)[^\\x22]*', '$1E8 (AE822FA0E5597BS0) - 5.5 MRAM / 9.75 SRAM' -replace '(\\x22Revision\\x22:\\s*\\x22)[^\\x22]*', '$1A0' | Set-Content utils/global-cfg.db -NoNewline; if (-not $?) { exit 1 };", + "./tools-config -p 'E8 (AE822FA0E5597BS0) - 5.5 MRAM / 9.75 SRAM' -r A0; if (-not $?) { exit 1 };", "./app-gen-toc -f 'build/config/M55_HP_mram_cfg.json'; if (-not $?) { exit 1 };", "./app-write-mram -p ${input:discoverCOM}" ], diff --git a/README.md b/README.md index b6c0c587..b5e63e83 100644 --- a/README.md +++ b/README.md @@ -1,13 +1,19 @@ -# ExecuTorch on Ethos-U85: hackathon guide - -The Arm ExecuTorch example, on its `hackathon` branch with the Alif board -added. One CMSIS solution runs a tiny int8 CNN on the Ethos-U85 of the **Alif Ensemble E8 DevKit** (Cortex-M55 -HP core) and on the **Corstone-320 FVP**; you switch between them by -target-type. The model is exported from PyTorch in three steps: the -CMSIS-Toolbox describes the target, `create_ai_layer.py` turns that into the -AI layer, the toolbox builds the application. This page takes you from an -empty machine to a debug session on the board. Everything about the example -itself is in [documentation/example.md](documentation/example.md). +# pico-faces on Ethos-U85 with ExecuTorch: hackathon guide + +The Arm ExecuTorch example, on its `hackathon` branch: a generative model on +a microcontroller. [pico-faces](https://github.com/cpldcpu/pico-faces) by +cpldcpu, a latent diffusion transformer (2.5M parameters) with a small +decoder, generates 128x128 faces; exported through ExecuTorch, every layer of +it runs on the Ethos-U85 NPU while the Cortex-M drives the sampling loop. One +CMSIS solution runs it on the **Alif Ensemble E8 DevKit** or the **Ensemble E8 +AI/ML AppKit** (Cortex-M55 HP core; the faces appear on the board's LCD, a new +one per joystick press) and on the **Corstone-320 FVP**; you switch between +them by target-type. The model is +exported from PyTorch in three steps: the CMSIS-Toolbox describes the target, +`create_ai_layer.py` turns that into the AI layer, the toolbox builds the +application. This page takes you from an empty machine to a debug session on +the board. Everything about the example itself is in +[documentation/example.md](documentation/example.md). ## 1. Host tools @@ -29,7 +35,7 @@ itself is in [documentation/example.md](documentation/example.md). ## 2. Alif and SEGGER tools (board only) -1. **Alif SETOOLS** V1.110.000 or later from the +1. **Alif SETOOLS** V1.110.00 or later (V1.112.00 is current) from the [Alif software and tools page](https://alifsemi.com/support/software-tools/ensemble/) (login required). Unpack it; on Linux and macOS make the tools executable and install the Python packages its README lists. Add the root directory @@ -46,16 +52,17 @@ itself is in [documentation/example.md](documentation/example.md). ## 3. Board -- Connect a USB-C cable to **PRG USB** (the connector in the corner). It - powers the board and carries the J-Link and a USB-to-UART bridge. Leave - **MCU USB** unconnected. -- Jumpers at their defaults: **JP5 on 1-2**, **JP7 on 3-4**. Never move - jumpers with power applied. -- **SW4** selects what the UART bridge is connected to: +- Connect a USB cable to **PRG USB** (USB-C in the corner of the DevKit, + Micro-USB on the AppKit). It powers the board and carries the J-Link and a + USB-to-UART bridge. Leave the other USB device connector unconnected. +- DevKit: jumpers at their defaults, **JP5 on 1-2**, **JP7 on 3-4**. Never + move jumpers with power applied. +- **SW4** (on both boards) selects what the UART bridge is connected to: | SW4 | Connected to | Used for | |-----|--------------|----------| | `SEUART` (default) | Secure Enclave UART | SETOOLS (step 5) | + | `UART2` (AppKit only, middle position) | Application UART2 | Not used here | | `UART4` | Application UART4, 115200 8N1 | The example's console (step 6) | - With the board attached, run these once: in the SETOOLS directory @@ -75,14 +82,22 @@ git checkout hackathon Open the folder in VS Code and accept the tool activation and the pack installation (`PyTorch::ExecuTorch`, `AlifSemiconductor::Ensemble`, CMSIS). In the CMSIS view open **Manage Solution**, choose the target-type -**DevKit-E8** (or **SSE-320-U85** for the FVP) and click **Apply**. - -The repository ships a generated AI layer, so no Python is needed to build. -To change the model, run **Terminal > Run Task > Setup Python virtual -environment** once (several GB of PyTorch, takes a while; the **(uv)** -variant of the task uses uv and can download the Python version it asks -for), edit `model/model.py`, and run the task **Create AI layer** before -building. +of your board, **DevKit-E8** or **AppKit-E8** (**SSE-320-U85** for the FVP), +and click **Apply**. + +The model data is generated rather than committed, so a fresh checkout +needs Python once before the first build: + +1. **Terminal > Run Task > Setup Python virtual environment** (several GB of + PyTorch, takes a while; the **(uv)** variant of the task uses uv and can + download the Python version it asks for). It also downloads the + pico-faces checkpoints (about 60 MB, checked by SHA-256) into + `model/pico_faces/`. +2. **Terminal > Run Task > Create AI layer** exports the model for the NPU + and writes `ai_layer/` (a few minutes). It reads + `cmsis-executorch.cbuild-mlops.yml`, which the CMSIS Solution extension + writes when it loads the solution (click **Build** once if the file is + missing). Run the task again after changing `model/model.py`. ## 5. Prepare the board once @@ -90,10 +105,17 @@ The Secure Enclave boots the M55 cores from a table of contents in MRAM; the debugger needs that table to point at a debug stub. 1. SW4 to **SEUART**, PRG USB attached. -2. **Terminal > Run Task > Alif: Install M55_HP debug stubs (DevKit-E8, single core configuration)**. Choose COM port +2. **Terminal > Run Task > Alif: Install M55_HP debug stubs (DevKit-E8, single core configuration)**, + or the **(AppKit-E8, ...)** task for the AppKit. Choose COM port discovery (`-d`) the first time; SETOOLS remembers the port. The task + selects the board's part in SETOOLS (`tools-config -p 'E8 + (AE822FA0E5597LS0) ...' -r A0` for the DevKit, `AE822FA0E5597BS0` for the + AppKit: the part goes into the table of contents, + and the Secure Enclave does not boot a table built for another part), copies the configuration and stub from `.alif/` into the SETOOLS tree and - runs `app-gen-toc` and `app-write-mram`. + runs `app-gen-toc` and `app-write-mram`. If `app-write-mram` reports a + different revision of the board, answer `y`: only the part number decides + whether the table boots. 3. SW4 to **UART4**. Repeat this after another project has reprogrammed the table. @@ -104,34 +126,76 @@ Repeat this after another project has reprogrammed the table. port, 115200 baud. 2. In the CMSIS view click **Build**, then **Debug** (or **Run**). Keil Studio starts the J-Link GDB server over SWD, loads the image into MRAM and stops - at `main`; continue with F5. The console shows: + at `main`; continue with F5. The console shows the Ethos-U banner, the + program and its two methods, the timings of the boot demo, the CRC of the + image, an ASCII preview of the face and the pass marker: ```text Ethos-U version info: Arch: v2.0.0 MACs/cc: 256 Cmd stream: v1 - ExecuTorch Ethos-U85 example: 8736 byte model - Output: 10 element(s): -0.0142 0.0206 0.0601 -0.0886 0.0791 0.0522 -0.0301 -0.0775 -0.2800 -0.0095 + ExecuTorch pico-faces (m3_long_cfg, a16w8/a8w8): 2796016 byte program + Methods: + dit_step 2 input(s), 1 output(s), 16384 planned byte(s) + decode 1 input(s), 1 output(s), 245760 planned byte(s) + Generating: seed 3, 4 steps, class 1, w 4.0 + Display: 480x800 RGB888 panel started + dit_step: 8 call(s), 68 ms total (8 ms each) + decode: 3 ms + total: 78 ms at 400 MHz (wall clock; not meaningful on the FVP) + dit_step: NPU 27132 kcycles, active 95%, MAC active 39%, 32 MAC/cycle, read 21279 kB on AXI0 + 0 kB on AXI1 + decode: NPU 1303 kcycles, active 50%, MAC active 37%, 83 MAC/cycle, read 434 kB on AXI0 + 0 kB on AXI1 + Image: 128x128x3, CRC32 6b938c66 + |::::::::....... . ..........| + |::::::::........... ..... | + ... Test_result: PASS + Interactive: send "G [k_steps] [class] [w]" (viewer/view_serial.py) or "I" + Joystick: left = one new image, right = start/stop continuous generation + ``` + + A face with guidance takes 78 ms: eight `dit_step` calls of 8.5 ms on the + NPU and a 3 ms decode. The same face appears on the LCD, scaled to + 384 x 384 in the centre of the screen; it is bit for bit the image the FVP + produces. (The CRC depends on the exported program, which can differ + slightly between the machines that run **Create AI layer**.) +3. Press the **SW2 joystick** to the left for a new face (the next seed; class + and guidance follow from it), to the right to generate faces back to back + until you press right again. Each one is reported on the console. +4. Or request faces from the host with pico-faces' viewer (close the Serial + Monitor first, the viewer needs the port; in a clone of + [pico-faces](https://github.com/cpldcpu/pico-faces), + `pip install pyserial pillow`): + + ```bash + python viewer/view_serial.py --port /dev/tty.usbmodemXXXX --seed 3 --steps 4 --class 1 --cfg 4 --show ``` -3. Set a breakpoint after `module.forward(input)` in `src/app_main.cpp` and - inspect the output tensor, or ask the CMSIS Developer Assistant to do it: - "Build for the DevKit-E8, load it, break after the inference and show me - the output logits." + Classes are 0 (female, neutral), 1 (female, smiling), 2 (male, neutral), + 3 (male, smiling) and 4 (unconditional); `--cfg` is the guidance strength + (0 = plain), `--steps` 8, 4, 2 or 1. +5. Set a breakpoint after `generate()` in `src/app_main.cpp` and inspect the + timings in `tm`, or ask the CMSIS Developer Assistant to do it: "Build for + the DevKit-E8, load it, break after the first generate() and show me the + NPU cycles per method." **FVP instead of the board:** choose the **SSE-320-U85** target-type and click -**Run** or **Debug**; the same output appears in the terminal. On macOS, -where Arm ships no FVP build, the FVP runs in Docker: set `model:` in the -csolution's SSE-320-U85 target-set to `${workspaceFolder}/.vscode/fvp.sh`, -copy `.vscode/launch.json.mac` to `.vscode/launch.json`, and keep Docker -Desktop running (the first run builds the image, about 100 MB). +**Run** or **Debug**; the same output appears in the terminal (a run takes a +few minutes), and the image lands in `out/fvp_image.bin`. +`python3 model/verify_export.py --compare out/fvp_image.bin ` +compares it with the host's rendering of the same seed (see +[documentation/example.md](documentation/example.md)). On macOS, where Arm +ships no FVP build, the FVP runs in Docker: set `model:` in the csolution's +SSE-320-U85 target-set to `${workspaceFolder}/.vscode/fvp.sh`, copy +`.vscode/launch.json.mac` to `.vscode/launch.json`, and keep Docker Desktop +running (the first run builds the image, about 100 MB). ## 7. If something does not work - **J-Link connects but never stops at `main`:** either the table of contents - does not point at the debug stub (repeat step 5), or the image cannot boot. + does not point at the debug stub or was built for another part, which the + Secure Enclave skips (repeat step 5), or the image cannot boot. Look before reprogramming: in the debugger, read the vector table at `0x80200000` and the fault registers (CFSR/HFSR); a PC of `0xEFFFFFFE` is a lockup at reset, which an image linked to run from ITCM produces when the @@ -142,13 +206,27 @@ Desktop running (the first run builds the image, about 100 MB). until it is power-cycled. - **No console output:** SW4 is still on `SEUART`, or the port was opened before the switch was moved. Set `UART4` and reopen the port. +- **Every SETOOLS tool prints `Revision is invalid!`:** SETOOLS stores the + selected part and revision in `utils/global-cfg.db`, and a + `tools-config -p` without `-r` (another project switching to an E7, for + example) keeps a revision the new part does not have. From then on even + `tools-config` refuses to run. The stub tasks of step 5 write their + board's part and revision into that file before they call `tools-config`, + so they recover by themselves; for SETOOLS commands of your own, set + `"Part#"` to `"E8 (AE822FA0E5597LS0) - 5.5 MRAM / 9.75 SRAM"` (DevKit) or + `"E8 (AE822FA0E5597BS0) - 5.5 MRAM / 9.75 SRAM"` (AppKit) and `"Revision"` + to `"A0"` there. - **`app-write-mram` gets no answer:** press reset while it waits, check SW4 is on `SEUART`, close any terminal holding the port. -- **"`.venv` does not exist":** run the task **Setup Python virtual - environment** first; it is only needed to regenerate the AI layer. +- **The build stops at `model_pte_data.inc is missing`:** the model data is + not committed; run the tasks **Setup Python virtual environment** and + **Create AI layer** (step 4). +- **"`.venv` does not exist" or "`model/pico_faces/...` is missing":** run the + task **Setup Python virtual environment** first; it creates the + environment and downloads the checkpoints. - `.vscode/launch.json` is generated by the extension for the target-types and is not committed; after **Apply** it has a J-Link entry for the - DevKit-E8. That is expected. + DevKit-E8 or the AppKit-E8. That is expected. ## Read on @@ -156,6 +234,8 @@ Desktop running (the first run builds the image, about 100 MB). command-line flow, how the model is generated. - [board/DevKit-E8/README.md](board/DevKit-E8/README.md): the board layer, memory map and RTE configuration. +- [board/AppKit-E8/README.md](board/AppKit-E8/README.md): the AppKit-E8 + layer and what differs from the DevKit. - [documentation/mlops-flow.md](documentation/mlops-flow.md): the `mlops:` node and `*.cbuild-mlops.yml` in detail. - [documentation/pack-provenance.md](documentation/pack-provenance.md): where diff --git a/RTE/_Debug_AppKit-E8/Pre_Include_Global.h b/RTE/_Debug_AppKit-E8/Pre_Include_Global.h new file mode 100644 index 00000000..550f68bb --- /dev/null +++ b/RTE/_Debug_AppKit-E8/Pre_Include_Global.h @@ -0,0 +1,25 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.15.1+p3-gf46d68bf + * + * Project: 'cmsis-executorch.Debug+AppKit-E8' + * Target: 'Debug+AppKit-E8' + */ + +#ifndef PRE_INCLUDE_GLOBAL_H +#define PRE_INCLUDE_GLOBAL_H + +/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.26.2 */ +// enabling global pre includes + #define ETHOSU_ARCH u85 +/* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.5.1 */ +#define EXECUTORCH_BUILD_ARM_BAREMETAL 1 + #define ET_USE_ETHOS_U_BACKEND 1 +/* PyTorch::Machine Learning:ExecuTorch:Runtime@1.5.1 */ +/* ExecuTorch global configuration */ + #define C10_USING_CUSTOM_GENERATED_MACROS + #define FLATBUFFERS_MAX_ALIGNMENT 1024 + #define FLATBUFFERS_LOCALE_INDEPENDENT 0 + + +#endif /* PRE_INCLUDE_GLOBAL_H */ diff --git a/RTE/_Debug_AppKit-E8/RTE_Components.h b/RTE/_Debug_AppKit-E8/RTE_Components.h new file mode 100644 index 00000000..3f897d18 --- /dev/null +++ b/RTE/_Debug_AppKit-E8/RTE_Components.h @@ -0,0 +1,57 @@ +/* + * CSOLUTION generated file: DO NOT EDIT! + * Generated by: csolution version 2.15.1+p3-gf46d68bf + * + * Project: 'cmsis-executorch.Debug+AppKit-E8' + * Target: 'Debug+AppKit-E8' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "alif.h" + +/* ARM::CMSIS-Compiler:STDERR:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDERR /* CMSIS-Compiler STDERR */ +#define RTE_CMSIS_Compiler_STDERR_Custom /* CMSIS-Compiler STDERR: Custom */ +/* ARM::CMSIS-Compiler:STDIN:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDIN /* CMSIS-Compiler STDIN */ +#define RTE_CMSIS_Compiler_STDIN_Custom /* CMSIS-Compiler STDIN: Custom */ +/* ARM::CMSIS-Compiler:STDOUT:Custom@1.1.0 */ +#define RTE_CMSIS_Compiler_STDOUT /* CMSIS-Compiler STDOUT */ +#define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ +/* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.26.2 */ +#define RTE_ETHOS_U_CORE_DRIVER +/* AlifSemiconductor::BSP:External peripherals:ILI9806E LCD panel@2.2.0 */ +#define RTE_Drivers_MIPI_DSI_ILI9806E_PANEL /* Driver ILI9806E LCD panel*/ +/* AlifSemiconductor::CMSIS Driver:USART@2.2.0 */ +#define RTE_Drivers_USART /* Driver UART */ +/* AlifSemiconductor::Device:SOC Peripherals:CDC@2.2.0 */ +#define RTE_Drivers_CDC200 /* Driver CDC200*/ +/* AlifSemiconductor::Device:SOC Peripherals:GPIO@2.2.0 */ +#define RTE_Drivers_IO /* Driver GPIO */ +/* AlifSemiconductor::Device:SOC Peripherals:MIPI DSI CSI2 DPHY@2.2.0 */ +#define RTE_Drivers_MIPI_DSI_CSI2_DPHY /* Driver DPHY */ +/* AlifSemiconductor::Device:SOC Peripherals:MIPI DSI@2.2.0 */ +#define RTE_Drivers_MIPI_DSI /* Driver MIPI DSI */ +/* AlifSemiconductor::Device:SOC Peripherals:PINCONF@2.2.0 */ +#define RTE_Drivers_LL_PINCONF /* Driver PinPAD and PinMux */ +/* PyTorch::Machine Learning:ExecuTorch Operators:Quantized dequantize@1.5.1 */ +#define RTE_ML_EXECUTORCH_OP_QUANTIZED_DEQUANTIZE /* ExecuTorch op_dequantize */ +/* PyTorch::Machine Learning:ExecuTorch Operators:Quantized quantize@1.5.1 */ +#define RTE_ML_EXECUTORCH_OP_QUANTIZED_QUANTIZE /* ExecuTorch op_quantize */ +/* PyTorch::Machine Learning:ExecuTorch:Backend EthosU@1.5.1 */ +#define RTE_ML_EXECUTORCH_BACKEND_ETHOS_U /* ExecuTorch Ethos-U Backend (Cortex-M host) */ +/* PyTorch::Machine Learning:ExecuTorch:Kernel Registration@1.5.1 */ +#define RTE_ML_EXECUTORCH_KERNEL_REGISTRATION /* ExecuTorch Kernel Registration */ +/* PyTorch::Machine Learning:ExecuTorch:Kernel Utils@1.5.1 */ +#define RTE_ML_EXECUTORCH_KERNEL_UTILS /* ExecuTorch Kernel Utils */ +/* PyTorch::Machine Learning:ExecuTorch:Runtime@1.5.1 */ +#define RTE_ML_EXECUTORCH_RUNTIME /* ExecuTorch Runtime */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/RTE/_Debug_DevKit-E8/Pre_Include_Global.h b/RTE/_Debug_DevKit-E8/Pre_Include_Global.h index 1079a0a3..7e77b2f1 100644 --- a/RTE/_Debug_DevKit-E8/Pre_Include_Global.h +++ b/RTE/_Debug_DevKit-E8/Pre_Include_Global.h @@ -1,6 +1,6 @@ /* * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.15.1+p3-gf46d68bf + * Generated by: csolution version 2.14.1+p88-g94cb0c5e * * Project: 'cmsis-executorch.Debug+DevKit-E8' * Target: 'Debug+DevKit-E8' diff --git a/RTE/_Debug_DevKit-E8/RTE_Components.h b/RTE/_Debug_DevKit-E8/RTE_Components.h index c9c805b5..fad541d4 100644 --- a/RTE/_Debug_DevKit-E8/RTE_Components.h +++ b/RTE/_Debug_DevKit-E8/RTE_Components.h @@ -1,6 +1,6 @@ /* * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.15.1+p3-gf46d68bf + * Generated by: csolution version 2.14.1+p88-g94cb0c5e * * Project: 'cmsis-executorch.Debug+DevKit-E8' * Target: 'Debug+DevKit-E8' @@ -26,8 +26,18 @@ #define RTE_CMSIS_Compiler_STDOUT_Custom /* CMSIS-Compiler STDOUT: Custom */ /* ARM::Machine Learning:NPU Support:Ethos-U Driver&Generic U85@1.26.2 */ #define RTE_ETHOS_U_CORE_DRIVER +/* AlifSemiconductor::BSP:External peripherals:ILI9806E LCD panel@2.2.0 */ +#define RTE_Drivers_MIPI_DSI_ILI9806E_PANEL /* Driver ILI9806E LCD panel*/ /* AlifSemiconductor::CMSIS Driver:USART@2.2.0 */ #define RTE_Drivers_USART /* Driver UART */ +/* AlifSemiconductor::Device:SOC Peripherals:CDC@2.2.0 */ +#define RTE_Drivers_CDC200 /* Driver CDC200*/ +/* AlifSemiconductor::Device:SOC Peripherals:GPIO@2.2.0 */ +#define RTE_Drivers_IO /* Driver GPIO */ +/* AlifSemiconductor::Device:SOC Peripherals:MIPI DSI CSI2 DPHY@2.2.0 */ +#define RTE_Drivers_MIPI_DSI_CSI2_DPHY /* Driver DPHY */ +/* AlifSemiconductor::Device:SOC Peripherals:MIPI DSI@2.2.0 */ +#define RTE_Drivers_MIPI_DSI /* Driver MIPI DSI */ /* AlifSemiconductor::Device:SOC Peripherals:PINCONF@2.2.0 */ #define RTE_Drivers_LL_PINCONF /* Driver PinPAD and PinMux */ /* PyTorch::Machine Learning:ExecuTorch Operators:Quantized dequantize@1.5.1 */ diff --git a/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h b/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h index 83d53110..59d04942 100644 --- a/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h +++ b/RTE/_Debug_SSE-320-U85/Pre_Include_Global.h @@ -1,6 +1,6 @@ /* * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.14.1+p38-gf512b381 + * Generated by: csolution version 2.14.1+p88-g94cb0c5e * * Project: 'cmsis-executorch.Debug+SSE-320-U85' * Target: 'Debug+SSE-320-U85' diff --git a/RTE/_Debug_SSE-320-U85/RTE_Components.h b/RTE/_Debug_SSE-320-U85/RTE_Components.h index a80a87c2..46fb28de 100644 --- a/RTE/_Debug_SSE-320-U85/RTE_Components.h +++ b/RTE/_Debug_SSE-320-U85/RTE_Components.h @@ -1,6 +1,6 @@ /* * CSOLUTION generated file: DO NOT EDIT! - * Generated by: csolution version 2.14.1+p38-gf512b381 + * Generated by: csolution version 2.14.1+p88-g94cb0c5e * * Project: 'cmsis-executorch.Debug+SSE-320-U85' * Target: 'Debug+SSE-320-U85' diff --git a/ai_layer/ai_layer.clayer.yml b/ai_layer/ai_layer.clayer.yml index 87928945..78a4ebb7 100644 --- a/ai_layer/ai_layer.clayer.yml +++ b/ai_layer/ai_layer.clayer.yml @@ -3,13 +3,14 @@ # model/model.py or the csolution's mlops: node. layer: type: AI - description: TinyCNN int8 image classifier for Ethos-U85 + description: pico-faces rectified-flow face generator for Ethos-U85 packs: - pack: PyTorch::ExecuTorch@1.5.1 define: - - ET_LOG_ENABLED: 0 + - ET_LOG_ENABLED: 1 + - ET_MIN_LOG_LEVEL: Error add-path: - . @@ -23,7 +24,8 @@ layer: - component: Machine Learning:ExecuTorch Operators:Quantized quantize groups: - - group: TinyCNN + - group: PicoFaces files: - file: ./model_pte.c - file: ./model_pte.h + - file: ./model_params.h diff --git a/ai_layer/model_params.h b/ai_layer/model_params.h new file mode 100644 index 00000000..0f29e3b7 --- /dev/null +++ b/ai_layer/model_params.h @@ -0,0 +1,758 @@ +// Generated by create_ai_layer.py from get_params() in model/model.py -- do not edit. +#pragma once + +#define PF_VARIANT "m3_long_cfg" +#define PF_QUANT "a16w8/a8w8" +#define PF_LATENT_CH 8 +#define PF_LATENT_HW 16 +#define PF_IMG_CH 3 +#define PF_IMG_HW 128 +#define PF_COND_DIM 128 +#define PF_N_CLASSES 4 +#define PF_NULL_CLASS 4 +#define PF_N_COND 5 +#define PF_K_MAX 8 +#define PF_N_CFG_W 3 +#define PF_MACS_DIT_STEP 110862336 +#define PF_MACS_DECODE 108527616 + +static const float pf_schedule[8] = { + 1.0f, 0.875f, 0.75f, 0.625f, 0.5f, 0.375f, 0.25f, 0.125f, +}; + +static const float pf_cfg_w[3] = { + 4.0f, 6.0f, 8.0f, +}; + +static const float pf_cond[5][8][128] = { + { + { + -1.19943476f, 0.103804976f, 0.136562869f, 0.403869957f, 0.112720974f, -1.13884139f, 0.175973892f, 0.219021901f, + -0.366773665f, 0.363391578f, 0.106817655f, 0.169369102f, 0.117557563f, 0.504136026f, -0.793248951f, 0.0114166802f, + -1.42425156f, -1.36040747f, 0.0925844833f, 0.0984721407f, 0.003575827f, 0.0365800671f, -4.30147552f, -0.947152913f, + 0.0721685141f, 0.0133737717f, -1.3378737f, 0.197082728f, 0.130707085f, -0.0264369529f, -0.0763685182f, -2.0532577f, + -0.882606864f, -2.86364627f, 0.120616429f, 0.0352996439f, 0.150541902f, 0.113137662f, 0.434817314f, 0.33688271f, + 0.036307428f, 0.00746208709f, 0.547157764f, 0.131747246f, 0.150908291f, -0.0414705202f, -1.45441914f, 0.0722233504f, + -0.487728715f, -0.148328811f, 0.200003564f, 0.474228591f, 0.0650881529f, 0.290172786f, -0.64867115f, -0.767971516f, + -3.74440336f, 1.27137351f, 0.290956557f, -3.26415229f, -0.636946321f, -3.2702086f, -0.750864208f, 0.0513311028f, + -0.590332985f, -1.8723588f, -2.5208509f, -0.150209546f, -3.35050535f, 0.0272536464f, 0.267508298f, -3.03893185f, + 0.111210436f, -0.646374881f, -3.85108638f, 0.00211119256f, -0.040174637f, -0.0211010128f, -3.079283f, 0.163860261f, + -1.53392673f, 0.0662775487f, -0.0361811444f, 0.0857123062f, -0.0379347652f, -3.78045321f, 1.04540241f, -3.58954859f, + -0.0510729365f, -3.58284926f, -3.40466928f, -3.67499018f, -0.104160056f, 1.0210427f, -0.504254699f, 0.104930371f, + 0.25771746f, -0.655095398f, 0.130081698f, 0.0681628212f, -3.2069695f, 0.18854633f, 0.0887730718f, 0.0722799748f, + -3.62117219f, 0.0174629018f, 0.119293101f, 0.147289991f, -0.115880363f, -3.6998744f, 0.172605276f, 0.294987053f, + 0.0140887611f, -2.49925494f, -3.44129729f, -1.28066111f, 0.169725671f, 0.0412407033f, -3.86365557f, 0.106899887f, + 0.033371266f, 0.0592505038f, -1.15162563f, 0.944659948f, -1.53378415f, -0.227571309f, -0.86935097f, 0.125859171f, + }, + { + -1.99555886f, 0.0684241056f, 0.100649126f, 0.475992501f, 0.228917629f, -1.37176812f, 0.259257257f, 0.24150756f, + -0.80439508f, 0.222720787f, 0.116660021f, 0.118016675f, 0.460731655f, -0.378264725f, -0.657062829f, 0.0638025478f, + -1.85027575f, -1.5713402f, 0.0862455741f, 0.139232665f, 0.0168564692f, -0.0448916107f, -6.3716054f, -1.57054615f, + 0.0924993977f, -0.030783534f, -2.9001689f, 0.168514654f, -2.95282936f, -0.293023467f, -0.0310602318f, -3.84112906f, + -0.854857206f, -5.46087456f, 0.133061111f, 0.125418067f, 0.265927732f, 0.0870344043f, -0.163001329f, 0.193304658f, + 0.102037698f, -0.0882560238f, 0.077583313f, 0.219638482f, 0.218367785f, -0.0167177487f, -1.32055056f, 0.00690719485f, + -1.09532595f, -0.221847981f, 0.101478428f, 0.662873566f, 0.201987758f, 0.254007816f, -0.773212671f, -0.937352061f, + -6.27132416f, 1.85911012f, 0.556967497f, -5.2236886f, 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0x65, 0x22, 0x3a, 0x20, 0x22, 0x62, 0x75, 0x69, 0x6c, 0x74, 0x69, - 0x6e, 0x73, 0x2e, 0x64, 0x69, 0x63, 0x74, 0x22, 0x2c, 0x20, 0x22, 0x63, 0x6f, 0x6e, 0x74, 0x65, - 0x78, 0x74, 0x22, 0x3a, 0x20, 0x22, 0x5b, 0x5d, 0x22, 0x2c, 0x20, 0x22, 0x63, 0x68, 0x69, 0x6c, - 0x64, 0x72, 0x65, 0x6e, 0x5f, 0x73, 0x70, 0x65, 0x63, 0x22, 0x3a, 0x20, 0x5b, 0x5d, 0x7d, 0x5d, - 0x7d, 0x5d, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x66, 0x6f, 0x72, 0x77, 0x61, 0x72, 0x64, 0x00 +#if __has_include("model_pte_data.inc") +__attribute__((aligned(16), section(".rodata.model"))) const unsigned char model_pte[] = { +#include "model_pte_data.inc" }; const unsigned long model_pte_size = sizeof(model_pte); +#else +#error "model_pte_data.inc is missing: run the task 'Create AI layer' (python create_ai_layer.py .cbuild-mlops.yml)" +#endif diff --git a/board/AppKit-E8/AppKit-E8.h b/board/AppKit-E8/AppKit-E8.h new file mode 100644 index 00000000..0d3b05ca --- /dev/null +++ b/board/AppKit-E8/AppKit-E8.h @@ -0,0 +1,37 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2025-2026 Arm Limited (or its affiliates). + * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * CMSIS target header for the AppKit-E8 layer: only the USART used + * for stdio. See the pack's Boards/AppKit-e8/board_defs.h for + * the full board pin-out; SW4 in position UART4 routes it to PRG USB. + *---------------------------------------------------------------------------*/ + +#ifndef APPKIT_E8_H_ +#define APPKIT_E8_H_ + +#include "Driver_USART.h" + +// CMSIS Driver instances of Board peripherals +#define CMSIS_DRIVER_USART 4 // CMSIS Driver USART instance number (PRG USB) + +// Retarget stdio to CMSIS UART +#define RETARGET_STDIO_UART 4 + +// CMSIS Drivers +extern ARM_DRIVER_USART Driver_USART4; /* PRG USB */ + +#endif /* APPKIT_E8_H_ */ diff --git a/board/AppKit-E8/Board-U85.clayer.yml b/board/AppKit-E8/Board-U85.clayer.yml new file mode 100644 index 00000000..efad53dd --- /dev/null +++ b/board/AppKit-E8/Board-U85.clayer.yml @@ -0,0 +1,128 @@ +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +# +# Alif Ensemble E8 AI/ML AppKit board bring-up for the Ethos-U85 NPU, running +# on the Cortex-M55 high-performance (HP) core. The AppKit carries the same E8 +# die as the DevKit in another package (AE822FA0E5597BS0, WLCSP), with the +# 4.3" ILI9806E panel soldered on instead of on a connector, the same UART4 +# console on the PRG USB connector (SW4 in position UART4) and the same +# five-way joystick on LPGPIO. Everything this example touches sits on the +# same pins and addresses, so this layer is the DevKit-E8 layer with the +# AppKit's board support (BSP:AppKit Config, the pack's Boards/AppKit-e8 +# Conductor files) and its own RTE configuration; the board sources and the +# linker scripts are shared with ../DevKit-E8. The pack ships no Board layer +# or examples for the AppKit-E8. +layer: + type: Board + description: AppKit-E8 board setup for Ethos-U85 inference on M55_HP with the LCD + for-board: Alif Semiconductor::AppKit-E8-AIML + for-device: Alif Semiconductor::AE822FA0E5597BS0:M55_HP + device: :M55_HP + + processor: + trustzone: off + + connections: + - connect: AppKit-E8 Board + provides: + - STDIN + - STDOUT + - STDERR + - Heap: 98304 + + define: + - CMSIS_target_header: \"AppKit-E8.h\" + - ETHOSU85 + # The runner's memory pools (src/app_main.cpp) do not fit the 1 MB DTCM + # that the Alif linker scripts use for .bss. Place them in the bulk SRAM0 + # (4 MB at 0x02000000, NPU-accessible) via the section named here; the + # linker scripts route the section there, above the A32 boot stub and next + # to the 1.15 MB LCD frame buffer. The temp pool holds the Ethos-U scratch + # of the decoder. Same layout as the DevKit-E8 layer. + - APP_POOL_SECTION: \".bss.ai_pool\" + - APP_METHOD_POOL_SIZE: 0x100000 + - APP_TEMP_POOL_SIZE: 0x180000 + # After the boot demo the runner keeps serving pico-faces' serial protocol + # on the console, for pico-faces' viewer/view_serial.py (APP_INTERACTIVE), + # and generates new faces on the joystick: left, one image; right, start + # or stop back-to-back generation (APP_BUTTONS, ../DevKit-E8/buttons.c). + - APP_INTERACTIVE + - APP_BUTTONS + # Every generated image is shown on the LCD (board_display_image(), + # ../DevKit-E8/display.c). + - APP_DISPLAY + + packs: + - pack: AlifSemiconductor::Ensemble@^2.2.0-0 + - pack: ARM::CMSIS@^6.2.0 + - pack: ARM::CMSIS-Compiler@^2.1.0 + - pack: ARM::ethos-u-core-driver@^1.26.2 + + misc: + - for-compiler: AC6 + Link: + - '--diag_suppress 6312,6314,6329,6848' + + components: + - component: Device:Startup + + - component: BSP:Board Config + # The AppKit's Conductor files (board_defs.h, pins.h, gpios.h) from the + # pack's Boards/AppKit-e8; the DevKit layer uses BSP:DevKit Config. + - component: BSP:AppKit Config&AppKit-E8-AIML + + - component: CMSIS:CORE + + - component: CMSIS Driver:USART + + - component: CMSIS-Compiler:CORE + - component: CMSIS-Compiler:STDERR:Custom + - component: CMSIS-Compiler:STDIN:Custom + - component: CMSIS-Compiler:STDOUT:Custom + + - component: Device:SOC Peripherals:MHU + - component: Device:SOC Peripherals:PINCONF + + # Display: CDC200 controller, 2-lane MIPI DSI + DPHY, the ILI9806E panel of + # the AppKit (480 x 800), GPIO for the panel reset and backlight + - component: Device:SOC Peripherals:CDC + - component: Device:SOC Peripherals:MIPI DSI + - component: Device:SOC Peripherals:MIPI DSI CSI2 DPHY + - component: Device:SOC Peripherals:GPIO + - component: BSP:External peripherals:ILI9806E LCD panel + + - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U85 + + - component: Services:Retarget IO:STDERR + - component: Services:Retarget IO:STDIN + - component: Services:Retarget IO:STDOUT + - component: Services:Secure Enclave:core&Source + - component: Services:Secure Enclave:Initialization Helper&Source + + # The board sources are shared with the DevKit-E8 layer: the console UART, + # the joystick, the display and the NPU are wired the same on both boards. + groups: + - group: Board + files: + - file: ../DevKit-E8/main.c + - file: ../DevKit-E8/main.h + - file: ./AppKit-E8.h + - file: ../DevKit-E8/ethos_setup.c + - file: ../DevKit-E8/retarget_stdio.c + - file: ../DevKit-E8/display.c + - file: ../DevKit-E8/buttons.c + + - group: Ethos Interface + files: + - file: ../DevKit-E8/ethosu_cb_dcache.c + + # The DevKit layer's linker scripts (the pack's plus the .bss.ai_pool section + # in bulk SRAM and a 32 kB main stack) with this layer's memory regions. + linker: + - regions: ./RTE/Device/AE822FA0E5597BS0_M55_HP/app_mem_regions.h + - script: ../DevKit-E8/linker_ac6_mram.sct.src + for-compiler: AC6 + - script: ../DevKit-E8/linker_gnu_mram.ld.src + for-compiler: GCC + - script: ../DevKit-E8/linker_gnu_mram.ld.src + for-compiler: CLANG diff --git a/board/AppKit-E8/README.md b/board/AppKit-E8/README.md new file mode 100644 index 00000000..9590a3d4 --- /dev/null +++ b/board/AppKit-E8/README.md @@ -0,0 +1,63 @@ +# Board layer: Alif Ensemble E8 AI/ML AppKit (M55_HP + Ethos-U85) + +Device: `Alif Semiconductor::AE822FA0E5597BS0:M55_HP` (Cortex-M55 high-performance +core, 400 MHz) with the Ethos-U85 (256 MACs) of the Ensemble E8. Board +`Alif Semiconductor::AppKit-E8-AIML` in the Ensemble pack. + +The AppKit carries the E8 die of the DevKit in the 216-ball WLCSP package +(the DevKit's `AE822FA0E5597LS0` is the 194-ball FBGA): the same cores, NPU, +5.5 MB MRAM and 9.75 MB SRAM. The pack ships a board entry and the +Conductor configuration for it (`Boards/AppKit-e8/board_defs.h`, `pins.h`, +`gpios.h`, through the component `BSP:AppKit Config&AppKit-E8-AIML`), but no +Board layer and no examples. This layer is therefore the +[DevKit-E8 layer](../DevKit-E8/README.md) with the AppKit's board support: +everything the face generator uses is wired the same on both boards. + +| | DevKit-E8 | AppKit-E8 | +|---|---|---| +| Console | UART4 on P12_1/P12_2 to the PRG USB (USB-C) bridge, SW4 = `UART4` | UART4 on the same pins to the PRG USB (Micro-USB) bridge, SW4 = `UART4` (SW4 also has `UART2` for the HE core) | +| Debug | J-Link OB on PRG USB, SWD 4 MHz | same | +| Display | 4.3" ILI9806E 480 x 800 on MIPI-DSI connector J21, CDC200, backlight GPIO6_1 | the same panel soldered on, same controller and pins; capacitive touch (GT911, unused) | +| Joystick | SW2, five-way on LPGPIO pins 0-4 | five-way joystick on the same LPGPIO pins | +| LEDs | 2 RGB | 1 RGB (unused) | +| Not on the AppKit | | Ethernet, mikroBUS, the 2x20 headers, ADC/CMP/DAC, I2C/SPI headers | + +| File | Purpose | +|------|---------| +| `Board-U85.clayer.yml` | Layer: startup, SE services, UART4 stdio, Ethos-U85 driver, display, memory placement; `BSP:AppKit Config` instead of `BSP:DevKit Config` | +| `AppKit-E8.h` | CMSIS target header: the USART instance of the console | +| `RTE/` | Configuration files carried with the layer, named after the BS0 part (see below) | +| `../DevKit-E8/*.c`, `*.h`, `linker_*.src` | The board sources and linker scripts, shared with the DevKit-E8 layer | + +The `define:` node sets the same pools, sections, `APP_DISPLAY`, +`APP_INTERACTIVE` and `APP_BUTTONS` as the DevKit layer; see +[its README](../DevKit-E8/README.md) for the memory layout, the SRAM1 and +Secure Enclave run-profile notes and the serial protocol. They apply +unchanged. + +## RTE configuration + +The RTE directories are named after the device, so this layer carries its +own copies under `AE822FA0E5597BS0_M55_HP`. The `Device/` and `Services/` +files are the same pack files for both parts (the pack's condition is the +SoC, `AE822FA0E5597*`), copied from the DevKit layer with its edits: +`RTE_UART4_BLOCKING_MODE_ENABLE 1` in `RTE_Device.h` (Alif's stdio retarget +needs polling mode) and the memory regions in `app_mem_regions.h` (the HP +MRAM region extended to 3.4375 MB for the model, the pools above the A32 +boot stub in SRAM0, `SRAM0_SRAM1_COMBINED 0`, 96 kB heap). The `BSP/` files +are the pack's AppKit-e8 Conductor configuration, unchanged. + +## STDIO + +UART4 on the PRG USB connector (Micro-USB), 115200 baud. Set **SW4 to UART4** +(the bottom position); the top position **SEUART** routes the same USB serial +port to the Secure Enclave for SETOOLS, the middle one to UART2. + +## Before the first debug session + +Program the debug stubs into the device's ATOC with Alif SETOOLS once: +**Terminal > Run Task > Alif: Install M55_HP debug stubs (AppKit-E8, single core configuration)**. +It is the DevKit task with the AppKit's part, `E8 (AE822FA0E5597BS0) - 5.5 +MRAM / 9.75 SRAM`; the ATOC configuration and the HP stub in `.alif/` are the +same. The task needs the VS Code setting `alif.setools.root` and SW4 in +position SEUART. See [the getting-started README](../../README.md). diff --git a/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/board_defs.h b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/board_defs.h new file mode 100644 index 00000000..fc640b0a --- /dev/null +++ b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/board_defs.h @@ -0,0 +1,1369 @@ +/* + * Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ + */ +/****************************************************************************** + * @file board_defs.h + * @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ + * @version v1.0.0 + * @date 2025-10-29 + * @brief Board info/settings for "AppKit-e8" project + * with AE822FA0E5597 + * @bug None. + * @note To modify this file manually, take care to modify pins.h and gpios.h + * accordingly when required. + ******************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + +/* + * ----------------------------------------------------------------------------- + * Board Feature Support Notes for Appkit-E8 + * ----------------------------------------------------------------------------- + * - ADC, HSCMP, LPCMP, DAC12, I2C/LPI2C, LPUART, QEC and SPI/LPSPI are + * **not supported** on the Appkit-E8 board due to unavailable pinouts. + * + * - LED: + * • Only LED0 is available. + * + * - PDM: + * • Only channels 4 and 5 are supported. + * Other PDM channels are not available on this board. + * + * - LPPDM: + * • Only channels 0 and 1 are supported. + * + * - I2S: + * • I2S microphones are not available on the Appkit-E8 board. + * To test I2S functionality, use predefined audio samples as input + * and route the output through the codec. + * + * - UTIMER: + * • Only Basic and Buffer modes are supported. Trigger, Capture and Compare + * modes are not supported due to unavailable pinouts. + * + * ----------------------------------------------------------------------------- + */ + +// Board peripheral instances +// CANFD module enabled flag +#define BOARD_CANFD_ENABLED 1 +// "CAN Transceiver" on CANFD presence flag +#define BOARD_CANFD_CAN_TRANSCEIVER_PRESENT 1 +// +// + +// CSI module enabled flag +#define BOARD_CSI_ENABLED 1 +// "ARX3A0" on CSI presence flag +#define BOARD_CSI_ARX3A0_PRESENT 1 +// +// "AR0144" on CSI presence flag +#define BOARD_CSI_AR0144_PRESENT 1 +// +// + +// DSI module enabled flag +#define BOARD_DSI_ENABLED 1 +// "ILI9806" on DSI presence flag +#define BOARD_DSI_ILI9806_PRESENT 1 +// +// + +// Select MIPI display by default +#define BOARD_CONFIGURE_LVDS_MUX 1 + +// ETH module enabled flag +#define BOARD_ETH_ENABLED 1 +// "RTL8201" on ETH presence flag +#define BOARD_ETH_RTL8201_PRESENT 1 +// +// + +// "Camera" I2C instance number <0-3> +#define BOARD_CAMERA_I2C_INSTANCE 1 + +// "GT911 Touchscreen" I2C instance number <0-3> +#define BOARD_GT911_TOUCHSCREEN_I2C_INSTANCE 1 + +// I3C module enabled flag +#define BOARD_I3C_ENABLED 1 + +// "FLEXIO" on I3C presence flag +#define BOARD_I3C_FLEXIO_PRESENT 1 +// "ICM42670 IMU" on I3C presence flag +#define BOARD_I3C_ICM42670_IMU_PRESENT 1 +// +// "BMI323 IMU" on I3C presence flag +#define BOARD_I3C_BMI323_IMU_PRESENT 1 +// +// "pin header" on I3C presence flag +#define BOARD_I3C_PIN_HEADER_PRESENT 1 +// +// + +// JTAG module enabled flag +#define BOARD_JTAG_ENABLED 1 +// + +// LPCPI module enabled flag +#define BOARD_LPCPI_ENABLED 1 +// + +// LPGPIO module enabled flag +#define BOARD_LPGPIO_ENABLED 1 +// + +// LPPDM module enabled flag +#define BOARD_LPPDM_ENABLED 1 +// + +// MISC module enabled flag +#define BOARD_MISC_ENABLED 1 +// + +// PDM module enabled flag +#define BOARD_PDM_ENABLED 1 +// "PDM MIC" on PDM presence flag +#define BOARD_PDM_PDM_MIC_PRESENT 1 +// +// + +// "Encoder" UTIMER instance number <12-15> +#define BOARD_ENCODER_UTIMER_INSTANCE 12 + +// SDMMC module enabled flag +#define BOARD_SDMMC_ENABLED 1 +// "SDCARD" on SDMMC presence flag +#define BOARD_SDMMC_SDCARD_PRESENT 1 +// +// + +// SEUART module enabled flag +#define BOARD_SEUART_ENABLED 1 +// + +// "Clickboard" UART instance number <0-7> +#define BOARD_CLICKBOARD_UART_INSTANCE 0 + +// "UARTA" UART instance number <0-7> +#define BOARD_UARTA_UART_INSTANCE 2 + +// "UARTB" UART instance number <0-7> +#define BOARD_UARTB_UART_INSTANCE 4 + +// USB module enabled flag +#define BOARD_USB_ENABLED 1 +// "Device Role" on USB presence flag +#define BOARD_USB_DEVICE_ROLE_PRESENT 1 +// +// + +// "Basic Mode" UTIMER instance number <0-12> +#define BOARD_BASIC_MODE_UTIMER_INSTANCE 0 + +// "Buffer Mode" UTIMER instance number <0-12> +#define BOARD_BUFFER_MODE_UTIMER_INSTANCE 1 + +// "Clickboard PWM" UTIMER instance number <0-12> +#define BOARD_CLICKBOARD_PWM_UTIMER_INSTANCE 3 + +// Utimer 250ms counter value +#define BOARD_UTIMER_250_MILLI_SEC_COUNTER_VALUE 100000000 + +// Utimer 500ms counter value +#define BOARD_UTIMER_500_MILLI_SEC_COUNTER_VALUE 200000000 + +// Utimer 750ms counter value +#define BOARD_UTIMER_750_MILLI_SEC_COUNTER_VALUE 300000000 + +// Utimer 1000ms counter value +#define BOARD_UTIMER_1000_MILLI_SEC_COUNTER_VALUE 400000000 + +// Utimer 1500ms counter value +#define BOARD_UTIMER_1500_MILLI_SEC_COUNTER_VALUE 600000000 + +// LED PWM utimer max counter value +#define BOARD_LED_PWM_UT_MAX_COUNTER_VALUE 240000 + +// "RED_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_RED_LED_UTIMER_COUNTER_TYPE 1 + +// "GREEN_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_GREEN_LED_UTIMER_COUNTER_TYPE 0 + +// "BLUE_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_BLUE_LED_UTIMER_COUNTER_TYPE 0 + +// UTIMER channel red LED instance number <9> +#define BOARD_RED_LED_UTIMER_INSTANCE 9 + +// UTIMER channel green LED instance number <10> +#define BOARD_GREEN_LED_UTIMER_INSTANCE 10 + +// UTIMER channel blue LED instance number <8> +#define BOARD_BLUE_LED_UTIMER_INSTANCE 8 + +// +// Miscellaneous +// Onboard LEDs +// Sets the #define BOARD_LED_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_LED_COUNT 0 + +// Onboard RGB LEDs +// Sets the #define BOARD_LEDRGB_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_LEDRGB_COUNT 1 + +// Onboard Push-buttons +// Sets the #define BOARD_BUTTON_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_BUTTON_COUNT 5 + +// Onboard Config Switches or Jumpers +// Sets the #define BOARD_CONFIG_JUMPER_COUNT in the board_def.h file exported from the +// Conductor tool. +#define BOARD_CONFIG_JUMPER_COUNT 0 + +// Onboard Switching Devices +// Sets the #define BOARD_SWITCH_OUTPUT_COUNT in the board_def.h file exported from the +// Conductor tool. These include relays, solid state relays, transistors, optocopulers, etc. +#define BOARD_SWITCH_OUTPUT_COUNT 0 + +// OSPI0 Bus Speed +// Selects OSPI0 bus speed for a 200-MHz (default) HCLK. For 100 MHz and lower HCLK clock +// speeds, some values are either not possible, either rounded to the closest possible value in +// hardware. +#define BOARD_OSPI0_BUS_SPEED 100000000 + +// OSPI1 Bus Speed +// Selects OSPI1 bus speed for a 200-MHz (default) HCLK. For 100 MHz and lower HCLK clock +// speeds, some values are either not possible, either rounded to the closest possible value in +// hardware. +#define BOARD_OSPI1_BUS_SPEED 100000000 + +// OSPI0 onboard memory size +#define BOARD_OSPI0_MEM_SIZE 33554432 + +// OSPI1 onboard memory size +#define BOARD_OSPI1_MEM_SIZE 33554432 + +// Number of CH201 sensors +#define BOARD_CH201_MAX_NUM_SENSORS 1 + +// Number of CH201 buses +#define BOARD_CH201_NUM_BUSES 1 + +// Number of CH201 interrupt pins +#define BOARD_CH201_SENSOR_INT_PIN 1 + +// Number of CH201 trigger pins +#define BOARD_CH201_SENSOR_TRIG_PIN 1 + +// CH201 TOF PROG pin GPIO port number +#define BOARD_CH201_SENSOR_PROG_IO_PORT 6 + +// CH201 TOF PROG pin number +#define BOARD_CH201_SENSOR_PROG_PIN_NO 2 + +// CH201 TOF INT pin GPIO port numbet +#define BOARD_CH201_SENSOR_INT_IO_PORT 6 + +// CH201 TOF INT pin number +#define BOARD_CH201_SENSOR_INT_PIN_NO 3 + +// CH201 TOF RESET pin GPIO port number +#define BOARD_CH201_SENSOR_RESET_IO_PORT 6 + +// CH201 TOF RESET pin number range +#define BOARD_CH201_SENSOR_RESET_PIN_NO 4 + +// +// GPIO port/pin numbers, analog instance/input numbers, etc. +// FLEX IO pins supply voltage <0=> 3.3 V <1=> 1.8 V +// Make sure this setting corresponds to the VDD_IO_FLEX pin voltage. If the VDD_IO_FLEX pin is +// connected to a 3.3 V supply, do not change the value of the GPIO_CNTL register to command 1.8-V +// operation mode! +#define FLEX_IO_VOLTAGE_1V8 1 + +// "SD_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_RESET_GPIO_PORT 14 +// "SD_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_RESET_GPIO_PIN 7 + +// "SD_CARD_DETECT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CARD_DETECT_GPIO_PORT 3 +// "SD_CARD_DETECT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SD_CARD_DETECT_GPIO_PIN 3 + +// "SD_CMD_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CMD_A_GPIO_PORT 7 +// "SD_CMD_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_CMD_A_GPIO_PIN 0 +// "SD_CMD_A" GPIO pin alternate function <0-7> +#define BOARD_SD_CMD_ALTERNATE_FUNCTION 6 + +// "SD_CLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CLK_A_GPIO_PORT 7 +// "SD_CLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_CLK_A_GPIO_PIN 1 +// "SD_CLK_A" GPIO pin alternate function <0-7> +#define BOARD_SD_CLK_ALTERNATE_FUNCTION 6 + +// "SD_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D0_A_GPIO_PORT 5 +// "SD_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D0_A_GPIO_PIN 0 +// "SD_D0_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D0_ALTERNATE_FUNCTION 7 + +// "SD_D1_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D1_A_GPIO_PORT 5 +// "SD_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D1_A_GPIO_PIN 1 +// "SD_D1_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D1_ALTERNATE_FUNCTION 7 + +// "SD_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D2_A_GPIO_PORT 5 +// "SD_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D2_A_GPIO_PIN 2 +// "SD_D2_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D2_ALTERNATE_FUNCTION 7 + +// "SD_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D3_A_GPIO_PORT 5 +// "SD_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D3_A_GPIO_PIN 3 +// "SD_D3_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D3_ALTERNATE_FUNCTION 6 + +// "SD_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D4_A_GPIO_PORT 5 +// "SD_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D4_A_GPIO_PIN 4 + +// "SD_D5_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D5_A_GPIO_PORT 5 +// "SD_D5_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D5_A_GPIO_PIN 5 + +// "SD_D6_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D6_A_GPIO_PORT 5 +// "SD_D6_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D6_A_GPIO_PIN 6 + +// "SD_D7_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D7_A_GPIO_PORT 5 +// "SD_D7_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D7_A_GPIO_PIN 7 + +// "LPPDM_TEST" LPPDM data/clock pair number <0=> D0/C0 <1=> D1/C1 <2=> D2/C2 <3=> D3/C3 +#define BOARD_LPPDM_TEST_LPPDM_INPUT 1 + +// "LPPDM_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D0_GPIO_PORT 3 +// "LPPDM_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D0_GPIO_PIN 5 +// "LPPDM_D0_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D0_ALTERNATE_FUNCTION 3 + +// "LPPDM_D1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D1_GPIO_PORT 3 +// "LPPDM_D1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D1_GPIO_PIN 7 +// "LPPDM_D1_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D1_ALTERNATE_FUNCTION 3 + +// "LPPDM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D2_GPIO_PORT 11 +// "LPPDM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D2_GPIO_PIN 6 +// "LPPDM_D2_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D2_ALTERNATE_FUNCTION 3 + +// "LPPDM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D3_GPIO_PORT 7 +// "LPPDM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D3_GPIO_PIN 7 +// "LPPDM_D3_A" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D3_ALTERNATE_FUNCTION 4 + +// "LPPDM_C0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C0_GPIO_PORT 3 +// "LPPDM_C0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C0_GPIO_PIN 4 +// "LPPDM_C0_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C0_ALTERNATE_FUNCTION 3 + +// "LPPDM_C1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C1_GPIO_PORT 3 +// "LPPDM_C1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C1_GPIO_PIN 6 +// "LPPDM_C1_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C1_ALTERNATE_FUNCTION 3 + +// "LPPDM_C2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C2_GPIO_PORT 11 +// "LPPDM_C2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C2_GPIO_PIN 2 +// "LPPDM_C2_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C2_ALTERNATE_FUNCTION 3 + +// "LPPDM_C3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C3_GPIO_PORT 7 +// "LPPDM_C3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C3_GPIO_PIN 6 +// "LPPDM_C3_A" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C3_ALTERNATE_FUNCTION 4 + +// "PDM_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D0_A_GPIO_PORT 3 +// "PDM_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D0_A_GPIO_PIN 4 + +// "PDM_D1_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D1_C_GPIO_PORT 6 +// "PDM_D1_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D1_C_GPIO_PIN 2 + +// "PDM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D2_B_GPIO_PORT 5 +// "PDM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D2_B_GPIO_PIN 4 + +// "PDM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D3_A_GPIO_PORT 5 +// "PDM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D3_A_GPIO_PIN 1 + +// "PDM_C0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C0_A_GPIO_PORT 3 +// "PDM_C0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C0_A_GPIO_PIN 5 + +// "PDM_C1_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C1_C_GPIO_PORT 6 +// "PDM_C1_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C1_C_GPIO_PIN 3 + +// "PDM_C2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C2_A_GPIO_PORT 6 +// "PDM_C2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C2_A_GPIO_PIN 7 + +// "PDM_C3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C3_A_GPIO_PORT 5 +// "PDM_C3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C3_A_GPIO_PIN 2 + +// "TOUCH_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_TOUCH_RESET_GPIO_PORT 6 +// "TOUCH_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_TOUCH_RESET_GPIO_PIN 5 + +// "PDM_MIC" PDM data/clock pair number <0=> D0/C0 <1=> D1/C1 <2=> D2/C2 <3=> D3/C3 +#define BOARD_PDM_MIC_PDM_INPUT 2 + +// "LCD_BACKLIGHT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LCD_BACKLIGHT_GPIO_PORT 6 +// "LCD_BACKLIGHT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 1 + +// The pack's ILI9806E panel driver (components/Source/ILI9806E_LCD_panel.c) +// drives the backlight through BOARD_LCD_BL_LED_GPIO_*, which the Conductor +// file of the DevKit-e8 defines next to BOARD_LCD_BACKLIGHT_GPIO_* (same pin) +// and the AppKit-e8 one does not. Added for the CMSIS-Executorch AppKit-E8 +// layer: the backlight enable of the on-board panel, GPIO6_1 as above. +#define BOARD_LCD_BL_LED_GPIO_PORT BOARD_LCD_BACKLIGHT_GPIO_PORT +#define BOARD_LCD_BL_LED_GPIO_PIN BOARD_LCD_BACKLIGHT_GPIO_PIN + +// "CAN_RXD" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_RXD_GPIO_PORT 12 +// "CAN_RXD_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_RXD_GPIO_PIN 4 +// "CAN_RXD" GPIO pin alternate function <0-7> +#define BOARD_CAN_RXD_ALTERNATE_FUNCTION 4 + +// "CAN_TXD" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_TXD_GPIO_PORT 12 +// "CAN_TXD" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_TXD_GPIO_PIN 5 +// "CAN_TXD" GPIO pin alternate function <0-7> +#define BOARD_CAN_TXD_ALTERNATE_FUNCTION 4 + +// "CAN_STBY" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_STBY_GPIO_PORT 12 +// "CAN_STBY" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_STBY_GPIO_PIN 6 +// "CAN_STBY" GPIO pin alternate function <0-7> +#define BOARD_CAN_STBY_ALTERNATE_FUNCTION 4 + +// "CAM_XVCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_XVCLK_A_GPIO_PORT 0 +// "CAM_XVCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_XVCLK_A_GPIO_PIN 3 + +// "CAMERA_POWER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_POWER_GPIO_PORT 7 +// "CAMERA_POWER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_POWER_GPIO_PIN 5 + +// "I2C1_SDA_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_I2C_SDA_GPIO_PORT 7 +// "I2C1_SDA_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAMERA_I2C_SDA_GPIO_PIN 2 +// "I2C1_SDA_C" GPIO pin alternate function <0-7> +#define BOARD_CAMERA_I2C_SDA_ALTERNATE_FUNCTION 5 + +// "I2C1_SCL_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_I2C_SCL_GPIO_PORT 7 +// "I2C1_SCL_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAMERA_I2C_SCL_GPIO_PIN 3 +// "I2C1_SCL_C" GPIO pin alternate function <0-7> +#define BOARD_CAMERA_I2C_SCL_ALTERNATE_FUNCTION 5 + +// "CAM_HSYNC_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_HSYNC_GPIO_PORT 0 +// "CAM_HSYNC_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_HSYNC_GPIO_PIN 0 +// "CAM_HSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_HSYNC_ALTERNATE_FUNCTION 6 + +// "CAM_VSYNC_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_VSYNC_GPIO_PORT 0 +// "CAM_VSYNC_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_VSYNC_GPIO_PIN 1 +// "CAM_VSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_VSYNC_ALTERNATE_FUNCTION 6 + +// "CAM_PCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_PCLK_GPIO_PORT 0 +// "CAM_PCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_PCLK_GPIO_PIN 2 +// "CAM_PCLK_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_PCLK_ALTERNATE_FUNCTION 6 + +// "CAM_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D0_GPIO_PORT 8 +// "CAM_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D0_GPIO_PIN 0 +// "CAM_D0_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D0_ALTERNATE_FUNCTION 7 + +// "CAM_D1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D1_GPIO_PORT 8 +// "CAM_D1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D1_GPIO_PIN 1 +// "CAM_D1_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D1_ALTERNATE_FUNCTION 6 + +// "CAM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D2_GPIO_PORT 8 +// "CAM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D2_GPIO_PIN 2 +// "CAM_D2_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D2_ALTERNATE_FUNCTION 7 + +// "CAM_D3_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D3_GPIO_PORT 8 +// "CAM_D3_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D3_GPIO_PIN 3 +// "CAM_D3_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D3_ALTERNATE_FUNCTION 7 + +// "CAM_D4_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D4_GPIO_PORT 8 +// "CAM_D4_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D4_GPIO_PIN 4 +// "CAM_D4_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D4_ALTERNATE_FUNCTION 7 + +// "CAM_D5_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D5_GPIO_PORT 8 +// "CAM_D5_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D5_GPIO_PIN 5 +// "CAM_D5_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D5_ALTERNATE_FUNCTION 7 + +// "CAM_D6_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D6_GPIO_PORT 8 +// "CAM_D6_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D6_GPIO_PIN 6 +// "CAM_D6_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D6_ALTERNATE_FUNCTION 7 + +// "CAM_D7_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D7_GPIO_PORT 8 +// "CAM_D7_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D7_GPIO_PIN 7 +// "CAM_D7_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D7_ALTERNATE_FUNCTION 7 + +// "LPCAM_HSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_HSYNC_GPIO_PORT 0 +// "LPCAM_HSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_HSYNC_GPIO_PIN 0 +// "LPCAM_HSYNC_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_HSYNC_ALTERNATE_FUNCTION 5 + +// "LPCAM_VSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_VSYNC_GPIO_PORT 0 +// "LPCAM_VSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_VSYNC_GPIO_PIN 1 +// "LPCAM_VSYNC_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_VSYNC_ALTERNATE_FUNCTION 5 + +// "LPCAM_PCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_PCLK_GPIO_PORT 0 +// "LPCAM_PCLK_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_PCLK_GPIO_PIN 2 +// "LPCAM_PCLK_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_PCLK_ALTERNATE_FUNCTION 5 + +// "LPCAM_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D0_GPIO_PORT 8 +// "LPCAM_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D0_GPIO_PIN 0 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D0_ALTERNATE_FUNCTION 4 + +// "LPCAM_D1_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D1_GPIO_PORT 8 +// "LPCAM_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D1_GPIO_PIN 1 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D1_ALTERNATE_FUNCTION 3 + +// "LPCAM_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D2_GPIO_PORT 8 +// "LPCAM_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D2_GPIO_PIN 2 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D2_ALTERNATE_FUNCTION 4 + +// "LPCAM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D3_GPIO_PORT 8 +// "LPCAM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D3_GPIO_PIN 3 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D3_ALTERNATE_FUNCTION 4 + +// "LPCAM_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D4_GPIO_PORT 8 +// "LPCAM_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D4_GPIO_PIN 4 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D4_ALTERNATE_FUNCTION 4 + +// "LPCAM_D5_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D5_GPIO_PORT 8 +// "LPCAM_D5_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D5_GPIO_PIN 5 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D5_ALTERNATE_FUNCTION 4 + +// "LPCAM_D6_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D6_GPIO_PORT 8 +// "LPCAM_D6_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D6_GPIO_PIN 6 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D6_ALTERNATE_FUNCTION 4 + +// "LPCAM_D7_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D7_GPIO_PORT 8 +// "LPCAM_D7_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D7_GPIO_PIN 7 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D7_ALTERNATE_FUNCTION 4 + +// "CDC_PCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_PCLK_GPIO_PORT 5 +// "CDC_PCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_PCLK_GPIO_PIN 3 +// "CDC_PCLK_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_PCLK_ALTERNATE_FUNCTION 7 + +// "CDC_DE_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_DE_GPIO_PORT 5 +// "CDC_DE_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_DE_GPIO_PIN 4 +// "CDC_DE_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_DE_ALTERNATE_FUNCTION 7 + +// "CDC_HSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_HSYNC_GPIO_PORT 4 +// "CDC_HSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CDC_HSYNC_GPIO_PIN 1 +// "CDC_HSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_HSYNC_ALTERNATE_FUNCTION 6 + +// "CDC_VSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_VSYNC_GPIO_PORT 4 +// "CDC_VSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CDC_VSYNC_GPIO_PIN 0 +// "CDC_VSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_VSYNC_ALTERNATE_FUNCTION 6 + +// "CDC_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D0_GPIO_PORT 11 +// "CDC_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D0_GPIO_PIN 0 +// "CDC_D0_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D0_ALTERNATE_FUNCTION 7 + +// "CDC_D1_A"GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D1_GPIO_PORT 8 +// "CDC_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D1_GPIO_PIN 1 +// "CDC_D1_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D1_ALTERNATE_FUNCTION 5 + +// "CDC_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D2_GPIO_PORT 8 +// "CDC_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D2_GPIO_PIN 2 +// "CDC_D2_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D2_ALTERNATE_FUNCTION 6 + +// "CDC_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D3_GPIO_PORT 8 +// "CDC_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D3_GPIO_PIN 3 +// "CDC_D3_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D3_ALTERNATE_FUNCTION 6 + +// "CDC_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D4_GPIO_PORT 8 +// "CDC_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D4_GPIO_PIN 4 +// "CDC_D4_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D4_ALTERNATE_FUNCTION 6 + +// "CDC_D5_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D5_GPIO_PORT 11 +// "CDC_D5_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D5_GPIO_PIN 5 +// "CDC_D5_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D5_ALTERNATE_FUNCTION 7 + +// "CDC_D6_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D6_GPIO_PORT 11 +// "CDC_D6_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D6_GPIO_PIN 6 +// "CDC_D6_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D6_ALTERNATE_FUNCTION 7 + +// "CDC_D7_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D7_GPIO_PORT 11 +// "CDC_D7_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D7_GPIO_PIN 7 +// "CDC_D7_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D7_ALTERNATE_FUNCTION 7 + +// "CDC_D8_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D8_GPIO_PORT 9 +// "CDC_D8_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D8_GPIO_PIN 0 +// "CDC_D8_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D8_ALTERNATE_FUNCTION 5 + +// "CDC_D9_A"GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D9_GPIO_PORT 9 +// "CDC_D9_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D9_GPIO_PIN 1 +// "CDC_D9_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D9_ALTERNATE_FUNCTION 6 + +// "CDC_D10_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D10_GPIO_PORT 9 +// "CDC_D10_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D10_GPIO_PIN 2 +// "CDC_D10_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D10_ALTERNATE_FUNCTION 6 + +// "CDC_D11_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D11_GPIO_PORT 9 +// "CDC_D11_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D11_GPIO_PIN 3 +// "CDC_D11_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D11_ALTERNATE_FUNCTION 6 + +// "CDC_D12_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D12_GPIO_PORT 9 +// "CDC_D12_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D12_GPIO_PIN 4 +// "CDC_D12_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D12_ALTERNATE_FUNCTION 6 + +// "CDC_D13_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D13_GPIO_PORT 12 +// "CDC_D13_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D13_GPIO_PIN 5 +// "CDC_D13_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D13_ALTERNATE_FUNCTION 5 + +// "CDC_D14_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D14_GPIO_PORT 12 +// "CDC_D14_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D14_GPIO_PIN 6 +// "CDC_D14_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D14_ALTERNATE_FUNCTION 5 + +// "CDC_D15_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D15_GPIO_PORT 12 +// "CDC_D15_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D15_GPIO_PIN 7 +// "CDC_D15_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D15_ALTERNATE_FUNCTION 5 + +// "CDC_D16_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D16_GPIO_PORT 13 +// "CDC_D16_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D16_GPIO_PIN 0 +// "CDC_D16_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D16_ALTERNATE_FUNCTION 6 + +// "CDC_D17_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D17_GPIO_PORT 13 +// "CDC_D17_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D17_GPIO_PIN 1 +// "CDC_D17_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D17_ALTERNATE_FUNCTION 5 + +// "CDC_D18_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D18_GPIO_PORT 13 +// "CDC_D18_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D18_GPIO_PIN 2 +// "CDC_D18_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D18_ALTERNATE_FUNCTION 5 + +// "CDC_D19_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D19_GPIO_PORT 13 +// "CDC_D19_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D19_GPIO_PIN 3 +// "CDC_D19_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D19_ALTERNATE_FUNCTION 5 + +// "CDC_D20_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D20_GPIO_PORT 13 +// "CDC_D20_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D20_GPIO_PIN 4 +// "CDC_D20_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D20_ALTERNATE_FUNCTION 5 + +// "CDC_D21_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D21_GPIO_PORT 13 +// "CDC_D21_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D21_GPIO_PIN 5 +// "CDC_D21_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D21_ALTERNATE_FUNCTION 5 + +// "CDC_D22_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D22_GPIO_PORT 13 +// "CDC_D22_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D22_GPIO_PIN 6 +// "CDC_D22_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D22_ALTERNATE_FUNCTION 5 + +// "CDC_D23_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D23_GPIO_PORT 13 +// "CDC_D23_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D23_GPIO_PIN 7 +// "CDC_D23_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D23_ALTERNATE_FUNCTION 5 + +// "CLICKBOARD_INT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CLICKBOARD_INT_GPIO_PORT 8 +// "CLICKBOARD_INT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CLICKBOARD_INT_GPIO_PIN 1 + +// "CLICKBOARD_RST" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CLICKBOARD_RST_GPIO_PORT 8 +// "CLICKBOARD_RST" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CLICKBOARD_RST_GPIO_PIN 3 + +// "ICM42670_IMU_IRQ" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ICM42670_IMU_IRQ_GPIO_PORT 1 +// "ICM42670_IMU_IRQ" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_ICM42670_IMU_IRQ_GPIO_PIN 5 + +// "BMI323_IMU_IRQ" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_BMI323_IMU_IRQ_GPIO_PORT 1 +// "BMI323_IMU_IRQ" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_BMI323_IMU_IRQ_GPIO_PIN 4 + +// "CAMERA_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_RESET_GPIO_PORT 9 +// "CAMERA_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_RESET_GPIO_PIN 1 + +// "CAMERA_FLASH" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_FLASH_GPIO_PORT 9 +// "CAMERA_FLASH" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_FLASH_GPIO_PIN 2 + +// "CAMERA_TRIGGER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_TRIGGER_GPIO_PORT 9 +// "CAMERA_TRIGGER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_TRIGGER_GPIO_PIN 3 + +// "TOUCH_INT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_TOUCH_INT_GPIO_PORT 9 +// "TOUCH_INT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_TOUCH_INT_GPIO_PIN 4 + +// "LEDRGB0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_B_GPIO_PORT 12 +// "LEDRGB0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_B_GPIO_PIN 0 +// "LEDRGB0_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_B_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_B_UT_ALTERNATE_FUNCTION 4 + +// "LEDRGB0_R" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_R_GPIO_PORT 12 +// "LEDRGB0_R" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_R_GPIO_PIN 3 +// "LEDRGB0_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_R_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_R_UT_ALTERNATE_FUNCTION 4 + +// "LEDRGB0_G" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_G_GPIO_PORT 7 +// "LEDRGB0_G" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_G_GPIO_PIN 4 +// "LEDRGB0_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_G_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_G_UT_ALTERNATE_FUNCTION 6 + +// "JOY_SW_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_A_GPIO_PORT 15 +// "JOY_SW_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_A_GPIO_PIN 0 + +// "JOY_SW_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_B_GPIO_PORT 15 +// "JOY_SW_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_B_GPIO_PIN 1 + +// "JOY_SW_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_C_GPIO_PORT 15 +// "JOY_SW_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_C_GPIO_PIN 2 + +// "JOY_SW_D" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_D_GPIO_PORT 15 +// "JOY_SW_D" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_D_GPIO_PIN 3 + +// "JOY_SW_CENTER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_CENTER_GPIO_PORT 15 +// "JOY_SW_CENTER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_JOY_SW_CENTER_GPIO_PIN 4 + +// "LCD_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LCD_RESET_GPIO_PORT 13 +// "LCD_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LCD_RESET_GPIO_PIN 6 + +// "PSRAM" OSPI instance number <0> (Do Not Modify!) +#define BOARD_PSRAM_OSPI_INSTANCE 0 + +// OSPI Flash instance number (Do Not Modify!) +#define BOARD_OSPI_FLASH_INSTANCE 2 + +// "OSPI_FLASH_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_OSPI_FLASH_RESET_GPIO_PORT 15 +// "OSPI_FLASH_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_OSPI_FLASH_RESET_GPIO_PIN 7 + +// "WM8904_CODEC" on I2S presence flag +#define BOARD_WM8904_CODEC_PRESENT 1 + +// "WM8904_CODEC_I2C_SDA" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <15=> LPGPIO +#define BOARD_WM8904_CODEC_I2C_SDA_GPIO_PORT 7 +// "WM8904_CODEC_I2C_SDA" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_WM8904_CODEC_I2C_SDA_GPIO_PIN 2 + +// "WM8904_CODEC_I2C_SDA" GPIO pin alternate function +#define BOARD_WM8904_CODEC_I2C_SDA_ALTERNATE_FUNCTION 5 + +// "WM8904_CODEC_I2C_SCL" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <15=> LPGPIO +#define BOARD_WM8904_CODEC_I2C_SCL_GPIO_PORT 7 + +// "WM8904_CODEC_I2C_SCL" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_WM8904_CODEC_I2C_SCL_GPIO_PIN 3 + +// "WM8904_CODEC_I2C_SCL" GPIO pin alternate function +#define BOARD_WM8904_CODEC_I2C_SCL_ALTERNATE_FUNCTION 5 + +// "DAC Output" I2S instance number <0=> I2S0 <1=> I2S1 <2=> I2S2 <3=> I2S3 LPI2S +#define BOARD_DAC_OUTPUT_I2S_INSTANCE 2 + +// "DAC_OUTPUT_SDO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SDO_GPIO_PORT 8 +// "DAC_OUTPUT_SDO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SDO_GPIO_PIN 2 +// "DAC_OUTPUT_SDO" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SDO_ALTERNATE_FUNCTION 1 + +// "DAC_OUTPUT_WS" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_WS_GPIO_PORT 8 +// "DAC_OUTPUT_WS" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_WS_GPIO_PIN 4 +// "DAC_OUTPUT_WS" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_WS_ALTERNATE_FUNCTION 1 + +// "DAC_OUTPUT_SCLK" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PORT 8 +// "DAC_OUTPUT_SCLK" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PIN 3 +// "DAC_OUTPUT_SCLK" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SCLK_ALTERNATE_FUNCTION 1 + +// "ISSI HYPERRAM" connected to HSPI presence flag +#define BOARD_ISSI_HYPERRAM_PRESENT 0 + +// "APS512XXN PSRAM" connected to HSPI presence flag +#define BOARD_APS512XXN_PSRAM_PRESENT 1 +// diff --git a/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/board_defs.h.base@2.2.0 b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/board_defs.h.base@2.2.0 new file mode 100644 index 00000000..6250c440 --- /dev/null +++ b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/board_defs.h.base@2.2.0 @@ -0,0 +1,1361 @@ +/* + * Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ + */ +/****************************************************************************** + * @file board_defs.h + * @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ + * @version v1.0.0 + * @date 2025-10-29 + * @brief Board info/settings for "AppKit-e8" project + * with AE822FA0E5597 + * @bug None. + * @note To modify this file manually, take care to modify pins.h and gpios.h + * accordingly when required. + ******************************************************************************/ +//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + +/* + * ----------------------------------------------------------------------------- + * Board Feature Support Notes for Appkit-E8 + * ----------------------------------------------------------------------------- + * - ADC, HSCMP, LPCMP, DAC12, I2C/LPI2C, LPUART, QEC and SPI/LPSPI are + * **not supported** on the Appkit-E8 board due to unavailable pinouts. + * + * - LED: + * • Only LED0 is available. + * + * - PDM: + * • Only channels 4 and 5 are supported. + * Other PDM channels are not available on this board. + * + * - LPPDM: + * • Only channels 0 and 1 are supported. + * + * - I2S: + * • I2S microphones are not available on the Appkit-E8 board. + * To test I2S functionality, use predefined audio samples as input + * and route the output through the codec. + * + * - UTIMER: + * • Only Basic and Buffer modes are supported. Trigger, Capture and Compare + * modes are not supported due to unavailable pinouts. + * + * ----------------------------------------------------------------------------- + */ + +// Board peripheral instances +// CANFD module enabled flag +#define BOARD_CANFD_ENABLED 1 +// "CAN Transceiver" on CANFD presence flag +#define BOARD_CANFD_CAN_TRANSCEIVER_PRESENT 1 +// +// + +// CSI module enabled flag +#define BOARD_CSI_ENABLED 1 +// "ARX3A0" on CSI presence flag +#define BOARD_CSI_ARX3A0_PRESENT 1 +// +// "AR0144" on CSI presence flag +#define BOARD_CSI_AR0144_PRESENT 1 +// +// + +// DSI module enabled flag +#define BOARD_DSI_ENABLED 1 +// "ILI9806" on DSI presence flag +#define BOARD_DSI_ILI9806_PRESENT 1 +// +// + +// Select MIPI display by default +#define BOARD_CONFIGURE_LVDS_MUX 1 + +// ETH module enabled flag +#define BOARD_ETH_ENABLED 1 +// "RTL8201" on ETH presence flag +#define BOARD_ETH_RTL8201_PRESENT 1 +// +// + +// "Camera" I2C instance number <0-3> +#define BOARD_CAMERA_I2C_INSTANCE 1 + +// "GT911 Touchscreen" I2C instance number <0-3> +#define BOARD_GT911_TOUCHSCREEN_I2C_INSTANCE 1 + +// I3C module enabled flag +#define BOARD_I3C_ENABLED 1 + +// "FLEXIO" on I3C presence flag +#define BOARD_I3C_FLEXIO_PRESENT 1 +// "ICM42670 IMU" on I3C presence flag +#define BOARD_I3C_ICM42670_IMU_PRESENT 1 +// +// "BMI323 IMU" on I3C presence flag +#define BOARD_I3C_BMI323_IMU_PRESENT 1 +// +// "pin header" on I3C presence flag +#define BOARD_I3C_PIN_HEADER_PRESENT 1 +// +// + +// JTAG module enabled flag +#define BOARD_JTAG_ENABLED 1 +// + +// LPCPI module enabled flag +#define BOARD_LPCPI_ENABLED 1 +// + +// LPGPIO module enabled flag +#define BOARD_LPGPIO_ENABLED 1 +// + +// LPPDM module enabled flag +#define BOARD_LPPDM_ENABLED 1 +// + +// MISC module enabled flag +#define BOARD_MISC_ENABLED 1 +// + +// PDM module enabled flag +#define BOARD_PDM_ENABLED 1 +// "PDM MIC" on PDM presence flag +#define BOARD_PDM_PDM_MIC_PRESENT 1 +// +// + +// "Encoder" UTIMER instance number <12-15> +#define BOARD_ENCODER_UTIMER_INSTANCE 12 + +// SDMMC module enabled flag +#define BOARD_SDMMC_ENABLED 1 +// "SDCARD" on SDMMC presence flag +#define BOARD_SDMMC_SDCARD_PRESENT 1 +// +// + +// SEUART module enabled flag +#define BOARD_SEUART_ENABLED 1 +// + +// "Clickboard" UART instance number <0-7> +#define BOARD_CLICKBOARD_UART_INSTANCE 0 + +// "UARTA" UART instance number <0-7> +#define BOARD_UARTA_UART_INSTANCE 2 + +// "UARTB" UART instance number <0-7> +#define BOARD_UARTB_UART_INSTANCE 4 + +// USB module enabled flag +#define BOARD_USB_ENABLED 1 +// "Device Role" on USB presence flag +#define BOARD_USB_DEVICE_ROLE_PRESENT 1 +// +// + +// "Basic Mode" UTIMER instance number <0-12> +#define BOARD_BASIC_MODE_UTIMER_INSTANCE 0 + +// "Buffer Mode" UTIMER instance number <0-12> +#define BOARD_BUFFER_MODE_UTIMER_INSTANCE 1 + +// "Clickboard PWM" UTIMER instance number <0-12> +#define BOARD_CLICKBOARD_PWM_UTIMER_INSTANCE 3 + +// Utimer 250ms counter value +#define BOARD_UTIMER_250_MILLI_SEC_COUNTER_VALUE 100000000 + +// Utimer 500ms counter value +#define BOARD_UTIMER_500_MILLI_SEC_COUNTER_VALUE 200000000 + +// Utimer 750ms counter value +#define BOARD_UTIMER_750_MILLI_SEC_COUNTER_VALUE 300000000 + +// Utimer 1000ms counter value +#define BOARD_UTIMER_1000_MILLI_SEC_COUNTER_VALUE 400000000 + +// Utimer 1500ms counter value +#define BOARD_UTIMER_1500_MILLI_SEC_COUNTER_VALUE 600000000 + +// LED PWM utimer max counter value +#define BOARD_LED_PWM_UT_MAX_COUNTER_VALUE 240000 + +// "RED_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_RED_LED_UTIMER_COUNTER_TYPE 1 + +// "GREEN_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_GREEN_LED_UTIMER_COUNTER_TYPE 0 + +// "BLUE_LED_UTIMER_COUNTER_TYPE" UTIMER counter type +// <0=> UTIMER_COMPARE_A +// <1=> UTIMER_COMPARE_B +#define BOARD_BLUE_LED_UTIMER_COUNTER_TYPE 0 + +// UTIMER channel red LED instance number <9> +#define BOARD_RED_LED_UTIMER_INSTANCE 9 + +// UTIMER channel green LED instance number <10> +#define BOARD_GREEN_LED_UTIMER_INSTANCE 10 + +// UTIMER channel blue LED instance number <8> +#define BOARD_BLUE_LED_UTIMER_INSTANCE 8 + +// +// Miscellaneous +// Onboard LEDs +// Sets the #define BOARD_LED_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_LED_COUNT 0 + +// Onboard RGB LEDs +// Sets the #define BOARD_LEDRGB_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_LEDRGB_COUNT 1 + +// Onboard Push-buttons +// Sets the #define BOARD_BUTTON_COUNT in the board_def.h file exported from the Conductor tool. +#define BOARD_BUTTON_COUNT 5 + +// Onboard Config Switches or Jumpers +// Sets the #define BOARD_CONFIG_JUMPER_COUNT in the board_def.h file exported from the +// Conductor tool. +#define BOARD_CONFIG_JUMPER_COUNT 0 + +// Onboard Switching Devices +// Sets the #define BOARD_SWITCH_OUTPUT_COUNT in the board_def.h file exported from the +// Conductor tool. These include relays, solid state relays, transistors, optocopulers, etc. +#define BOARD_SWITCH_OUTPUT_COUNT 0 + +// OSPI0 Bus Speed +// Selects OSPI0 bus speed for a 200-MHz (default) HCLK. For 100 MHz and lower HCLK clock +// speeds, some values are either not possible, either rounded to the closest possible value in +// hardware. +#define BOARD_OSPI0_BUS_SPEED 100000000 + +// OSPI1 Bus Speed +// Selects OSPI1 bus speed for a 200-MHz (default) HCLK. For 100 MHz and lower HCLK clock +// speeds, some values are either not possible, either rounded to the closest possible value in +// hardware. +#define BOARD_OSPI1_BUS_SPEED 100000000 + +// OSPI0 onboard memory size +#define BOARD_OSPI0_MEM_SIZE 33554432 + +// OSPI1 onboard memory size +#define BOARD_OSPI1_MEM_SIZE 33554432 + +// Number of CH201 sensors +#define BOARD_CH201_MAX_NUM_SENSORS 1 + +// Number of CH201 buses +#define BOARD_CH201_NUM_BUSES 1 + +// Number of CH201 interrupt pins +#define BOARD_CH201_SENSOR_INT_PIN 1 + +// Number of CH201 trigger pins +#define BOARD_CH201_SENSOR_TRIG_PIN 1 + +// CH201 TOF PROG pin GPIO port number +#define BOARD_CH201_SENSOR_PROG_IO_PORT 6 + +// CH201 TOF PROG pin number +#define BOARD_CH201_SENSOR_PROG_PIN_NO 2 + +// CH201 TOF INT pin GPIO port numbet +#define BOARD_CH201_SENSOR_INT_IO_PORT 6 + +// CH201 TOF INT pin number +#define BOARD_CH201_SENSOR_INT_PIN_NO 3 + +// CH201 TOF RESET pin GPIO port number +#define BOARD_CH201_SENSOR_RESET_IO_PORT 6 + +// CH201 TOF RESET pin number range +#define BOARD_CH201_SENSOR_RESET_PIN_NO 4 + +// +// GPIO port/pin numbers, analog instance/input numbers, etc. +// FLEX IO pins supply voltage <0=> 3.3 V <1=> 1.8 V +// Make sure this setting corresponds to the VDD_IO_FLEX pin voltage. If the VDD_IO_FLEX pin is +// connected to a 3.3 V supply, do not change the value of the GPIO_CNTL register to command 1.8-V +// operation mode! +#define FLEX_IO_VOLTAGE_1V8 1 + +// "SD_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_RESET_GPIO_PORT 14 +// "SD_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_RESET_GPIO_PIN 7 + +// "SD_CARD_DETECT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CARD_DETECT_GPIO_PORT 3 +// "SD_CARD_DETECT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_SD_CARD_DETECT_GPIO_PIN 3 + +// "SD_CMD_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CMD_A_GPIO_PORT 7 +// "SD_CMD_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_CMD_A_GPIO_PIN 0 +// "SD_CMD_A" GPIO pin alternate function <0-7> +#define BOARD_SD_CMD_ALTERNATE_FUNCTION 6 + +// "SD_CLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_CLK_A_GPIO_PORT 7 +// "SD_CLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_CLK_A_GPIO_PIN 1 +// "SD_CLK_A" GPIO pin alternate function <0-7> +#define BOARD_SD_CLK_ALTERNATE_FUNCTION 6 + +// "SD_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D0_A_GPIO_PORT 5 +// "SD_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D0_A_GPIO_PIN 0 +// "SD_D0_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D0_ALTERNATE_FUNCTION 7 + +// "SD_D1_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D1_A_GPIO_PORT 5 +// "SD_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D1_A_GPIO_PIN 1 +// "SD_D1_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D1_ALTERNATE_FUNCTION 7 + +// "SD_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D2_A_GPIO_PORT 5 +// "SD_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D2_A_GPIO_PIN 2 +// "SD_D2_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D2_ALTERNATE_FUNCTION 7 + +// "SD_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D3_A_GPIO_PORT 5 +// "SD_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D3_A_GPIO_PIN 3 +// "SD_D3_A" GPIO pin alternate function <0-7> +#define BOARD_SD_D3_ALTERNATE_FUNCTION 6 + +// "SD_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D4_A_GPIO_PORT 5 +// "SD_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D4_A_GPIO_PIN 4 + +// "SD_D5_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D5_A_GPIO_PORT 5 +// "SD_D5_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D5_A_GPIO_PIN 5 + +// "SD_D6_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D6_A_GPIO_PORT 5 +// "SD_D6_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D6_A_GPIO_PIN 6 + +// "SD_D7_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_SD_D7_A_GPIO_PORT 5 +// "SD_D7_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_SD_D7_A_GPIO_PIN 7 + +// "LPPDM_TEST" LPPDM data/clock pair number <0=> D0/C0 <1=> D1/C1 <2=> D2/C2 <3=> D3/C3 +#define BOARD_LPPDM_TEST_LPPDM_INPUT 1 + +// "LPPDM_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D0_GPIO_PORT 3 +// "LPPDM_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D0_GPIO_PIN 5 +// "LPPDM_D0_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D0_ALTERNATE_FUNCTION 3 + +// "LPPDM_D1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D1_GPIO_PORT 3 +// "LPPDM_D1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D1_GPIO_PIN 7 +// "LPPDM_D1_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D1_ALTERNATE_FUNCTION 3 + +// "LPPDM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D2_GPIO_PORT 11 +// "LPPDM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D2_GPIO_PIN 6 +// "LPPDM_D2_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D2_ALTERNATE_FUNCTION 3 + +// "LPPDM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_D3_GPIO_PORT 7 +// "LPPDM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_D3_GPIO_PIN 7 +// "LPPDM_D3_A" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_D3_ALTERNATE_FUNCTION 4 + +// "LPPDM_C0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C0_GPIO_PORT 3 +// "LPPDM_C0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C0_GPIO_PIN 4 +// "LPPDM_C0_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C0_ALTERNATE_FUNCTION 3 + +// "LPPDM_C1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C1_GPIO_PORT 3 +// "LPPDM_C1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C1_GPIO_PIN 6 +// "LPPDM_C1_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C1_ALTERNATE_FUNCTION 3 + +// "LPPDM_C2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C2_GPIO_PORT 11 +// "LPPDM_C2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C2_GPIO_PIN 2 +// "LPPDM_C2_B" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C2_ALTERNATE_FUNCTION 3 + +// "LPPDM_C3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPPDM_C3_GPIO_PORT 7 +// "LPPDM_C3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPPDM_C3_GPIO_PIN 6 +// "LPPDM_C3_A" GPIO pin alternate function <0-7> +#define BOARD_LPPDM_C3_ALTERNATE_FUNCTION 4 + +// "PDM_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D0_A_GPIO_PORT 3 +// "PDM_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D0_A_GPIO_PIN 4 + +// "PDM_D1_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D1_C_GPIO_PORT 6 +// "PDM_D1_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D1_C_GPIO_PIN 2 + +// "PDM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D2_B_GPIO_PORT 5 +// "PDM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D2_B_GPIO_PIN 4 + +// "PDM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_D3_A_GPIO_PORT 5 +// "PDM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_D3_A_GPIO_PIN 1 + +// "PDM_C0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C0_A_GPIO_PORT 3 +// "PDM_C0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C0_A_GPIO_PIN 5 + +// "PDM_C1_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C1_C_GPIO_PORT 6 +// "PDM_C1_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C1_C_GPIO_PIN 3 + +// "PDM_C2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C2_A_GPIO_PORT 6 +// "PDM_C2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C2_A_GPIO_PIN 7 + +// "PDM_C3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_PDM_C3_A_GPIO_PORT 5 +// "PDM_C3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_PDM_C3_A_GPIO_PIN 2 + +// "TOUCH_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_TOUCH_RESET_GPIO_PORT 6 +// "TOUCH_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_TOUCH_RESET_GPIO_PIN 5 + +// "PDM_MIC" PDM data/clock pair number <0=> D0/C0 <1=> D1/C1 <2=> D2/C2 <3=> D3/C3 +#define BOARD_PDM_MIC_PDM_INPUT 2 + +// "LCD_BACKLIGHT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LCD_BACKLIGHT_GPIO_PORT 6 +// "LCD_BACKLIGHT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LCD_BACKLIGHT_GPIO_PIN 1 + +// "CAN_RXD" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_RXD_GPIO_PORT 12 +// "CAN_RXD_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_RXD_GPIO_PIN 4 +// "CAN_RXD" GPIO pin alternate function <0-7> +#define BOARD_CAN_RXD_ALTERNATE_FUNCTION 4 + +// "CAN_TXD" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_TXD_GPIO_PORT 12 +// "CAN_TXD" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_TXD_GPIO_PIN 5 +// "CAN_TXD" GPIO pin alternate function <0-7> +#define BOARD_CAN_TXD_ALTERNATE_FUNCTION 4 + +// "CAN_STBY" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAN_STBY_GPIO_PORT 12 +// "CAN_STBY" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAN_STBY_GPIO_PIN 6 +// "CAN_STBY" GPIO pin alternate function <0-7> +#define BOARD_CAN_STBY_ALTERNATE_FUNCTION 4 + +// "CAM_XVCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_XVCLK_A_GPIO_PORT 0 +// "CAM_XVCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_XVCLK_A_GPIO_PIN 3 + +// "CAMERA_POWER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_POWER_GPIO_PORT 7 +// "CAMERA_POWER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_POWER_GPIO_PIN 5 + +// "I2C1_SDA_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_I2C_SDA_GPIO_PORT 7 +// "I2C1_SDA_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAMERA_I2C_SDA_GPIO_PIN 2 +// "I2C1_SDA_C" GPIO pin alternate function <0-7> +#define BOARD_CAMERA_I2C_SDA_ALTERNATE_FUNCTION 5 + +// "I2C1_SCL_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_I2C_SCL_GPIO_PORT 7 +// "I2C1_SCL_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAMERA_I2C_SCL_GPIO_PIN 3 +// "I2C1_SCL_C" GPIO pin alternate function <0-7> +#define BOARD_CAMERA_I2C_SCL_ALTERNATE_FUNCTION 5 + +// "CAM_HSYNC_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_HSYNC_GPIO_PORT 0 +// "CAM_HSYNC_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_HSYNC_GPIO_PIN 0 +// "CAM_HSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_HSYNC_ALTERNATE_FUNCTION 6 + +// "CAM_VSYNC_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_VSYNC_GPIO_PORT 0 +// "CAM_VSYNC_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAM_VSYNC_GPIO_PIN 1 +// "CAM_VSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_VSYNC_ALTERNATE_FUNCTION 6 + +// "CAM_PCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_PCLK_GPIO_PORT 0 +// "CAM_PCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_PCLK_GPIO_PIN 2 +// "CAM_PCLK_A" GPIO pin alternate function <0-7> +#define BOARD_CAM_PCLK_ALTERNATE_FUNCTION 6 + +// "CAM_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D0_GPIO_PORT 8 +// "CAM_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D0_GPIO_PIN 0 +// "CAM_D0_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D0_ALTERNATE_FUNCTION 7 + +// "CAM_D1_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D1_GPIO_PORT 8 +// "CAM_D1_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D1_GPIO_PIN 1 +// "CAM_D1_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D1_ALTERNATE_FUNCTION 6 + +// "CAM_D2_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D2_GPIO_PORT 8 +// "CAM_D2_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D2_GPIO_PIN 2 +// "CAM_D2_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D2_ALTERNATE_FUNCTION 7 + +// "CAM_D3_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D3_GPIO_PORT 8 +// "CAM_D3_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D3_GPIO_PIN 3 +// "CAM_D3_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D3_ALTERNATE_FUNCTION 7 + +// "CAM_D4_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D4_GPIO_PORT 8 +// "CAM_D4_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D4_GPIO_PIN 4 +// "CAM_D4_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D4_ALTERNATE_FUNCTION 7 + +// "CAM_D5_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D5_GPIO_PORT 8 +// "CAM_D5_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D5_GPIO_PIN 5 +// "CAM_D5_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D5_ALTERNATE_FUNCTION 7 + +// "CAM_D6_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D6_GPIO_PORT 8 +// "CAM_D6_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D6_GPIO_PIN 6 +// "CAM_D6_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D6_ALTERNATE_FUNCTION 7 + +// "CAM_D7_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAM_D7_GPIO_PORT 8 +// "CAM_D7_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CAM_D7_GPIO_PIN 7 +// "CAM_D7_B" GPIO pin alternate function <0-7> +#define BOARD_CAM_D7_ALTERNATE_FUNCTION 7 + +// "LPCAM_HSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_HSYNC_GPIO_PORT 0 +// "LPCAM_HSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_HSYNC_GPIO_PIN 0 +// "LPCAM_HSYNC_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_HSYNC_ALTERNATE_FUNCTION 5 + +// "LPCAM_VSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_VSYNC_GPIO_PORT 0 +// "LPCAM_VSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_VSYNC_GPIO_PIN 1 +// "LPCAM_VSYNC_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_VSYNC_ALTERNATE_FUNCTION 5 + +// "LPCAM_PCLK_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_PCLK_GPIO_PORT 0 +// "LPCAM_PCLK_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_LPCAM_PCLK_GPIO_PIN 2 +// "LPCAM_PCLK_B" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_PCLK_ALTERNATE_FUNCTION 5 + +// "LPCAM_D0_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D0_GPIO_PORT 8 +// "LPCAM_D0_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D0_GPIO_PIN 0 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D0_ALTERNATE_FUNCTION 4 + +// "LPCAM_D1_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D1_GPIO_PORT 8 +// "LPCAM_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D1_GPIO_PIN 1 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D1_ALTERNATE_FUNCTION 3 + +// "LPCAM_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D2_GPIO_PORT 8 +// "LPCAM_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D2_GPIO_PIN 2 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D2_ALTERNATE_FUNCTION 4 + +// "LPCAM_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D3_GPIO_PORT 8 +// "LPCAM_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D3_GPIO_PIN 3 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D3_ALTERNATE_FUNCTION 4 + +// "LPCAM_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D4_GPIO_PORT 8 +// "LPCAM_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D4_GPIO_PIN 4 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D4_ALTERNATE_FUNCTION 4 + +// "LPCAM_D5_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D5_GPIO_PORT 8 +// "LPCAM_D5_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D5_GPIO_PIN 5 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D5_ALTERNATE_FUNCTION 4 + +// "LPCAM_D6_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D6_GPIO_PORT 8 +// "LPCAM_D6_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D6_GPIO_PIN 6 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D6_ALTERNATE_FUNCTION 4 + +// "LPCAM_D7_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LPCAM_D7_GPIO_PORT 8 +// "LPCAM_D7_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LPCAM_D7_GPIO_PIN 7 +// "LPCAM_D0_A" GPIO pin alternate function <0-7> +#define BOARD_LPCAM_D7_ALTERNATE_FUNCTION 4 + +// "CDC_PCLK_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_PCLK_GPIO_PORT 5 +// "CDC_PCLK_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_PCLK_GPIO_PIN 3 +// "CDC_PCLK_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_PCLK_ALTERNATE_FUNCTION 7 + +// "CDC_DE_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_DE_GPIO_PORT 5 +// "CDC_DE_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_DE_GPIO_PIN 4 +// "CDC_DE_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_DE_ALTERNATE_FUNCTION 7 + +// "CDC_HSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_HSYNC_GPIO_PORT 4 +// "CDC_HSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CDC_HSYNC_GPIO_PIN 1 +// "CDC_HSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_HSYNC_ALTERNATE_FUNCTION 6 + +// "CDC_VSYNC_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_VSYNC_GPIO_PORT 4 +// "CDC_VSYNC_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CDC_VSYNC_GPIO_PIN 0 +// "CDC_VSYNC_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_VSYNC_ALTERNATE_FUNCTION 6 + +// "CDC_D0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D0_GPIO_PORT 11 +// "CDC_D0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D0_GPIO_PIN 0 +// "CDC_D0_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D0_ALTERNATE_FUNCTION 7 + +// "CDC_D1_A"GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D1_GPIO_PORT 8 +// "CDC_D1_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D1_GPIO_PIN 1 +// "CDC_D1_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D1_ALTERNATE_FUNCTION 5 + +// "CDC_D2_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D2_GPIO_PORT 8 +// "CDC_D2_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D2_GPIO_PIN 2 +// "CDC_D2_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D2_ALTERNATE_FUNCTION 6 + +// "CDC_D3_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D3_GPIO_PORT 8 +// "CDC_D3_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D3_GPIO_PIN 3 +// "CDC_D3_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D3_ALTERNATE_FUNCTION 6 + +// "CDC_D4_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D4_GPIO_PORT 8 +// "CDC_D4_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D4_GPIO_PIN 4 +// "CDC_D4_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D4_ALTERNATE_FUNCTION 6 + +// "CDC_D5_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D5_GPIO_PORT 11 +// "CDC_D5_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D5_GPIO_PIN 5 +// "CDC_D5_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D5_ALTERNATE_FUNCTION 7 + +// "CDC_D6_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D6_GPIO_PORT 11 +// "CDC_D6_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D6_GPIO_PIN 6 +// "CDC_D6_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D6_ALTERNATE_FUNCTION 7 + +// "CDC_D7_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D7_GPIO_PORT 11 +// "CDC_D7_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D7_GPIO_PIN 7 +// "CDC_D7_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D7_ALTERNATE_FUNCTION 7 + +// "CDC_D8_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D8_GPIO_PORT 9 +// "CDC_D8_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D8_GPIO_PIN 0 +// "CDC_D8_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D8_ALTERNATE_FUNCTION 5 + +// "CDC_D9_A"GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D9_GPIO_PORT 9 +// "CDC_D9_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D9_GPIO_PIN 1 +// "CDC_D9_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D9_ALTERNATE_FUNCTION 6 + +// "CDC_D10_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D10_GPIO_PORT 9 +// "CDC_D10_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D10_GPIO_PIN 2 +// "CDC_D10_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D10_ALTERNATE_FUNCTION 6 + +// "CDC_D11_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D11_GPIO_PORT 9 +// "CDC_D11_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D11_GPIO_PIN 3 +// "CDC_D11_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D11_ALTERNATE_FUNCTION 6 + +// "CDC_D12_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D12_GPIO_PORT 9 +// "CDC_D12_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D12_GPIO_PIN 4 +// "CDC_D12_A" GPIO pin alternate function <0-7> +#define BOARD_CDC_D12_ALTERNATE_FUNCTION 6 + +// "CDC_D13_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D13_GPIO_PORT 12 +// "CDC_D13_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D13_GPIO_PIN 5 +// "CDC_D13_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D13_ALTERNATE_FUNCTION 5 + +// "CDC_D14_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D14_GPIO_PORT 12 +// "CDC_D14_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D14_GPIO_PIN 6 +// "CDC_D14_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D14_ALTERNATE_FUNCTION 5 + +// "CDC_D15_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D15_GPIO_PORT 12 +// "CDC_D15_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D15_GPIO_PIN 7 +// "CDC_D15_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D15_ALTERNATE_FUNCTION 5 + +// "CDC_D16_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D16_GPIO_PORT 13 +// "CDC_D16_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D16_GPIO_PIN 0 +// "CDC_D16_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D16_ALTERNATE_FUNCTION 6 + +// "CDC_D17_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D17_GPIO_PORT 13 +// "CDC_D17_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D17_GPIO_PIN 1 +// "CDC_D17_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D17_ALTERNATE_FUNCTION 5 + +// "CDC_D18_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D18_GPIO_PORT 13 +// "CDC_D18_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D18_GPIO_PIN 2 +// "CDC_D18_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D18_ALTERNATE_FUNCTION 5 + +// "CDC_D19_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D19_GPIO_PORT 13 +// "CDC_D19_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D19_GPIO_PIN 3 +// "CDC_D19_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D19_ALTERNATE_FUNCTION 5 + +// "CDC_D20_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D20_GPIO_PORT 13 +// "CDC_D20_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D20_GPIO_PIN 4 +// "CDC_D20_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D20_ALTERNATE_FUNCTION 5 + +// "CDC_D21_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D21_GPIO_PORT 13 +// "CDC_D21_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D21_GPIO_PIN 5 +// "CDC_D21_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D21_ALTERNATE_FUNCTION 5 + +// "CDC_D22_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D22_GPIO_PORT 13 +// "CDC_D22_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D22_GPIO_PIN 6 +// "CDC_D22_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D22_ALTERNATE_FUNCTION 5 + +// "CDC_D23_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CDC_D23_GPIO_PORT 13 +// "CDC_D23_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_CDC_D23_GPIO_PIN 7 +// "CDC_D23_B" GPIO pin alternate function <0-7> +#define BOARD_CDC_D23_ALTERNATE_FUNCTION 5 + +// "CLICKBOARD_INT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CLICKBOARD_INT_GPIO_PORT 8 +// "CLICKBOARD_INT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CLICKBOARD_INT_GPIO_PIN 1 + +// "CLICKBOARD_RST" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CLICKBOARD_RST_GPIO_PORT 8 +// "CLICKBOARD_RST" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CLICKBOARD_RST_GPIO_PIN 3 + +// "ICM42670_IMU_IRQ" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_ICM42670_IMU_IRQ_GPIO_PORT 1 +// "ICM42670_IMU_IRQ" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 +// <5=> PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_ICM42670_IMU_IRQ_GPIO_PIN 5 + +// "BMI323_IMU_IRQ" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_BMI323_IMU_IRQ_GPIO_PORT 1 +// "BMI323_IMU_IRQ" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_BMI323_IMU_IRQ_GPIO_PIN 4 + +// "CAMERA_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_RESET_GPIO_PORT 9 +// "CAMERA_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_RESET_GPIO_PIN 1 + +// "CAMERA_FLASH" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_FLASH_GPIO_PORT 9 +// "CAMERA_FLASH" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_FLASH_GPIO_PIN 2 + +// "CAMERA_TRIGGER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_CAMERA_TRIGGER_GPIO_PORT 9 +// "CAMERA_TRIGGER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_CAMERA_TRIGGER_GPIO_PIN 3 + +// "TOUCH_INT" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_TOUCH_INT_GPIO_PORT 9 +// "TOUCH_INT" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_TOUCH_INT_GPIO_PIN 4 + +// "LEDRGB0_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_B_GPIO_PORT 12 +// "LEDRGB0_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_B_GPIO_PIN 0 +// "LEDRGB0_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_B_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_B" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_B_UT_ALTERNATE_FUNCTION 4 + +// "LEDRGB0_R" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_R_GPIO_PORT 12 +// "LEDRGB0_R" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_R_GPIO_PIN 3 +// "LEDRGB0_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_R_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_R" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_R_UT_ALTERNATE_FUNCTION 4 + +// "LEDRGB0_G" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LEDRGB0_G_GPIO_PORT 7 +// "LEDRGB0_G" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LEDRGB0_G_GPIO_PIN 4 +// "LEDRGB0_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_G_ALTERNATE_FUNCTION 0 +// "UTIMER PWM LEDRGB0_G" GPIO pin alternate function <0-7> +#define BOARD_LEDRGB0_G_UT_ALTERNATE_FUNCTION 6 + +// "JOY_SW_A" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_A_GPIO_PORT 15 +// "JOY_SW_A" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_A_GPIO_PIN 0 + +// "JOY_SW_B" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_B_GPIO_PORT 15 +// "JOY_SW_B" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_B_GPIO_PIN 1 + +// "JOY_SW_C" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_C_GPIO_PORT 15 +// "JOY_SW_C" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_C_GPIO_PIN 2 + +// "JOY_SW_D" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> GPIO5 +// <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> GPIO13 +// <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_D_GPIO_PORT 15 +// "JOY_SW_D" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_JOY_SW_D_GPIO_PIN 3 + +// "JOY_SW_CENTER" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_JOY_SW_CENTER_GPIO_PORT 15 +// "JOY_SW_CENTER" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_JOY_SW_CENTER_GPIO_PIN 4 + +// "LCD_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_LCD_RESET_GPIO_PORT 13 +// "LCD_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 <6=> +// PIN6 <7=> PIN7 +#define BOARD_LCD_RESET_GPIO_PIN 6 + +// "PSRAM" OSPI instance number <0> (Do Not Modify!) +#define BOARD_PSRAM_OSPI_INSTANCE 0 + +// OSPI Flash instance number (Do Not Modify!) +#define BOARD_OSPI_FLASH_INSTANCE 2 + +// "OSPI_FLASH_RESET" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_OSPI_FLASH_RESET_GPIO_PORT 15 +// "OSPI_FLASH_RESET" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_OSPI_FLASH_RESET_GPIO_PIN 7 + +// "WM8904_CODEC" on I2S presence flag +#define BOARD_WM8904_CODEC_PRESENT 1 + +// "WM8904_CODEC_I2C_SDA" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <15=> LPGPIO +#define BOARD_WM8904_CODEC_I2C_SDA_GPIO_PORT 7 +// "WM8904_CODEC_I2C_SDA" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_WM8904_CODEC_I2C_SDA_GPIO_PIN 2 + +// "WM8904_CODEC_I2C_SDA" GPIO pin alternate function +#define BOARD_WM8904_CODEC_I2C_SDA_ALTERNATE_FUNCTION 5 + +// "WM8904_CODEC_I2C_SCL" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> +// GPIO4 <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <15=> LPGPIO +#define BOARD_WM8904_CODEC_I2C_SCL_GPIO_PORT 7 + +// "WM8904_CODEC_I2C_SCL" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> +// PIN5 <6=> PIN6 <7=> PIN7 +#define BOARD_WM8904_CODEC_I2C_SCL_GPIO_PIN 3 + +// "WM8904_CODEC_I2C_SCL" GPIO pin alternate function +#define BOARD_WM8904_CODEC_I2C_SCL_ALTERNATE_FUNCTION 5 + +// "DAC Output" I2S instance number <0=> I2S0 <1=> I2S1 <2=> I2S2 <3=> I2S3 LPI2S +#define BOARD_DAC_OUTPUT_I2S_INSTANCE 2 + +// "DAC_OUTPUT_SDO" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SDO_GPIO_PORT 8 +// "DAC_OUTPUT_SDO" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SDO_GPIO_PIN 2 +// "DAC_OUTPUT_SDO" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SDO_ALTERNATE_FUNCTION 1 + +// "DAC_OUTPUT_WS" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 <5=> +// GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 <13=> +// GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_WS_GPIO_PORT 8 +// "DAC_OUTPUT_WS" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_WS_GPIO_PIN 4 +// "DAC_OUTPUT_WS" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_WS_ALTERNATE_FUNCTION 1 + +// "DAC_OUTPUT_SCLK" GPIO port number <0=> GPIO0 <1=> GPIO1 <2=> GPIO2 <3=> GPIO3 <4=> GPIO4 +// <5=> GPIO5 <6=> GPIO6 <7=> GPIO7 <8=> GPIO8 <9=> GPIO9 <10=> GPIO10 <11=> GPIO11 <12=> GPIO12 +// <13=> GPIO13 <14=> GPIO14 <15=> LPGPIO +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PORT 8 +// "DAC_OUTPUT_SCLK" GPIO pin number <0=> PIN0 <1=> PIN1 <2=> PIN2 <3=> PIN3 <4=> PIN4 <5=> PIN5 +// <6=> PIN6 <7=> PIN7 +#define BOARD_DAC_OUTPUT_SCLK_GPIO_PIN 3 +// "DAC_OUTPUT_SCLK" GPIO pin alternate function <0-7> +#define BOARD_DAC_OUTPUT_SCLK_ALTERNATE_FUNCTION 1 + +// "ISSI HYPERRAM" connected to HSPI presence flag +#define BOARD_ISSI_HYPERRAM_PRESENT 0 + +// "APS512XXN PSRAM" connected to HSPI presence flag +#define BOARD_APS512XXN_PSRAM_PRESENT 1 +// diff --git a/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/gpios.h b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/gpios.h new file mode 100644 index 00000000..1307bc65 --- /dev/null +++ b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/gpios.h @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ + */ +/****************************************************************************** + * @file gpios.h + * @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ + * @version v1.0.0 + * @date 2025-10-29 + * @brief Pseudo-static GPIO pin settings for "AppKit-e8" + * project with AE822FA0E5597. + * @bug None. + * @note None. + ******************************************************************************/ + +#ifndef __GPIOS_H__ +#define __GPIOS_H__ + +#include +#include "pinconf.h" + +struct gpioconf { + uint8_t port_num; + uint8_t hardware_mode_lptimer_on_lpgpio; + uint8_t initial_state_high; + uint8_t direction_output; + uint8_t debounce_enable; + uint8_t interrupt_enable; + uint8_t interrupt_edge; + uint8_t interrupt_polarity_high_edge_rising; + uint8_t interrupt_both_edge; +}; + +/* GPIO pseudo-static settings generated by Conductor Tool */ + +const struct gpioconf board_gpioconf[] = { + + /* Pin settings (8-bit, 1 bit per pin) for GPIO3 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_3, + 0, + 0, + 0, + (1 << PIN_3), + (1 << PIN_3), + 0, + 0, + (1 << PIN_3), + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO4 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_4, + 0, + 0, + (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO6 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_6, + 0, + 0, + (1 << PIN_6) | (1 << PIN_5) | (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO7 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_7, + 0, + 0, + (1 << PIN_5) | (1 << PIN_4), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO8 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_8, + 0, + (1 << PIN_3), + (1 << PIN_3), + 0, + (1 << PIN_5) | (1 << PIN_1), + (1 << PIN_5) | (1 << PIN_1), + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO9 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_9, + 0, + (1 << PIN_1), + (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1), + 0, + (1 << PIN_4), + (1 << PIN_4), + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO12 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_12, + 0, + 0, + (1 << PIN_3) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO13 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_13, + 0, + (1 << PIN_6), + (1 << PIN_6), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO14 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_14, + 0, + (1 << PIN_2), + (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO15 + 1 - LPGPIO pins driven by LPTIMER + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_15, + 0, + (1 << PIN_7) | (1 << PIN_6) | (1 << PIN_5), + (1 << PIN_7) | (1 << PIN_6) | (1 << PIN_5), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + }}; + +#endif /* __GPIOS_H__ */ diff --git a/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/gpios.h.base@2.2.0 b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/gpios.h.base@2.2.0 new file mode 100644 index 00000000..1307bc65 --- /dev/null +++ b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/gpios.h.base@2.2.0 @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ + */ +/****************************************************************************** + * @file gpios.h + * @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ + * @version v1.0.0 + * @date 2025-10-29 + * @brief Pseudo-static GPIO pin settings for "AppKit-e8" + * project with AE822FA0E5597. + * @bug None. + * @note None. + ******************************************************************************/ + +#ifndef __GPIOS_H__ +#define __GPIOS_H__ + +#include +#include "pinconf.h" + +struct gpioconf { + uint8_t port_num; + uint8_t hardware_mode_lptimer_on_lpgpio; + uint8_t initial_state_high; + uint8_t direction_output; + uint8_t debounce_enable; + uint8_t interrupt_enable; + uint8_t interrupt_edge; + uint8_t interrupt_polarity_high_edge_rising; + uint8_t interrupt_both_edge; +}; + +/* GPIO pseudo-static settings generated by Conductor Tool */ + +const struct gpioconf board_gpioconf[] = { + + /* Pin settings (8-bit, 1 bit per pin) for GPIO3 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_3, + 0, + 0, + 0, + (1 << PIN_3), + (1 << PIN_3), + 0, + 0, + (1 << PIN_3), + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO4 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_4, + 0, + 0, + (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO6 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_6, + 0, + 0, + (1 << PIN_6) | (1 << PIN_5) | (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO7 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_7, + 0, + 0, + (1 << PIN_5) | (1 << PIN_4), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO8 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_8, + 0, + (1 << PIN_3), + (1 << PIN_3), + 0, + (1 << PIN_5) | (1 << PIN_1), + (1 << PIN_5) | (1 << PIN_1), + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO9 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_9, + 0, + (1 << PIN_1), + (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1), + 0, + (1 << PIN_4), + (1 << PIN_4), + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO12 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_12, + 0, + 0, + (1 << PIN_3) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO13 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_13, + 0, + (1 << PIN_6), + (1 << PIN_6), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO14 + 1 - Reserved for LPGPIO + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_14, + 0, + (1 << PIN_2), + (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + 0, + 0, + 0, + }, + + /* Pin settings (8-bit, 1 bit per pin) for GPIO15 + 1 - LPGPIO pins driven by LPTIMER + 2 - Output pins that will drive logic '1' after startup. Other output pins + will drive '0' + 3 - Output pins. Other pins are inputs + 4 - Pins with debounce function enabled + 5 - Pins that will generate interrupts + 6 - Interrupts that are edge sensitive. Other interrupts are level sensitive + 7 - Interrupts generated on high level or on rising edge - depending on + previous setting. Other pins are low level/falling edge sensitive + 8 - Interrupts generated on both edges. Other pins behavior is based on + previous 2 settings */ + { + PORT_15, + 0, + (1 << PIN_7) | (1 << PIN_6) | (1 << PIN_5), + (1 << PIN_7) | (1 << PIN_6) | (1 << PIN_5), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + (1 << PIN_4) | (1 << PIN_3) | (1 << PIN_2) | (1 << PIN_1) | (1 << PIN_0), + 0, + 0, + }}; + +#endif /* __GPIOS_H__ */ diff --git a/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/pins.h b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/pins.h new file mode 100644 index 00000000..7c332c98 --- /dev/null +++ b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/pins.h @@ -0,0 +1,1032 @@ +/* + * Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ + */ +/****************************************************************************** + * @file pins.h + * @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ + * @version v1.0.0 + * @date 2025-10-29 + * @brief Pin MUX and Pin Config settings for "AppKit-e8" + * project with AE822FA0E5597. + * @bug None. + * @note None. + ******************************************************************************/ + +#ifndef __PINS_H__ +#define __PINS_H__ + +#include +#include "pinconf.h" + +struct pinconf { + uint8_t port; + uint8_t pin; + uint8_t alternate_function; + uint8_t pad_control; +}; + +/* Pin Mux and Config Values generated by Conductor Tool */ + +const struct pinconf board_pinconf[] = { + /* P0_0 on pin AA2. Functions: [0]: GPIO0_0, [1]: OSPI0_D0_A, [2]: >>>UART0_RX_A<<<,, [3]: + I3C_SDA_A, [4]: UT0_T0_A [5]: LPCAM_HSYNC_B, [6]: CAM_HSYNC_A, [7]: ANA_S0 */ + /* Selected: UART0_RX_A */ + {PORT_0, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP}, + + /* P0_1 on pin L8. Functions: [0]: GPIO0_1, [1]: OSPI0_D1_A, [2]: >>>UART0_TX_A<<<,, [3]: + I3C_SCL_A, [4]: UT0_T1_A [5]: LPCAM_VSYNC_B, [6]: CAM_VSYNC_A, [7]: ANA_S1 */ + /* Selected: UART0_TX_A */ + {PORT_0, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_2 on pin J8. Functions: [0]: >>>GPIO0_2<<<, [1]: OSPI0_D2_A, [2]: UART0_CTS_A, [3]: + I2C0_SDA_A, [4]: UT1_T0_A, [5]: LPCAM_PCLK_B, [6]: CAM_PCLK_A, [7]: ANA_S2 */ + /* Selected: GPIO0_2 */ + {PORT_0, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_3 on pin P7. Functions: [0]: GPIO0_3, [1]: OSPI0_D3_A, [2]: UART0_RTS_A, [3]: I2C0_SCL_A, + [4]: UT1_T1_A, [5]: LPCAM_XVCLK_B [6]: >>>CAM_XVCLK_A<<<,, [7]: ANA_S3 */ + /* Selected: CAM_XVCLK_A */ + {PORT_0, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_4 on pin T5. Functions: [0]: GPIO0_4, [1]: OSPI0_D4_A, [2]: UART1_RX_A, [3]: PDM_D0_A, + [4]: I2C1_SDA_A, [5]: UT2_T0_A [6]: >>>CAN_RXD_B<<<,, [7]: ANA_S4 */ + /* Selected: CAN_RXD_B */ + {PORT_0, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE}, + + /* P0_5 on pin T3. Functions: [0]: GPIO0_5, [1]: OSPI0_D5_A, [2]: UART1_TX_A, [3]: PDM_C0_A, + [4]: I2C1_SCL_A, [5]: UT2_T1_A [6]: >>>CAN_TXD_B<<<,, [7]: ANA_S5 */ + /* Selected: CAN_TXD_B */ + {PORT_0, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA | PADCTRL_SCHMITT_TRIGGER_ENABLE}, + + /* P0_6 on pin U2. Functions: [0]: GPIO0_6, [1]: OSPI0_D6_A, [2]: UART1_CTS_A, [3]: PDM_D1_A, + [4]: I2C2_SCL_A, [5]: UT3_T0_A, [6]: CAN_STBY_B, [7]: >>>ANA_S6<<< */ + /* Selected: ANA_S6 for "CLICKBOARD_ANA". Can be used with ADC121_IN0 (ADC121 input 0); + ADC24_IN2_N (ADC24 differential input 2 negative); CMP0_IN1 (CMP0 input 1) */ + {PORT_0, PIN_6, PINMUX_ALTERNATE_FUNCTION_7, 0}, + + /* P0_7 on pin T1. Functions: [0]: GPIO0_7, [1]: OSPI0_D7_A, [2]: UART1_RTS_A, [3]: PDM_C1_A, + [4]: I2C2_SDA_A, [5]: UT3_T1_A, [6]: CDC_DE_B, [7]: >>>ANA_S7<<< */ + /* Selected: ANA_S7 for "POTENTIOMETER". Can be used with ADC121_IN1 (ADC121 input 1); + ADC24_IN3_N (ADC24 differential input 3 negative); CMP1_IN1 (CMP1 input 1) */ + {PORT_0, PIN_7, PINMUX_ALTERNATE_FUNCTION_7, 0}, + + /* P1_0 on pin R4. Functions: [0]: GPIO1_0, [1]: >>>UART2_RX_A<<<, [2]: SPI0_MISO_A, [3]: + I2C3_SDA_A, [4]: UT4_T0_A, [5]: LPCAM_HSYNC_C, [6]: ETH_RXD0_C, [7]: ANA_S8 */ + /* Selected: UART2_RX_A for "UARTA" */ + {PORT_1, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_1 on pin P5. Functions: [0]: GPIO1_1, [1]: >>>UART2_TX_A<<<, [2]: SPI0_MOSI_A, [3]: + I2C3_SCL_A, [4]: UT4_T1_A, [5]: LPCAM_VSYNC_C, [6]: ETH_RXD1_C, [7]: ANA_S9 */ + /* Selected: UART2_TX_A for "UARTA" */ + {PORT_1, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_2 on pin N6. Functions: [0]: GPIO1_2, [1]: >>>UART3_RX_A<<<, [2]: SPI0_SCLK_A, [3]: + I3C_SDA_B, [4]: UT5_T0_A, [5]: LPCAM_PCLK_C, [6]: ETH_RST_C, [7]: ANA_S10 */ + /* Selected: UART3_RX_A for "UARTD" */ + {PORT_1, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_3 on pin M7. Functions: [0]: GPIO1_3, [1]: >>>UART3_TX_A<<<, [2]: SPI0_SS0_A, [3]: + I3C_SCL_B, [4]: UT5_T1_A, [5]: LPCAM_XVCLK_C, [6]: ETH_TXD0_C, [7]: ANA_S11 */ + /* Selected: UART3_TX_A for "UARTD" */ + {PORT_1, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_4 on pin P1. Functions: [0]: GPIO1_4, [1]: OSPI0_SS0_A, [2]: >>>UART0_RX_B<<<, [3]: + SPI0_SS1_A, [4]: UT6_T0_A, [5]: LPCAM_D0_C, [6]: ETH_TXD1_C, [7]: ANA_S12 */ + /* Selected: GPIO1_4 */ + {PORT_1, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_5 on pin R2. Functions: [0]: GPIO1_5, [1]: OSPI0_SS1_A, [2]: >>>UART0_TX_B<<<, [3]: + SPI0_SS2_A, [4]: UT6_T1_A, [5]: LPCAM_D1_C, [6]: ETH_TXEN_C, [7]: ANA_S13 */ + /* Selected: GPIO1_5 */ + {PORT_1, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_6 on pin P3. Functions: [0]: GPIO1_6, [1]: >>>OSPI0_RXDS_B<<<, [2]: UART1_RX_B, [3]: + I2S0_SDI_A, [4]: UT7_T0_A, [5]: LPCAM_D2_C, [6]: ETH_IRQ_C, [7]: ANA_S14 */ + /* Selected: OSPI0_RXDS_B for "ISSI RAM" */ + {PORT_1, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_0 on pin M1. Functions: [0]: GPIO2_0, [1]: >>>OSPI0_D0_B<<<, [2]: UART2_RX_B, [3]: + LPPDM_D0_A, [4]: UT8_T0_A, [5]: LPCAM_D4_C, [6]: ETH_MDIO_C, [7]: ANA_S16 */ + /* Selected: OSPI0_D0_B for "ISSI RAM" */ + {PORT_2, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_1 on pin N2. Functions: [0]: GPIO2_1, [1]: >>>OSPI0_D1_B<<<, [2]: UART2_TX_B, [3]: + LPPDM_C0_A, [4]: UT8_T1_A, [5]: LPCAM_D5_C, [6]: ETH_MDC_C, [7]: ANA_S17 */ + /* Selected: OSPI0_D1_B for "ISSI RAM" */ + {PORT_2, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_2 on pin M3. Functions: [0]: GPIO2_2, [1]: >>>OSPI0_D2_B<<<, [2]: UART3_RX_B [3]: + LPPDM_D1_A, [4]: UT9_T0_A, [5]: LPCAM_D6_C, [6]: ETH_CRS_DV_C, [7]: ANA_S18 */ + /* Selected: OSPI0_D2_B */ + {PORT_2, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_3 on pin M5. Functions: [0]: GPIO2_3, [1]: >>>OSPI0_D3_B<<<, [2]: UART3_TX_B [3]: + LPPDM_C1_A, [4]: UT9_T1_A, [5]: LPCAM_D7_C, [6]: CDC_PCLK_B, [7]: ANA_S19 */ + /* Selected: OSPI0_D3_B */ + {PORT_2, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_4 on pin L4. Functions: [0]: GPIO2_4, [1]: >>>OSPI0_D4_B<<<, [2]: LPI2S_SDI_A, [3]: + SPI1_MISO_A, [4]: UT10_T0_A, [5]: LPCAM_D0_B, [6]: CAM_D0_A, [7]: ANA_S20 */ + /* Selected: OSPI0_D4_B for "ISSI RAM" */ + {PORT_2, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_5 on pin K1. Functions: [0]: GPIO2_5, [1]: >>>OSPI0_D5_B<<<, [2]: LPI2S_SDO_A, [3]: + SPI1_MOSI_A, [4]: UT10_T1_A, [5]: LPCAM_D1_B, [6]: CAM_D1_A, [7]: ANA_S21 */ + /* Selected: OSPI0_D5_B for "ISSI RAM" */ + {PORT_2, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_6 on pin L2. Functions: [0]: GPIO2_6, [1]: >>>OSPI0_D6_B<<<, [2]: LPI2S_SCLK_A, [3]: + SPI1_SCLK_A, [4]: UT11_T0_A, [5]: LPCAM_D2_B, [6]: CAM_D2_A, [7]: ANA_S22 */ + /* Selected: OSPI0_D6_B for "ISSI RAM" */ + {PORT_2, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_7 on pin L6. Functions: [0]: GPIO2_7, [1]: >>>OSPI0_D7_B<<<, [2]: LPI2S_WS_A, [3]: + SPI1_SS0_A, [4]: UT11_T1_A, [5]: LPCAM_D3_B, [6]: CAM_D3_A, [7]: ANA_S23 */ + /* Selected: OSPI0_D7_B for "ISSI RAM" */ + {PORT_2, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_0 on pin J12. Functions: [0]: GPIO3_0, [1]: >>>OSPI0_SCLK_B<<<, [2]: UART4_RX_A, [3]: + PDM_D0_B, [4]: I2S0_SCLK_A, [5]: QEC0_X_A, [6]: LPCAM_D4_B, [7]: CAM_D4_A */ + /* Selected: OSPI0_SCLK_B for "ISSI RAM" */ + {PORT_3, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_1 on pin L12. Functions: [0]: GPIO3_1, [1]: >>>OSPI0_SCLKN_B<<<, [2]: UART4_TX_A, [3]: + PDM_C0_B, [4]: I2S0_WS_A, [5]: QEC0_Y_A, [6]: LPCAM_D5_B, [7]: CAM_D5_A */ + /* Selected: OSPI0_SCLKN_B for "ISSI RAM" */ + {PORT_3, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_2 on pin D17. Functions: [0]: GPIO3_2, [1]: >>>OSPI0_SS0_B<<<, [2]: PDM_D1_B, [3]: + I2S1_SDI_A, [4]: I3C_SDA_C, [5]: QEC0_Z_A, [6]: LPCAM_D6_B, [7]: CAM_D6_A */ + /* Selected: OSPI0_SS0_B for "ISSI RAM" */ + {PORT_3, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_3 on pin C18. Functions: [0]: >>>GPIO3_3<<<, [1]: OSPI0_SS1_B, [2]: PDM_C1_B, [3]: + I2S1_SDO_A, [4]: I3C_SCL_C, [5]: QEC1_X_A, [6]: LPCAM_D7_B, [7]: CAM_D7_A */ + /* Selected: GPIO3_3 for "SD_CARD_DETECT" */ + {PORT_3, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P3_4 on pin E14. Functions: [0]: GPIO3_4, [1]: OSPI0_RXDS_A, [2]: UART5_RX_A, [3]: LPPDM_C0_B, + [4]: I2S1_SCLK_A, [5]: >>>I2C0_SCL_B<<<, [6]: QEC1_Y_A, [7]: CAM_D8_A */ + /* Selected: I2C0_SCL_B for "Clickboard,Slave" */ + {PORT_3, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_5 on pin F13. Functions: [0]: GPIO3_5, [1]: OSPI0_SCLKN_A, [2]: UART5_TX_A, [3]: + LPPDM_D0_B, [4]: SPI0_SS1_B, [5]: >>>I2C0_SDA_B<<<, [6]: QEC1_Z_A, [7]: CAM_D9_A */ + /* Selected: I2C0_SDA_B for "Clickboard,Slave" */ + {PORT_3, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_6 on pin AA16. Functions: [0]: GPIO3_6, [1]: Reserved, [2]: LPUART_CTS_B, [3]: + >>>LPPDM_C1_B<<<, [4]: SPI0_SS2_B, [5]: I2C1_SDA_B, [6]: QEC2_X_A, [7]: CAM_D10_A */ + /* Selected: LPPDM_C1_B for "My LPPDM" */ + {PORT_3, PIN_6, PINMUX_ALTERNATE_FUNCTION_3, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P3_7 on pin Y15. Functions: [0]: GPIO3_7, [1]: Reserved, [2]: LPUART_RTS_B, [3]: + >>>LPPDM_D1_B<<<, [4]: SPI1_SS1_A, [5]: I2C1_SCL_B, [6]: QEC2_Y_A, [7]: CAM_D11_A */ + /* Selected: LPPDM_D1_B for "My LPPDM" */ + {PORT_3, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_0 on pin C3. Functions: [0]: >>>GPIO4_0<<<, [1]: Reserved, [2]: Reserved, [3]: I2S1_WS_A, + [4]: SPI1_SS2_A, [5]: QEC2_Z_A, [6]: CDC_VSYNC_B, [7]: CAM_D12_A */ + /* Selected: GPIO4_0 */ + {PORT_4, PIN_0, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_1 on pin D3. Functions: [0]: >>>GPIO4_1<<<, [1]: Reserved, [2]: I2S0_SDI_B, [3]: + SPI1_SS3_A, [4]: QEC3_X_A, [5]: SD_CLK_D, [6]: CDC_HSYNC_B, [7]: CAM_D13_A */ + /* Selected: GPIO4_1 for "UTIMER_GPO0" */ + {PORT_4, PIN_1, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_2 on pin E3. Functions: [0]: >>>GPIO4_2<<<, [1]: Reserved, [2]: Reserved, [3]: + I2S0_SDO_B, [4]: SPI2_MISO_A, [5]: QEC3_Y_A, [6]: SD_CMD_D, [7]: CAM_D14_A */ + /* Selected: GPIO4_2 for "UTIMER_GPO1" */ + {PORT_4, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_3 on pin F3. Functions: [0]: >>>GPIO4_3<<<, [1]: Reserved, [2]: Reserved, [3]: + I2S0_SCLK_B, [4]: SPI2_MOSI_A, [5]: QEC3_Z_A, [6]: SD_RST_D, [7]: CAM_D15_A */ + /* Selected: GPIO4_3 for "UTIMER_GPO2" */ + {PORT_4, PIN_3, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_4 on pin G3. Functions: [0]: GPIO4_4, [1]: >>>JTAG_TCK<<<, [2]: I2S0_WS_B, [3]: + SPI2_SCLK_A, [4]: FAULT0_A */ + /* Selected: JTAG_TCK for "My JTAG" */ + {PORT_4, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_5 on pin H3. Functions: [0]: GPIO4_5, [1]: >>>JTAG_TMS<<<, [2]: SPI2_SS0_A, [3]: FAULT1_A + */ + /* Selected: JTAG_TMS for "My JTAG" */ + {PORT_4, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_6 on pin J3. Functions: [0]: GPIO4_6, [1]: >>>JTAG_TDI<<<, [2]: SPI2_SS1_A, [3]: FAULT2_A + */ + /* Selected: JTAG_TDI for "My JTAG" */ + {PORT_4, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_7 on pin K3. Functions: [0]: GPIO4_7, [1]: >>>JTAG_TDO<<<, [2]: SPI2_SS2_A, [3]: FAULT3_A + */ + /* Selected: JTAG_TDO for "My JTAG" */ + {PORT_4, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P5_0 on pin C4. Functions: [0]: GPIO5_0, [1]: OSPI1_RXDS_A, [2]: UART4_RX_C, [3]: PDM_D2_A, + [4]: SPI0_MISO_B, [5]: I2C2_SDA_B, [6]: UT0_T0_B, [7]: >>>SD_D0_A<<< */ + /* Selected: SD_D0_A for "SDCARD" */ + {PORT_5, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_1 on pin G8. Functions: [0]: GPIO5_1, [1]: OSPI1_SS0_A, [2]: UART4_TX_C, [3]: PDM_D3_A, + [4]: SPI0_MOSI_B, [5]: I2C2_SCL_B, [6]: UT0_T1_B, [7]: >>>SD_D1_A<<< */ + /* Selected: SD_D1_A for "SDCARD" */ + {PORT_5, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_2 on pin B5. Functions: [0]: GPIO5_2, [1]: OSPI1_SCLKN_A, [2]: UART5_RX_C, [3]: PDM_C3_A, + [4]: SPI0_SS0_B, [5]: LPI2C_SCL_B, [6]: UT1_T0_B, [7]: >>>SD_D2_A<<< */ + /* Selected: SD_D2_A for "SDCARD" */ + {PORT_5, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_3 on pin F7. Functions: [0]: GPIO5_3, [1]: OSPI1_SCLK_A, [2]: UART5_TX_C, [3]: + SPI0_SCLK_B, [4]: LPI2C_SDA_B, [5]: UT1_T1_B, [6]: >>>SD_D3_A<<<, [7]: CDC_PCLK_A */ + /* Selected: SD_D3_A for "SDCARD" */ + {PORT_5, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_4 on pin C6. Functions: [0]: GPIO5_4, [1]: OSPI1_SS1_A, [2]: UART3_CTS_A, [3]: + >>>PDM_D2_B<<<, [4]: SPI0_SS3_A, [5]: UT2_T0_B, [6]: SD_D4_A, [7]: CDC_DE_A */ + /* Selected: PDM_D2_B for "PDM MIC" */ + {PORT_5, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_5 on pin A6. Functions: [0]: GPIO5_5, [1]: >>>OSPI1_SCLK_C<<<, [2]: UART3_RTS_A, [3]: + PDM_D3_B, [4]: UT2_T1_B, [5]: SD_D5_A, [6]: ETH_RXD0_A, [7]: CDC_HSYNC_A */ + /* Selected: OSPI1_SCLK_C for "ISSI Flash" */ + {PORT_5, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P5_6 on pin D7. Functions: [0]: GPIO5_6, [1]: UART1_CTS_B, [2]: I2C2_SCL_C, [3]: + >>>UT3_T0_B<<<, [4]: SD_D6_A, [5]: ETH_RXD1_A, [6]: CDC_VSYNC_A */ + /* Selected: UT3_T0_B for "Clickboard PWM" */ + {PORT_5, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_7 on pin B7. Functions: [0]: GPIO5_7, [1]: >>>OSPI1_SS0_C<<<, [2]: UART1_RTS_B, [3]: + I2C2_SDA_C, [4]: UT3_T1_B, [5]: SD_D7_A, [6]: ETH_RST_A */ + /* Selected: OSPI1_SS0_C for "ISSI Flash" */ + {PORT_5, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P6_0 on pin E8. Functions: [0]: GPIO6_0, [1]: OSPI0_D0_C, [2]: UART4_DE_A, [3]: PDM_D0_C, + [4]: UT4_T0_B, [5]: SD_D0_D, [6]: >>>ETH_TXD0_A<<< [7]: LPSPI_SS1_A */ + /* Selected: ETH_TXD0_A for "RTL8201" */ + {PORT_6, PIN_0, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_1 on pin H9. Functions: [0]: >>>GPIO6_1<<<, [1]: OSPI0_D1_C, [2]: UART5_DE_A, [3]: + PDM_C0_C, [4]: UT4_T1_B, [5]: SD_D1_D, [6]: ETH_TXD1_A, [7]: LPSPI_SS2_A */ + /* Selected: GPIO6_1 for "LCD_BACKLIGHT" */ + {PORT_6, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_2 on pin C8. Functions: [0]: >>>GPIO6_2<<<, [1]: OSPI0_D2_C, [2]: UART2_CTS_A, [3]: + LPI3C_SDA_A, [4]: PDM_D1_C, [5]: UT5_T0_B, [6]: SD_D2_D, [7]: ETH_TXEN_A */ + /* Selected: GPIO6_2 for "LEDRGB1_R" */ + {PORT_6, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_3 on pin F9. Functions: [0]: >>>GPIO6_3<<<, [1]: OSPI0_D3_C, [2]: UART2_RTS_A, [3]: + LPI3C_SCL_A, [4]: PDM_C1_C, [5]: UT5_T1_B, [6]: SD_D3_D, [7]: ETH_IRQ_A */ + /* Selected: GPIO6_3 for "UTIMER_GPO3" */ + {PORT_6, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_4 on pin G10. Functions: [0]: >>>GPIO6_4<<<, [1]: OSPI0_D4_C, [2]: UART2_CTS_B, [3]: + LFRC_OUT_A, [4]: SPI1_SS0_B, [5]: UT6_T0_B, [6]: SD_D4_D, [7]: ETH_REFCLK_A */ + /* Selected: GPIO6_4 for "LEDRGB1_G" */ + {PORT_6, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_5 on pin E10. Functions: [0]: >>>GPIO6_5<<<, [1]: OSPI0_D5_C, [2]: UART2_RTS_B, [3]: + * LPI2C1_SDA_B, [4]: SPI1_SS1_B, [5]: UT6_T1_B, [6]: SD_D5_D, [7]: ETH_MDIO_A + */ + /* Selected: GPIO6_5 for "TOUCH_RESET" */ + {PORT_6, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_6 on pin C10. Functions: [0]: >>>GPIO6_6<<<, [1]: OSPI0_D6_C, [2]: UART0_CTS_B, [3]: + Reserved, [4]: SPI1_SS2_B, [5]: UT7_T0_B, [6]: SD_D6_D, [7]: ETH_MDC_A */ + /* Selected: GPIO6_6 for "LEDRGB1_B" */ + {PORT_6, PIN_6, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_7 on pin D11. Functions: [0]: GPIO6_7, [1]: OSPI0_D7_C, [2]: UART0_RTS_B, [3]: + >>>PDM_C2_A<<<, [4]: SPI1_SS3_B, [5]: UT7_T1_B, [6]: SD_D7_D, [7]: ETH_CRS_DV_A */ + /* Selected: PDM_C2_A for "PDM MIC" */ + {PORT_6, PIN_7, PINMUX_ALTERNATE_FUNCTION_3, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_0 on pin A12. Functions: [0]: GPIO7_0, [1]: Reserved, [2]: CMP3_OUT_A, [3]: SPI0_MISO_C, + [4]: I2C0_SDA_C, [5]: UT8_T0_B, [6]: >>>SD_CMD_A<<<, [7]: CAN_RXD_A */ + /* Selected: SD_CMD_A for "SDCARD" */ + {PORT_7, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_1 on pin C12. Functions: [0]: GPIO7_1, [1]: Reserved, [2]: CMP2_OUT_A, [3]: SPI0_MOSI_C, + [4]: I2C0_SCL_C, [5]: UT8_T1_B, [6]: >>>SD_CLK_A<<<, [7]: CAN_TXD_A */ + /* Selected: SD_CLK_A for "SDCARD" */ + {PORT_7, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_2 on pin K11. Functions: [0]: GPIO7_2, [1]: Reserved, [2]: UART3_CTS_B, [3]: CMP1_OUT_A, + [4]: SPI0_SCLK_C, [5]: >>>I2C1_SDA_C<<<, [6]: UT9_T0_B, [7]: SD_RST_A */ + /* Selected: I2C1_SDA_C for "Camera,GT911 Touchscreen,Master" */ + {PORT_7, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P7_3 on pin E12. Functions: [0]: GPIO7_3, [1]: Reserved, [2]: UART3_RTS_B, [3]: CMP0_OUT_A, + [4]: SPI0_SS0_C, [5]: >>>I2C1_SCL_C<<<, [6]: UT9_T1_B, [7]: CAN_STBY_A */ + /* Selected: I2C1_SCL_C for "Camera,GT911 Touchscreen,Master" */ + {PORT_7, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P7_4 on pin T1 {FLEX IO}. Functions: [0]: >>>GPIO7_4<<<, [1]: Reserved, [2]: LPUART_CTS_A, + [3]: LPPDM_C2_A, [4]: LPSPI_MISO_A, [5]: LPI2C_SCL_A, [6]: UT10_T0_B */ + /* Selected: GPIO7_4 for "LEDRGB0_G" */ + {PORT_7, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_5 on pin T2 {FLEX IO}. Functions: [0]: >>>GPIO7_5<<<, [1]: Reserved, [2]: LPUART_RTS_A, + [3]: LFXO_OUT_A, [4]: LPPDM_D2_A, [5]: LPSPI_MOSI_A, [6]: LPI2C_SDA_A, [7]: UT10_T1_B */ + /* Selected: GPIO7_5 for "CAMERA_POWER" */ + {PORT_7, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_6 on pin U3 {FLEX IO}. Functions: [0]: GPIO7_6, [1]: Reserved, [2]: LPUART_RX_A, [3]: + LPI3C_SDA_B, [4]: LPPDM_C3_A, [5]: LPSPI_SCLK_A, [6]: >>>I3C_SDA_D<<<, [7]: UT11_T0_B */ + /* Selected: I3C_SDA_D for "ICM42670 IMU,BMI323 IMU,pin header" */ + {PORT_7, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_7 on pin U1 {FLEX IO}. Functions: [0]: GPIO7_7, [1]: Reserved, [2]: LPUART_TX_A, [3]: + LPI3C_SCL_B, [4]: LPPDM_D3_A, [5]: LPSPI_SS_A, [6]: >>>I3C_SCL_D<<<, [7]: UT11_T1_B */ + /* Selected: I3C_SCL_D for "ICM42670 IMU,BMI323 IMU,pin header" */ + {PORT_7, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_0 on pin B13. Functions: [0]: GPIO8_0, [1]: >>>OSPI1_SCLKN_C<<<, [2]: AUDIO_CLK_A, [3]: + FAULT0_B, [4]: LPCAM_D0_A, [5]: SD_D0_C, [6]: CDC_D0_A, [7]: CAM_D0_B */ + /* Selected: OSPI1_SCLKN_C for "ISSI Flash" */ + {PORT_8, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P8_1 on pin D13. Functions: [0]: >>>GPIO8_1<<<, [1]: I2S2_SDI_A, [2]: FAULT1_B, [3]: + LPCAM_D1_A, [4]: SD_D1_C, [5]: CDC_D1_A, [6]: CAM_D1_B */ + /* Selected: GPIO8_1 for "CLICKBOARD_INT" */ + {PORT_8, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_3 on pin C14. Functions: [0]: >>>GPIO8_3<<<, [1]: I2S2_SCLK_A, [2]: SPI1_MISO_B, [3]: + FAULT3_B, [4]: LPCAM_D3_A, [5]: SD_D3_C, [6]: CDC_D3_A, [7]: CAM_D3_B */ + /* Selected: GPIO8_3 for "CLICKBOARD_RST" */ + {PORT_8, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_4 on pin G12. Functions: [0]: >>>GPIO8_4<<<, [1]: I2S2_WS_A, [2]: SPI1_MOSI_B, [3]: + QEC0_X_B, [4]: LPCAM_D4_A, [5]: SD_D4_C, [6]: CDC_D4_A, [7]: CAM_D4_B */ + /* Selected: GPIO8_4 for "ICM_IMU_IRQ" */ + {PORT_8, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_5 on pin G16. Functions: [0]: GPIO8_5, [1]: >>>HSPI0_RXDS1<<<, [2]: SPI1_SCLK_B, [3]: + QEC0_Y_B, [4]: LPCAM_D5_A, [5]: SD_D5_C, [6]: CDC_D5_A, [7]: CAM_D5_B */ + /* Selected: HSPI0_RXDS1 */ + {PORT_8, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P8_6 on pin H13. Functions: [0]: GPIO8_6, [1]: Reserved, [2]: >>>I2S3_SCLK_B<<<, [3]: + QEC0_Z_B, [4]: LPCAM_D6_A, [5]: SD_D6_C, [6]: CDC_D6_A, [7]: CAM_D6_B */ + /* Selected: I2S3_SCLK_B for "MIC Input" */ + {PORT_8, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_7 on pin G18. Functions: [0]: GPIO8_7, [1]: Reserved, [2]: >>>I2S3_WS_B<<<, [3]: QEC1_X_B, + [4]: LPCAM_D7_A, [5]: SD_D7_C, [6]: CDC_D7_A, [7]: CAM_D7_B */ + /* Selected: I2S3_WS_B for "MIC Input" */ + {PORT_8, PIN_7, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_0 on pin H15. Functions: [0]: GPIO9_0, [1]: Reserved, [2]: >>>I2S3_SDI_B<<<, [3]: QEC1_Y_B, + [4]: SD_CMD_C, [5]: CDC_D8_A, [6]: CAM_D8_B, [7]: LPSPI_SS3_A */ + /* Selected: I2S3_SDI_B for "MIC Input" */ + {PORT_9, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_BUS_REPEATER | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_1 on pin H17. Functions: [0]: >>>GPIO9_1<<<, [1]: LPUART_RX_B, [2]: I2S3_SDO_B, [3]: + QEC1_Z_B, [4]: SD_CLK_C, [5]: CDC_D9_A, [6]: CAM_D9_B, [7]: LPSPI_SS4_A */ + /* Selected: GPIO9_1 for "CAMERA_RESET" */ + {PORT_9, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_2 on pin J14. Functions: [0]: >>>GPIO9_2<<<, [1]: LPUART_TX_B, [2]: I2S3_SDI_A, [3]: + SPI2_MISO_B, [4]: QEC2_X_B, [5]: SD_RST_C, [6]: CDC_D10_A, [7]: CAM_D10_B */ + /* Selected: GPIO9_2 for "CAMERA_FLASH" */ + {PORT_9, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_3 on pin K13. Functions: [0]: >>>GPIO9_3<<<, [1]: Reserved, [2]: UART7_RX_B, [3]: + I2S3_SDO_A, [4]: SPI2_MOSI_B, [5]: QEC2_Y_B, [6]: CDC_D11_A, [7]: CAM_D11_B */ + /* Selected: GPIO9_3 for "CAMERA_TRIGGER" */ + {PORT_9, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_4 on pin J18. Functions: [0]: >>>GPIO9_4<<<, [1]: UART7_TX_B, [2]: I2S3_SCLK_A, [3]: + SPI2_SCLK_B, [4]: I2C3_SDA_C, [5]: QEC2_Z_B, [6]: CDC_D12_A, [7]: CAM_D12_B */ + /* Selected: GPIO9_4 for "TOUCH_INT" */ + {PORT_9, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_5 on pin J16. Functions: [0]: GPIO9_5, [1]: >>>OSPI1_D0_C<<<, [2]: I2S3_WS_A, [3]: + SPI2_SS0_B, [4]: I2C3_SCL_C, [5]: QEC3_X_B, [6]: CDC_D13_A, [7]: CAM_D13_B */ + /* Selected: OSPI1_D0_C for "ISSI Flash" */ + {PORT_9, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P9_6 on pin K17. Functions: [0]: GPIO9_6, [1]: >>>OSPI1_D1_C<<<, [2]: AUDIO_CLK_B, [3]: + SPI2_SS1_B, [4]: I2C3_SDA_B, [5]: QEC3_Y_B, [6]: CDC_D14_A, [7]: CAM_D14_B */ + /* Selected: OSPI1_D1_C for "ISSI Flash" */ + {PORT_9, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P9_7 on pin L16. Functions: [0]: GPIO9_7, [1]: >>>OSPI1_D2_C<<<, [2]: UART7_DE_B, [3]: + SPI2_SS2_B, [4]: I2C3_SCL_B, [5]: QEC3_Z_B, [6]: CDC_D15_A, [7]: CAM_D15_B */ + /* Selected: OSPI1_D2_C for "ISSI Flash" */ + {PORT_9, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_0 on pin M13. Functions: [0]: GPIO10_0, [1]: >>>OSPI1_D3_C<<<, [2]: UART6_DE_B, [3]: + SPI2_SS3_B, [4]: UT0_T0_C, [5]: LPCAM_HSYNC_A, [6]: CDC_D16_A, [7]: CAM_HSYNC_B */ + /* Selected: OSPI1_D3_C for "ISSI Flash" */ + {PORT_10, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_1 on pin M15. Functions: [0]: GPIO10_1, [1]: >>>OSPI1_D4_C<<<, [2]: Reserved, [3]: + LPI2S_SDI_B, [4]: UT0_T1_C, [5]: LPCAM_VSYNC_A, [6]: CDC_D17_A, [7]: CAM_VSYNC_B */ + /* Selected: OSPI1_D4_C for "ISSI Flash" */ + {PORT_10, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_2 on pin N18. Functions: [0]: GPIO10_2, [1]: >>>OSPI1_D5_C<<<, [2]: Reserved, [3]: + LPI2S_SDO_B, [4]: UT1_T0_C, [5]: LPCAM_PCLK_A, [6]: CDC_D18_A, [7]: CAM_PCLK_B */ + /* Selected: OSPI1_D5_C for "ISSI Flash" */ + {PORT_10, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_3 on pin R15. Functions: [0]: GPIO10_3, [1]: >>>OSPI1_D6_C<<<, [2]: Reserved, [3]: + LPI2S_SCLK_B, [4]: UT1_T1_C, [5]: LPCAM_XVCLK_A, [6]: CDC_D19_A, [7]: CAM_XVCLK_B */ + /* Selected: OSPI1_D6_C for "ISSI Flash" */ + {PORT_10, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_4 on pin R16. Functions: [0]: GPIO10_4, [1]: >>>OSPI1_D7_C<<<, [2]: Reserved, [3]: + LPI2S_WS_B, [4]: I2C0_SDA_D, [5]: UT2_T0_C, [6]: ETH_TXD0_B, [7]: CDC_D20_A */ + /* Selected: OSPI1_D7_C for "ISSI Flash" */ + {PORT_10, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_5 on pin P14. Functions: [0]: GPIO10_5, [1]: UART6_RX_A, [2]: I2S2_SDI_B, [3]: + SPI3_MISO_B, [4]: I2C0_SCL_D, [5]: UT2_T1_C, [6]: >>>ETH_TXD1_B<<<, [7]: CDC_D21_A */ + /* Selected: ETH_TXD1_B for "RTL8201" */ + {PORT_10, PIN_5, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P10_6 on pin T15. Functions: [0]: GPIO10_6, [1]: UART6_TX_A, [2]: I2S2_SDO_B, [3]: + SPI3_MOSI_B, [4]: I2C1_SDA_D, [5]: UT3_T0_C, [6]: >>>ETH_TXEN_B<<<, [7]: CDC_D22_A */ + /* Selected: ETH_TXEN_B for "RTL8201" */ + {PORT_10, PIN_6, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P10_7 on pin T17. Functions: [0]: GPIO10_7, [1]: UART7_RX_A, [2]: I2S2_SCLK_B, [3]: + SPI3_SCLK_B, [4]: I2C1_SCL_D, [5]: UT3_T1_C, [6]: CDC_D23_A, [7]: >>>OSPI1_RXDS_C<<< */ + /* Selected: OSPI1_RXDS_C for "ISSI Flash" */ + {PORT_10, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P11_0 on pin P13. Functions: [0]: GPIO11_0, [1]: OSPI1_D0_A, [2]: UART7_TX_A, [3]: I2S2_WS_B, + [4]: SPI3_SS0_B, [5]: UT4_T0_C, [6]: >>>ETH_REFCLK_B<<<, [7]: CDC_D0_B */ + /* Selected: ETH_REFCLK_B for "RTL8201" */ + {PORT_11, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_1 on pin U18. Functions: [0]: GPIO11_1, [1]: OSPI1_D1_A, [2]: UART7_DE_A, [3]: SPI3_SS1_B, + [4]: UT4_T1_C, [5]: >>>ETH_MDIO_B<<<, [6]: CDC_D1_B, [7]: LPSPI_SS5_A */ + /* Selected: ETH_MDIO_B for "RTL8201" */ + {PORT_11, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_2 on pin N12. Functions: [0]: GPIO11_2, [1]: OSPI1_D2_A, [2]: UART6_DE_A, [3]: LPPDM_C2_B, + [4]: SPI3_SS2_B, [5]: UT5_T0_C, [6]: >>>ETH_MDC_B<<<, [7]: CDC_D2_B */ + /* Selected: ETH_MDC_B for "RTL8201" */ + {PORT_11, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_3 on pin M11. Functions: [0]: GPIO11_3, [1]: OSPI1_D3_A, [2]: UART5_RX_B, [3]: LPPDM_C3_B, + [4]: SPI3_SS3_B, [5]: UT5_T1_C, [6]: >>>ETH_RXD0_B<<<, [7]: CDC_D3_B */ + /* Selected: ETH_RXD0_B for "RTL8201" */ + {PORT_11, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_4 on pin Y13. Functions: [0]: GPIO11_4, [1]: OSPI1_D4_A, [2]: UART5_TX_B, [3]: PDM_C2_B, + [4]: LPSPI_MISO_B, [5]: UT6_T0_C, [6]: >>>ETH_RXD1_B<<<, [7]: CDC_D4_B */ + /* Selected: ETH_RXD1_B for "RTL8201" */ + {PORT_11, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_5 on pin AD17. Functions: [0]: GPIO11_5, [1]: OSPI1_D5_A, [2]: UART6_RX_B, [3]: PDM_C3_B, + [4]: LPSPI_MOSI_B, [5]: UT6_T1_C, [6]: >>>ETH_CRS_DV_B<<<, [7]: CDC_D5_B */ + /* Selected: ETH_CRS_DV_B for "RTL8201" */ + {PORT_11, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_6 on pin AA14. Functions: [0]: GPIO11_6, [1]: OSPI1_D6_A, [2]: UART6_TX_B, [3]: LPPDM_D2_B, + [4]: LPSPI_SCLK_B, [5]: UT7_T0_C, [6]: >>>ETH_RST_B<<<, [7]: CDC_D6_B */ + /* Selected: ETH_RST_B for "RTL8201" */ + {PORT_11, PIN_6, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_7 on pin AC16. Functions: [0]: GPIO11_7, [1]: OSPI1_D7_A, [2]: UART5_DE_B, [3]: LPPDM_D3_B, + [4]: LPSPI_SS_B, [5]: UT7_T1_C, [6]: >>>ETH_IRQ_B<<<, [7]: CDC_D7_B */ + /* Selected: ETH_IRQ_B for "RTL8201" */ + {PORT_11, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_0 on pin E2. Functions: [0]: >>>GPIO12_0<<<, [1]: OSPI0_SCLK_C, [2]: AUDIO_CLK_C, [3]: + I2S1_SDI_B, [4]: UT8_T0_C, [5]: CDC_D8_B, [7]: LPUT0_T0_B */ + /* Selected: GPIO12_0 for "LEDRGB0_B" */ + {PORT_12, PIN_0, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_1 on pin D1. Functions: [0]: GPIO12_1, [1]: OSPI0_SCLKN_C, [2]: >>>UART4_RX_B<<<, [3]: + I2S1_SDO_B, [4]: UT8_T1_C, [5]: CDC_D9_B, [7]: LPUT0_T1_B */ + /* Selected: UART4_RX_B for "UARTB" */ + {PORT_12, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_2 on pin K5. Functions: [0]: GPIO12_2, [1]: OSPI0_RXDS_C, [2]: >>>UART4_TX_B<<<, [3]: + I2S1_SCLK_B, [4]: UT9_T0_C, [5]: CDC_D10_B */ + /* Selected: UART4_TX_B for "UARTB" */ + {PORT_12, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_3 on pin J6. Functions: [0]: >>>GPIO12_3<<<, [1]: OSPI0_SS0_C, [2]: UART4_DE_B, [3]: + I2S1_WS_B, [4]: UT9_T1_C, [5]: CDC_D11_B */ + /* Selected: GPIO12_3 for "LEDRGB0_R" */ + {PORT_12, PIN_3, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_4 on pin A10. Functions: [0]: GPIO12_4, [1]: OSPI0_SS1_C, [2]: SPI3_MISO_A, [3]: + UT10_T0_C, [4]: >>>CAN_RXD_C<<<, [5]: CDC_D12_B */ + /* Selected: CAN_RXD_C for "CAN Transceiver" */ + {PORT_12, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_5 on pin J10. Functions: [0]: GPIO12_5, [1]: Reserved, [2]: SPI3_MOSI_A, [3]: UT10_T1_C, + [4]: >>>CAN_TXD_C<<<, [5]: CDC_D13_B */ + /* Selected: CAN_TXD_C for "CAN Transceiver" */ + {PORT_12, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_6 on pin H11. Functions: [0]: GPIO12_6, [1]: Reserved, [2]: SPI3_SCLK_A, [3]: UT11_T0_C, + [4]: >>>CAN_STBY_C<<<, [5]: CDC_D14_B */ + /* Selected: CAN_STBY_C for "CAN Transceiver" */ + {PORT_12, PIN_6, PINMUX_ALTERNATE_FUNCTION_4, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_0 on pin H3. Functions: [0]: GPIO13_0, [1]: OSPI1_D0_B, [2]: Reserved, [3]: SPI3_SS1_A, + [4]: >>>QEC0_X_C<<<, [5]: SD_D0_B, [6]: CDC_D16_B */ + /* Selected: QEC0_X_C for "Encoder" */ + {PORT_13, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_1 on pin G2. Functions: [0]: GPIO13_1, [1]: OSPI1_D1_B, [2]: SPI3_SS2_A, [3]: + >>>QEC0_Y_C<<<, [4]: SD_D1_B, [5]: CDC_D17_B */ + /* Selected: QEC0_Y_C for "Encoder" */ + {PORT_13, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_2 on pin F1. Functions: [0]: GPIO13_2, [1]: OSPI1_D2_B, [2]: SPI3_SS3_A, [3]: + >>>QEC0_Z_C<<<, [4]: SD_D2_B, [5]: CDC_D18_B */ + /* Selected: QEC0_Z_C for "Encoder" */ + {PORT_13, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_4 on pin G4. Functions: [0]: >>>GPIO13_4<<<, [1]: OSPI1_D4_B, [2]: LPI2S_SDI_C, [3]: + QEC1_Y_C, [4]: SD_D4_B, [5]: CDC_D20_B */ + /* Selected: GPIO13_4 */ + {PORT_13, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_5 on pin D5. Functions: [0]: >>>GPIO13_5<<<, [1]: OSPI1_D5_B, [2]: LPI2S_SDO_C, [3]: + QEC1_Z_C, [4]: SD_D5_B, [5]: CDC_D21_B */ + /* Selected: GPIO13_5 */ + {PORT_13, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_6 on pin E6. Functions: [0]: >>>GPIO13_6<<<, [1]: OSPI1_D6_B, [2]: LPI2S_SCLK_C, [3]: + QEC2_X_C, [4]: SD_D6_B, [5]: CDC_D22_B */ + /* Selected: GPIO13_6 */ + {PORT_13, PIN_6, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_7 on pin A4. Functions: [0]: >>>GPIO13_7<<<, [1]: OSPI1_D7_B, [2]: LPI2S_WS_C, [3]: + QEC2_Y_C, [4]: SD_D7_B, [5]: CDC_D23_B */ + /* Selected: GPIO13_7 */ + {PORT_13, PIN_7, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_0 on pin B11. Functions: [0]: GPIO14_0 [1]: OSPI1_SCLK_B, [2]: >>>UART6_RX_C<<<,, [3]: + QEC2_Z_C, [4]: SD_CMD_B, [5]: LFRC_OUT_B */ + /* Selected: UART6_RX_C */ + {PORT_14, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP}, + + /* P14_1 on pin G14. Functions: [0]: GPIO14_1 [1]: OSPI1_SCLKN_B, [2]: >>>UART6_TX_C<<<,, [3]: + Reserved, [4]: QEC3_X_C, [5]: SD_CLK_B, [6]: LFXO_OUT_B */ + /* Selected: UART6_TX_C */ + {PORT_14, PIN_1, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_2 on pin F15. Functions: [0]: >>>GPIO14_2<<<, [1]: OSPI1_SS0_B, [2]: UART7_RX_C, [3]: + LPI3C_SDA_C, [4]: QEC3_Y_C, [5]: SD_RST_B */ + /* Selected: GPIO14_2 for "QEC_Z_GPO" */ + {PORT_14, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_4 on pin W12. Functions: [0]: >>>GPIO14_4<<<, [1]: CMP3_OUT_B, [2]: SPI1_MISO_C, [3]: + FAULT0_C */ + /* Selected: GPIO14_4 */ + {PORT_14, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_5 on pin V11. Functions: [0]: >>>CGPIO14_5<<<, [1]: CMP2_OUT_B, [2]: SPI1_MOSI_C, [3]: + FAULT1_C */ + /* Selected: GPIO14_5 */ + {PORT_14, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_6 on pin Y11. Functions: [0]: >>>GPIO14_6<<<, [1]: CMP1_OUT_B, [2]: SPI1_SCLK_C, [3]: + FAULT2_C */ + /* Selected: GPIO14_6 */ + {PORT_14, PIN_6, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_7 on pin AD15. Functions: [0]: >>>GPIO14_7<<<, [1]: CMP0_OUT_B, [2]: SPI1_SS0_C, [3]: + FAULT3_C */ + /* Selected: GPIO14_7 */ + {PORT_14, PIN_7, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_0 on pin V2 {FLEX IO}. Functions: [0]: >>>GPIOV_0<<<, [1]: LPTMR0_CLK_IO. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_0 for "JOY_SW_A" */ + {PORT_15, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_1 on pin W2 {FLEX IO}. Functions: [0]: >>>GPIOV_1<<<, [1]: LPTMR1_CLK_OUT. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_1 for "JOY_SW_B" */ + {PORT_15, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_2 on pin U2 {FLEX IO}. Functions: [0]: >>>GPIOV_2<<<, [1]: LPTMR2_CLK_IO. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_2 for "JOY_SW_C" */ + {PORT_15, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_3 on pin V1 {FLEX IO}. Functions: [0]: >>>GPIOV_3<<<, [1]: LPTMR3_CLK_OUT. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_3 for "JOY_SW_D" */ + {PORT_15, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_4 on pin T11. Functions: [0]: >>>GPIOV_4<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_4 for "JOY_SW_CENTER" */ + {PORT_15, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_5 on pin V13. Functions: [0]: >>>GPIOV_5<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_5 for "BT_HWAKE" */ + {PORT_15, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_6 on pin AC18. Functions: [0]: >>>GPIOV_6<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_6 for "WIFI_HWAKE" */ + {PORT_15, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_7 on pin W14. Functions: [0]: >>>GPIOV_7<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_7 for "HSPI1_RESETn" */ + {PORT_15, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P16_0 Functions: [0]: GPIO16_0, [1]: >>>HSPI0_D8<<< */ + /* Selected: HSPI0_D8 */ + {PORT_16, PIN_0, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_1 Functions: [0]: GPIO16_1, [1]: >>>HSPI0_D9<<< */ + /* Selected: HSPI0_D9 */ + {PORT_16, PIN_1, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_2 Functions: [0]: GPIO16_2, [1]: >>>HSPI0_D10<<< */ + /* Selected: HSPI0_D10 */ + {PORT_16, PIN_2, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_3 Functions: [0]: GPIO16_3, [1]: >>>HSPI0_D11<<< */ + /* Selected: HSPI0_D11 */ + {PORT_16, PIN_3, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_4 Functions: [0]: GPIO16_4, [1]: >>>HSPI0_D12<<< */ + /* Selected: HSPI0_D12 */ + {PORT_16, PIN_4, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_5 Functions: [0]: GPIO16_5, [1]: >>>HSPI0_D13<<< */ + /* Selected: HSPI0_D13 */ + {PORT_16, PIN_5, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_6 Functions: [0]: GPIO16_6, [1]: >>>HSPI0_D14<<< */ + /* Selected: HSPI0_D14 */ + {PORT_16, PIN_6, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_7 Functions: [0]: GPIO16_7, [1]: >>>HSPI0_D15<<< */ + /* Selected: HSPI0_D15 */ + {PORT_16, PIN_7, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_0 Functions: [0]: GPIO17_0, [1]: >>>HSPI1_D8<<< */ + /* Selected: HSPI1_D8 */ + {PORT_17, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_1 Functions: [0]: GPIO17_1, [1]: >>>HSPI1_D9<<< */ + /* Selected: HSPI1_D9 */ + {PORT_17, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_2 Functions: [0]: GPIO17_2, [1]: >>>HSPI1_D10<<< */ + /* Selected: HSPI1_D10 */ + {PORT_17, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_3 Functions: [0]: GPIO17_3, [1]: >>>HSPI1_D11<<< */ + /* Selected: HSPI1_D11 */ + {PORT_17, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_4 Functions: [0]: GPIO17_4, [1]: >>>HSPI1_D12<<< */ + /* Selected: HSPI1_D12 */ + {PORT_17, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_5 Functions: [0]: GPIO17_5, [1]: >>>HSPI1_D13<<< */ + /* Selected: HSPI1_D13 */ + {PORT_17, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_6 Functions: [0]: GPIO17_6, [1]: >>>HSPI1_D14<<< */ + /* Selected: HSPI1_D14 */ + {PORT_17, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_7 Functions: [0]: GPIO17_7, [1]: >>>HSPI1_D15<<< */ + /* Selected: HSPI1_D15 */ + {PORT_17, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, +}; + +#endif /* __PINS_H__ */ diff --git a/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/pins.h.base@2.2.0 b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/pins.h.base@2.2.0 new file mode 100644 index 00000000..7c332c98 --- /dev/null +++ b/board/AppKit-E8/RTE/BSP/AE822FA0E5597BS0_M55_HP/pins.h.base@2.2.0 @@ -0,0 +1,1032 @@ +/* + * Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * https://alifsemi.com/contact/, or visit: https://alifsemi.com/license/ + */ +/****************************************************************************** + * @file pins.h + * @author Auto generated by Conductor Tool https://conductor.alifsemi.com/ + * @version v1.0.0 + * @date 2025-10-29 + * @brief Pin MUX and Pin Config settings for "AppKit-e8" + * project with AE822FA0E5597. + * @bug None. + * @note None. + ******************************************************************************/ + +#ifndef __PINS_H__ +#define __PINS_H__ + +#include +#include "pinconf.h" + +struct pinconf { + uint8_t port; + uint8_t pin; + uint8_t alternate_function; + uint8_t pad_control; +}; + +/* Pin Mux and Config Values generated by Conductor Tool */ + +const struct pinconf board_pinconf[] = { + /* P0_0 on pin AA2. Functions: [0]: GPIO0_0, [1]: OSPI0_D0_A, [2]: >>>UART0_RX_A<<<,, [3]: + I3C_SDA_A, [4]: UT0_T0_A [5]: LPCAM_HSYNC_B, [6]: CAM_HSYNC_A, [7]: ANA_S0 */ + /* Selected: UART0_RX_A */ + {PORT_0, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP}, + + /* P0_1 on pin L8. Functions: [0]: GPIO0_1, [1]: OSPI0_D1_A, [2]: >>>UART0_TX_A<<<,, [3]: + I3C_SCL_A, [4]: UT0_T1_A [5]: LPCAM_VSYNC_B, [6]: CAM_VSYNC_A, [7]: ANA_S1 */ + /* Selected: UART0_TX_A */ + {PORT_0, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_2 on pin J8. Functions: [0]: >>>GPIO0_2<<<, [1]: OSPI0_D2_A, [2]: UART0_CTS_A, [3]: + I2C0_SDA_A, [4]: UT1_T0_A, [5]: LPCAM_PCLK_B, [6]: CAM_PCLK_A, [7]: ANA_S2 */ + /* Selected: GPIO0_2 */ + {PORT_0, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_3 on pin P7. Functions: [0]: GPIO0_3, [1]: OSPI0_D3_A, [2]: UART0_RTS_A, [3]: I2C0_SCL_A, + [4]: UT1_T1_A, [5]: LPCAM_XVCLK_B [6]: >>>CAM_XVCLK_A<<<,, [7]: ANA_S3 */ + /* Selected: CAM_XVCLK_A */ + {PORT_0, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P0_4 on pin T5. Functions: [0]: GPIO0_4, [1]: OSPI0_D4_A, [2]: UART1_RX_A, [3]: PDM_D0_A, + [4]: I2C1_SDA_A, [5]: UT2_T0_A [6]: >>>CAN_RXD_B<<<,, [7]: ANA_S4 */ + /* Selected: CAN_RXD_B */ + {PORT_0, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE}, + + /* P0_5 on pin T3. Functions: [0]: GPIO0_5, [1]: OSPI0_D5_A, [2]: UART1_TX_A, [3]: PDM_C0_A, + [4]: I2C1_SCL_A, [5]: UT2_T1_A [6]: >>>CAN_TXD_B<<<,, [7]: ANA_S5 */ + /* Selected: CAN_TXD_B */ + {PORT_0, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA | PADCTRL_SCHMITT_TRIGGER_ENABLE}, + + /* P0_6 on pin U2. Functions: [0]: GPIO0_6, [1]: OSPI0_D6_A, [2]: UART1_CTS_A, [3]: PDM_D1_A, + [4]: I2C2_SCL_A, [5]: UT3_T0_A, [6]: CAN_STBY_B, [7]: >>>ANA_S6<<< */ + /* Selected: ANA_S6 for "CLICKBOARD_ANA". Can be used with ADC121_IN0 (ADC121 input 0); + ADC24_IN2_N (ADC24 differential input 2 negative); CMP0_IN1 (CMP0 input 1) */ + {PORT_0, PIN_6, PINMUX_ALTERNATE_FUNCTION_7, 0}, + + /* P0_7 on pin T1. Functions: [0]: GPIO0_7, [1]: OSPI0_D7_A, [2]: UART1_RTS_A, [3]: PDM_C1_A, + [4]: I2C2_SDA_A, [5]: UT3_T1_A, [6]: CDC_DE_B, [7]: >>>ANA_S7<<< */ + /* Selected: ANA_S7 for "POTENTIOMETER". Can be used with ADC121_IN1 (ADC121 input 1); + ADC24_IN3_N (ADC24 differential input 3 negative); CMP1_IN1 (CMP1 input 1) */ + {PORT_0, PIN_7, PINMUX_ALTERNATE_FUNCTION_7, 0}, + + /* P1_0 on pin R4. Functions: [0]: GPIO1_0, [1]: >>>UART2_RX_A<<<, [2]: SPI0_MISO_A, [3]: + I2C3_SDA_A, [4]: UT4_T0_A, [5]: LPCAM_HSYNC_C, [6]: ETH_RXD0_C, [7]: ANA_S8 */ + /* Selected: UART2_RX_A for "UARTA" */ + {PORT_1, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_1 on pin P5. Functions: [0]: GPIO1_1, [1]: >>>UART2_TX_A<<<, [2]: SPI0_MOSI_A, [3]: + I2C3_SCL_A, [4]: UT4_T1_A, [5]: LPCAM_VSYNC_C, [6]: ETH_RXD1_C, [7]: ANA_S9 */ + /* Selected: UART2_TX_A for "UARTA" */ + {PORT_1, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_2 on pin N6. Functions: [0]: GPIO1_2, [1]: >>>UART3_RX_A<<<, [2]: SPI0_SCLK_A, [3]: + I3C_SDA_B, [4]: UT5_T0_A, [5]: LPCAM_PCLK_C, [6]: ETH_RST_C, [7]: ANA_S10 */ + /* Selected: UART3_RX_A for "UARTD" */ + {PORT_1, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_3 on pin M7. Functions: [0]: GPIO1_3, [1]: >>>UART3_TX_A<<<, [2]: SPI0_SS0_A, [3]: + I3C_SCL_B, [4]: UT5_T1_A, [5]: LPCAM_XVCLK_C, [6]: ETH_TXD0_C, [7]: ANA_S11 */ + /* Selected: UART3_TX_A for "UARTD" */ + {PORT_1, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_4 on pin P1. Functions: [0]: GPIO1_4, [1]: OSPI0_SS0_A, [2]: >>>UART0_RX_B<<<, [3]: + SPI0_SS1_A, [4]: UT6_T0_A, [5]: LPCAM_D0_C, [6]: ETH_TXD1_C, [7]: ANA_S12 */ + /* Selected: GPIO1_4 */ + {PORT_1, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_5 on pin R2. Functions: [0]: GPIO1_5, [1]: OSPI0_SS1_A, [2]: >>>UART0_TX_B<<<, [3]: + SPI0_SS2_A, [4]: UT6_T1_A, [5]: LPCAM_D1_C, [6]: ETH_TXEN_C, [7]: ANA_S13 */ + /* Selected: GPIO1_5 */ + {PORT_1, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P1_6 on pin P3. Functions: [0]: GPIO1_6, [1]: >>>OSPI0_RXDS_B<<<, [2]: UART1_RX_B, [3]: + I2S0_SDI_A, [4]: UT7_T0_A, [5]: LPCAM_D2_C, [6]: ETH_IRQ_C, [7]: ANA_S14 */ + /* Selected: OSPI0_RXDS_B for "ISSI RAM" */ + {PORT_1, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_0 on pin M1. Functions: [0]: GPIO2_0, [1]: >>>OSPI0_D0_B<<<, [2]: UART2_RX_B, [3]: + LPPDM_D0_A, [4]: UT8_T0_A, [5]: LPCAM_D4_C, [6]: ETH_MDIO_C, [7]: ANA_S16 */ + /* Selected: OSPI0_D0_B for "ISSI RAM" */ + {PORT_2, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_1 on pin N2. Functions: [0]: GPIO2_1, [1]: >>>OSPI0_D1_B<<<, [2]: UART2_TX_B, [3]: + LPPDM_C0_A, [4]: UT8_T1_A, [5]: LPCAM_D5_C, [6]: ETH_MDC_C, [7]: ANA_S17 */ + /* Selected: OSPI0_D1_B for "ISSI RAM" */ + {PORT_2, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_2 on pin M3. Functions: [0]: GPIO2_2, [1]: >>>OSPI0_D2_B<<<, [2]: UART3_RX_B [3]: + LPPDM_D1_A, [4]: UT9_T0_A, [5]: LPCAM_D6_C, [6]: ETH_CRS_DV_C, [7]: ANA_S18 */ + /* Selected: OSPI0_D2_B */ + {PORT_2, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_3 on pin M5. Functions: [0]: GPIO2_3, [1]: >>>OSPI0_D3_B<<<, [2]: UART3_TX_B [3]: + LPPDM_C1_A, [4]: UT9_T1_A, [5]: LPCAM_D7_C, [6]: CDC_PCLK_B, [7]: ANA_S19 */ + /* Selected: OSPI0_D3_B */ + {PORT_2, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_4 on pin L4. Functions: [0]: GPIO2_4, [1]: >>>OSPI0_D4_B<<<, [2]: LPI2S_SDI_A, [3]: + SPI1_MISO_A, [4]: UT10_T0_A, [5]: LPCAM_D0_B, [6]: CAM_D0_A, [7]: ANA_S20 */ + /* Selected: OSPI0_D4_B for "ISSI RAM" */ + {PORT_2, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_5 on pin K1. Functions: [0]: GPIO2_5, [1]: >>>OSPI0_D5_B<<<, [2]: LPI2S_SDO_A, [3]: + SPI1_MOSI_A, [4]: UT10_T1_A, [5]: LPCAM_D1_B, [6]: CAM_D1_A, [7]: ANA_S21 */ + /* Selected: OSPI0_D5_B for "ISSI RAM" */ + {PORT_2, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_6 on pin L2. Functions: [0]: GPIO2_6, [1]: >>>OSPI0_D6_B<<<, [2]: LPI2S_SCLK_A, [3]: + SPI1_SCLK_A, [4]: UT11_T0_A, [5]: LPCAM_D2_B, [6]: CAM_D2_A, [7]: ANA_S22 */ + /* Selected: OSPI0_D6_B for "ISSI RAM" */ + {PORT_2, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P2_7 on pin L6. Functions: [0]: GPIO2_7, [1]: >>>OSPI0_D7_B<<<, [2]: LPI2S_WS_A, [3]: + SPI1_SS0_A, [4]: UT11_T1_A, [5]: LPCAM_D3_B, [6]: CAM_D3_A, [7]: ANA_S23 */ + /* Selected: OSPI0_D7_B for "ISSI RAM" */ + {PORT_2, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_0 on pin J12. Functions: [0]: GPIO3_0, [1]: >>>OSPI0_SCLK_B<<<, [2]: UART4_RX_A, [3]: + PDM_D0_B, [4]: I2S0_SCLK_A, [5]: QEC0_X_A, [6]: LPCAM_D4_B, [7]: CAM_D4_A */ + /* Selected: OSPI0_SCLK_B for "ISSI RAM" */ + {PORT_3, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_1 on pin L12. Functions: [0]: GPIO3_1, [1]: >>>OSPI0_SCLKN_B<<<, [2]: UART4_TX_A, [3]: + PDM_C0_B, [4]: I2S0_WS_A, [5]: QEC0_Y_A, [6]: LPCAM_D5_B, [7]: CAM_D5_A */ + /* Selected: OSPI0_SCLKN_B for "ISSI RAM" */ + {PORT_3, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_2 on pin D17. Functions: [0]: GPIO3_2, [1]: >>>OSPI0_SS0_B<<<, [2]: PDM_D1_B, [3]: + I2S1_SDI_A, [4]: I3C_SDA_C, [5]: QEC0_Z_A, [6]: LPCAM_D6_B, [7]: CAM_D6_A */ + /* Selected: OSPI0_SS0_B for "ISSI RAM" */ + {PORT_3, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_3 on pin C18. Functions: [0]: >>>GPIO3_3<<<, [1]: OSPI0_SS1_B, [2]: PDM_C1_B, [3]: + I2S1_SDO_A, [4]: I3C_SCL_C, [5]: QEC1_X_A, [6]: LPCAM_D7_B, [7]: CAM_D7_A */ + /* Selected: GPIO3_3 for "SD_CARD_DETECT" */ + {PORT_3, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P3_4 on pin E14. Functions: [0]: GPIO3_4, [1]: OSPI0_RXDS_A, [2]: UART5_RX_A, [3]: LPPDM_C0_B, + [4]: I2S1_SCLK_A, [5]: >>>I2C0_SCL_B<<<, [6]: QEC1_Y_A, [7]: CAM_D8_A */ + /* Selected: I2C0_SCL_B for "Clickboard,Slave" */ + {PORT_3, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_5 on pin F13. Functions: [0]: GPIO3_5, [1]: OSPI0_SCLKN_A, [2]: UART5_TX_A, [3]: + LPPDM_D0_B, [4]: SPI0_SS1_B, [5]: >>>I2C0_SDA_B<<<, [6]: QEC1_Z_A, [7]: CAM_D9_A */ + /* Selected: I2C0_SDA_B for "Clickboard,Slave" */ + {PORT_3, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P3_6 on pin AA16. Functions: [0]: GPIO3_6, [1]: Reserved, [2]: LPUART_CTS_B, [3]: + >>>LPPDM_C1_B<<<, [4]: SPI0_SS2_B, [5]: I2C1_SDA_B, [6]: QEC2_X_A, [7]: CAM_D10_A */ + /* Selected: LPPDM_C1_B for "My LPPDM" */ + {PORT_3, PIN_6, PINMUX_ALTERNATE_FUNCTION_3, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P3_7 on pin Y15. Functions: [0]: GPIO3_7, [1]: Reserved, [2]: LPUART_RTS_B, [3]: + >>>LPPDM_D1_B<<<, [4]: SPI1_SS1_A, [5]: I2C1_SCL_B, [6]: QEC2_Y_A, [7]: CAM_D11_A */ + /* Selected: LPPDM_D1_B for "My LPPDM" */ + {PORT_3, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_0 on pin C3. Functions: [0]: >>>GPIO4_0<<<, [1]: Reserved, [2]: Reserved, [3]: I2S1_WS_A, + [4]: SPI1_SS2_A, [5]: QEC2_Z_A, [6]: CDC_VSYNC_B, [7]: CAM_D12_A */ + /* Selected: GPIO4_0 */ + {PORT_4, PIN_0, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_1 on pin D3. Functions: [0]: >>>GPIO4_1<<<, [1]: Reserved, [2]: I2S0_SDI_B, [3]: + SPI1_SS3_A, [4]: QEC3_X_A, [5]: SD_CLK_D, [6]: CDC_HSYNC_B, [7]: CAM_D13_A */ + /* Selected: GPIO4_1 for "UTIMER_GPO0" */ + {PORT_4, PIN_1, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_2 on pin E3. Functions: [0]: >>>GPIO4_2<<<, [1]: Reserved, [2]: Reserved, [3]: + I2S0_SDO_B, [4]: SPI2_MISO_A, [5]: QEC3_Y_A, [6]: SD_CMD_D, [7]: CAM_D14_A */ + /* Selected: GPIO4_2 for "UTIMER_GPO1" */ + {PORT_4, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_3 on pin F3. Functions: [0]: >>>GPIO4_3<<<, [1]: Reserved, [2]: Reserved, [3]: + I2S0_SCLK_B, [4]: SPI2_MOSI_A, [5]: QEC3_Z_A, [6]: SD_RST_D, [7]: CAM_D15_A */ + /* Selected: GPIO4_3 for "UTIMER_GPO2" */ + {PORT_4, PIN_3, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P4_4 on pin G3. Functions: [0]: GPIO4_4, [1]: >>>JTAG_TCK<<<, [2]: I2S0_WS_B, [3]: + SPI2_SCLK_A, [4]: FAULT0_A */ + /* Selected: JTAG_TCK for "My JTAG" */ + {PORT_4, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_5 on pin H3. Functions: [0]: GPIO4_5, [1]: >>>JTAG_TMS<<<, [2]: SPI2_SS0_A, [3]: FAULT1_A + */ + /* Selected: JTAG_TMS for "My JTAG" */ + {PORT_4, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_6 on pin J3. Functions: [0]: GPIO4_6, [1]: >>>JTAG_TDI<<<, [2]: SPI2_SS1_A, [3]: FAULT2_A + */ + /* Selected: JTAG_TDI for "My JTAG" */ + {PORT_4, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P4_7 on pin K3. Functions: [0]: GPIO4_7, [1]: >>>JTAG_TDO<<<, [2]: SPI2_SS2_A, [3]: FAULT3_A + */ + /* Selected: JTAG_TDO for "My JTAG" */ + {PORT_4, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P5_0 on pin C4. Functions: [0]: GPIO5_0, [1]: OSPI1_RXDS_A, [2]: UART4_RX_C, [3]: PDM_D2_A, + [4]: SPI0_MISO_B, [5]: I2C2_SDA_B, [6]: UT0_T0_B, [7]: >>>SD_D0_A<<< */ + /* Selected: SD_D0_A for "SDCARD" */ + {PORT_5, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_1 on pin G8. Functions: [0]: GPIO5_1, [1]: OSPI1_SS0_A, [2]: UART4_TX_C, [3]: PDM_D3_A, + [4]: SPI0_MOSI_B, [5]: I2C2_SCL_B, [6]: UT0_T1_B, [7]: >>>SD_D1_A<<< */ + /* Selected: SD_D1_A for "SDCARD" */ + {PORT_5, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_2 on pin B5. Functions: [0]: GPIO5_2, [1]: OSPI1_SCLKN_A, [2]: UART5_RX_C, [3]: PDM_C3_A, + [4]: SPI0_SS0_B, [5]: LPI2C_SCL_B, [6]: UT1_T0_B, [7]: >>>SD_D2_A<<< */ + /* Selected: SD_D2_A for "SDCARD" */ + {PORT_5, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_3 on pin F7. Functions: [0]: GPIO5_3, [1]: OSPI1_SCLK_A, [2]: UART5_TX_C, [3]: + SPI0_SCLK_B, [4]: LPI2C_SDA_B, [5]: UT1_T1_B, [6]: >>>SD_D3_A<<<, [7]: CDC_PCLK_A */ + /* Selected: SD_D3_A for "SDCARD" */ + {PORT_5, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_4 on pin C6. Functions: [0]: GPIO5_4, [1]: OSPI1_SS1_A, [2]: UART3_CTS_A, [3]: + >>>PDM_D2_B<<<, [4]: SPI0_SS3_A, [5]: UT2_T0_B, [6]: SD_D4_A, [7]: CDC_DE_A */ + /* Selected: PDM_D2_B for "PDM MIC" */ + {PORT_5, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_5 on pin A6. Functions: [0]: GPIO5_5, [1]: >>>OSPI1_SCLK_C<<<, [2]: UART3_RTS_A, [3]: + PDM_D3_B, [4]: UT2_T1_B, [5]: SD_D5_A, [6]: ETH_RXD0_A, [7]: CDC_HSYNC_A */ + /* Selected: OSPI1_SCLK_C for "ISSI Flash" */ + {PORT_5, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P5_6 on pin D7. Functions: [0]: GPIO5_6, [1]: UART1_CTS_B, [2]: I2C2_SCL_C, [3]: + >>>UT3_T0_B<<<, [4]: SD_D6_A, [5]: ETH_RXD1_A, [6]: CDC_VSYNC_A */ + /* Selected: UT3_T0_B for "Clickboard PWM" */ + {PORT_5, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P5_7 on pin B7. Functions: [0]: GPIO5_7, [1]: >>>OSPI1_SS0_C<<<, [2]: UART1_RTS_B, [3]: + I2C2_SDA_C, [4]: UT3_T1_B, [5]: SD_D7_A, [6]: ETH_RST_A */ + /* Selected: OSPI1_SS0_C for "ISSI Flash" */ + {PORT_5, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P6_0 on pin E8. Functions: [0]: GPIO6_0, [1]: OSPI0_D0_C, [2]: UART4_DE_A, [3]: PDM_D0_C, + [4]: UT4_T0_B, [5]: SD_D0_D, [6]: >>>ETH_TXD0_A<<< [7]: LPSPI_SS1_A */ + /* Selected: ETH_TXD0_A for "RTL8201" */ + {PORT_6, PIN_0, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_1 on pin H9. Functions: [0]: >>>GPIO6_1<<<, [1]: OSPI0_D1_C, [2]: UART5_DE_A, [3]: + PDM_C0_C, [4]: UT4_T1_B, [5]: SD_D1_D, [6]: ETH_TXD1_A, [7]: LPSPI_SS2_A */ + /* Selected: GPIO6_1 for "LCD_BACKLIGHT" */ + {PORT_6, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_2 on pin C8. Functions: [0]: >>>GPIO6_2<<<, [1]: OSPI0_D2_C, [2]: UART2_CTS_A, [3]: + LPI3C_SDA_A, [4]: PDM_D1_C, [5]: UT5_T0_B, [6]: SD_D2_D, [7]: ETH_TXEN_A */ + /* Selected: GPIO6_2 for "LEDRGB1_R" */ + {PORT_6, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_3 on pin F9. Functions: [0]: >>>GPIO6_3<<<, [1]: OSPI0_D3_C, [2]: UART2_RTS_A, [3]: + LPI3C_SCL_A, [4]: PDM_C1_C, [5]: UT5_T1_B, [6]: SD_D3_D, [7]: ETH_IRQ_A */ + /* Selected: GPIO6_3 for "UTIMER_GPO3" */ + {PORT_6, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_4 on pin G10. Functions: [0]: >>>GPIO6_4<<<, [1]: OSPI0_D4_C, [2]: UART2_CTS_B, [3]: + LFRC_OUT_A, [4]: SPI1_SS0_B, [5]: UT6_T0_B, [6]: SD_D4_D, [7]: ETH_REFCLK_A */ + /* Selected: GPIO6_4 for "LEDRGB1_G" */ + {PORT_6, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_5 on pin E10. Functions: [0]: >>>GPIO6_5<<<, [1]: OSPI0_D5_C, [2]: UART2_RTS_B, [3]: + * LPI2C1_SDA_B, [4]: SPI1_SS1_B, [5]: UT6_T1_B, [6]: SD_D5_D, [7]: ETH_MDIO_A + */ + /* Selected: GPIO6_5 for "TOUCH_RESET" */ + {PORT_6, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_6 on pin C10. Functions: [0]: >>>GPIO6_6<<<, [1]: OSPI0_D6_C, [2]: UART0_CTS_B, [3]: + Reserved, [4]: SPI1_SS2_B, [5]: UT7_T0_B, [6]: SD_D6_D, [7]: ETH_MDC_A */ + /* Selected: GPIO6_6 for "LEDRGB1_B" */ + {PORT_6, PIN_6, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P6_7 on pin D11. Functions: [0]: GPIO6_7, [1]: OSPI0_D7_C, [2]: UART0_RTS_B, [3]: + >>>PDM_C2_A<<<, [4]: SPI1_SS3_B, [5]: UT7_T1_B, [6]: SD_D7_D, [7]: ETH_CRS_DV_A */ + /* Selected: PDM_C2_A for "PDM MIC" */ + {PORT_6, PIN_7, PINMUX_ALTERNATE_FUNCTION_3, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_0 on pin A12. Functions: [0]: GPIO7_0, [1]: Reserved, [2]: CMP3_OUT_A, [3]: SPI0_MISO_C, + [4]: I2C0_SDA_C, [5]: UT8_T0_B, [6]: >>>SD_CMD_A<<<, [7]: CAN_RXD_A */ + /* Selected: SD_CMD_A for "SDCARD" */ + {PORT_7, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_1 on pin C12. Functions: [0]: GPIO7_1, [1]: Reserved, [2]: CMP2_OUT_A, [3]: SPI0_MOSI_C, + [4]: I2C0_SCL_C, [5]: UT8_T1_B, [6]: >>>SD_CLK_A<<<, [7]: CAN_TXD_A */ + /* Selected: SD_CLK_A for "SDCARD" */ + {PORT_7, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_2 on pin K11. Functions: [0]: GPIO7_2, [1]: Reserved, [2]: UART3_CTS_B, [3]: CMP1_OUT_A, + [4]: SPI0_SCLK_C, [5]: >>>I2C1_SDA_C<<<, [6]: UT9_T0_B, [7]: SD_RST_A */ + /* Selected: I2C1_SDA_C for "Camera,GT911 Touchscreen,Master" */ + {PORT_7, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P7_3 on pin E12. Functions: [0]: GPIO7_3, [1]: Reserved, [2]: UART3_RTS_B, [3]: CMP0_OUT_A, + [4]: SPI0_SS0_C, [5]: >>>I2C1_SCL_C<<<, [6]: UT9_T1_B, [7]: CAN_STBY_A */ + /* Selected: I2C1_SCL_C for "Camera,GT911 Touchscreen,Master" */ + {PORT_7, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P7_4 on pin T1 {FLEX IO}. Functions: [0]: >>>GPIO7_4<<<, [1]: Reserved, [2]: LPUART_CTS_A, + [3]: LPPDM_C2_A, [4]: LPSPI_MISO_A, [5]: LPI2C_SCL_A, [6]: UT10_T0_B */ + /* Selected: GPIO7_4 for "LEDRGB0_G" */ + {PORT_7, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_5 on pin T2 {FLEX IO}. Functions: [0]: >>>GPIO7_5<<<, [1]: Reserved, [2]: LPUART_RTS_A, + [3]: LFXO_OUT_A, [4]: LPPDM_D2_A, [5]: LPSPI_MOSI_A, [6]: LPI2C_SDA_A, [7]: UT10_T1_B */ + /* Selected: GPIO7_5 for "CAMERA_POWER" */ + {PORT_7, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_6 on pin U3 {FLEX IO}. Functions: [0]: GPIO7_6, [1]: Reserved, [2]: LPUART_RX_A, [3]: + LPI3C_SDA_B, [4]: LPPDM_C3_A, [5]: LPSPI_SCLK_A, [6]: >>>I3C_SDA_D<<<, [7]: UT11_T0_B */ + /* Selected: I3C_SDA_D for "ICM42670 IMU,BMI323 IMU,pin header" */ + {PORT_7, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P7_7 on pin U1 {FLEX IO}. Functions: [0]: GPIO7_7, [1]: Reserved, [2]: LPUART_TX_A, [3]: + LPI3C_SCL_B, [4]: LPPDM_D3_A, [5]: LPSPI_SS_A, [6]: >>>I3C_SCL_D<<<, [7]: UT11_T1_B */ + /* Selected: I3C_SCL_D for "ICM42670 IMU,BMI323 IMU,pin header" */ + {PORT_7, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_0 on pin B13. Functions: [0]: GPIO8_0, [1]: >>>OSPI1_SCLKN_C<<<, [2]: AUDIO_CLK_A, [3]: + FAULT0_B, [4]: LPCAM_D0_A, [5]: SD_D0_C, [6]: CDC_D0_A, [7]: CAM_D0_B */ + /* Selected: OSPI1_SCLKN_C for "ISSI Flash" */ + {PORT_8, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P8_1 on pin D13. Functions: [0]: >>>GPIO8_1<<<, [1]: I2S2_SDI_A, [2]: FAULT1_B, [3]: + LPCAM_D1_A, [4]: SD_D1_C, [5]: CDC_D1_A, [6]: CAM_D1_B */ + /* Selected: GPIO8_1 for "CLICKBOARD_INT" */ + {PORT_8, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_3 on pin C14. Functions: [0]: >>>GPIO8_3<<<, [1]: I2S2_SCLK_A, [2]: SPI1_MISO_B, [3]: + FAULT3_B, [4]: LPCAM_D3_A, [5]: SD_D3_C, [6]: CDC_D3_A, [7]: CAM_D3_B */ + /* Selected: GPIO8_3 for "CLICKBOARD_RST" */ + {PORT_8, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_4 on pin G12. Functions: [0]: >>>GPIO8_4<<<, [1]: I2S2_WS_A, [2]: SPI1_MOSI_B, [3]: + QEC0_X_B, [4]: LPCAM_D4_A, [5]: SD_D4_C, [6]: CDC_D4_A, [7]: CAM_D4_B */ + /* Selected: GPIO8_4 for "ICM_IMU_IRQ" */ + {PORT_8, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_5 on pin G16. Functions: [0]: GPIO8_5, [1]: >>>HSPI0_RXDS1<<<, [2]: SPI1_SCLK_B, [3]: + QEC0_Y_B, [4]: LPCAM_D5_A, [5]: SD_D5_C, [6]: CDC_D5_A, [7]: CAM_D5_B */ + /* Selected: HSPI0_RXDS1 */ + {PORT_8, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P8_6 on pin H13. Functions: [0]: GPIO8_6, [1]: Reserved, [2]: >>>I2S3_SCLK_B<<<, [3]: + QEC0_Z_B, [4]: LPCAM_D6_A, [5]: SD_D6_C, [6]: CDC_D6_A, [7]: CAM_D6_B */ + /* Selected: I2S3_SCLK_B for "MIC Input" */ + {PORT_8, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_DRIVER_DISABLED_BUS_REPEATER | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P8_7 on pin G18. Functions: [0]: GPIO8_7, [1]: Reserved, [2]: >>>I2S3_WS_B<<<, [3]: QEC1_X_B, + [4]: LPCAM_D7_A, [5]: SD_D7_C, [6]: CDC_D7_A, [7]: CAM_D7_B */ + /* Selected: I2S3_WS_B for "MIC Input" */ + {PORT_8, PIN_7, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_0 on pin H15. Functions: [0]: GPIO9_0, [1]: Reserved, [2]: >>>I2S3_SDI_B<<<, [3]: QEC1_Y_B, + [4]: SD_CMD_C, [5]: CDC_D8_A, [6]: CAM_D8_B, [7]: LPSPI_SS3_A */ + /* Selected: I2S3_SDI_B for "MIC Input" */ + {PORT_9, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_BUS_REPEATER | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_1 on pin H17. Functions: [0]: >>>GPIO9_1<<<, [1]: LPUART_RX_B, [2]: I2S3_SDO_B, [3]: + QEC1_Z_B, [4]: SD_CLK_C, [5]: CDC_D9_A, [6]: CAM_D9_B, [7]: LPSPI_SS4_A */ + /* Selected: GPIO9_1 for "CAMERA_RESET" */ + {PORT_9, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_2 on pin J14. Functions: [0]: >>>GPIO9_2<<<, [1]: LPUART_TX_B, [2]: I2S3_SDI_A, [3]: + SPI2_MISO_B, [4]: QEC2_X_B, [5]: SD_RST_C, [6]: CDC_D10_A, [7]: CAM_D10_B */ + /* Selected: GPIO9_2 for "CAMERA_FLASH" */ + {PORT_9, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_3 on pin K13. Functions: [0]: >>>GPIO9_3<<<, [1]: Reserved, [2]: UART7_RX_B, [3]: + I2S3_SDO_A, [4]: SPI2_MOSI_B, [5]: QEC2_Y_B, [6]: CDC_D11_A, [7]: CAM_D11_B */ + /* Selected: GPIO9_3 for "CAMERA_TRIGGER" */ + {PORT_9, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_DOWN | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_4 on pin J18. Functions: [0]: >>>GPIO9_4<<<, [1]: UART7_TX_B, [2]: I2S3_SCLK_A, [3]: + SPI2_SCLK_B, [4]: I2C3_SDA_C, [5]: QEC2_Z_B, [6]: CDC_D12_A, [7]: CAM_D12_B */ + /* Selected: GPIO9_4 for "TOUCH_INT" */ + {PORT_9, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P9_5 on pin J16. Functions: [0]: GPIO9_5, [1]: >>>OSPI1_D0_C<<<, [2]: I2S3_WS_A, [3]: + SPI2_SS0_B, [4]: I2C3_SCL_C, [5]: QEC3_X_B, [6]: CDC_D13_A, [7]: CAM_D13_B */ + /* Selected: OSPI1_D0_C for "ISSI Flash" */ + {PORT_9, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P9_6 on pin K17. Functions: [0]: GPIO9_6, [1]: >>>OSPI1_D1_C<<<, [2]: AUDIO_CLK_B, [3]: + SPI2_SS1_B, [4]: I2C3_SDA_B, [5]: QEC3_Y_B, [6]: CDC_D14_A, [7]: CAM_D14_B */ + /* Selected: OSPI1_D1_C for "ISSI Flash" */ + {PORT_9, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P9_7 on pin L16. Functions: [0]: GPIO9_7, [1]: >>>OSPI1_D2_C<<<, [2]: UART7_DE_B, [3]: + SPI2_SS2_B, [4]: I2C3_SCL_B, [5]: QEC3_Z_B, [6]: CDC_D15_A, [7]: CAM_D15_B */ + /* Selected: OSPI1_D2_C for "ISSI Flash" */ + {PORT_9, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_0 on pin M13. Functions: [0]: GPIO10_0, [1]: >>>OSPI1_D3_C<<<, [2]: UART6_DE_B, [3]: + SPI2_SS3_B, [4]: UT0_T0_C, [5]: LPCAM_HSYNC_A, [6]: CDC_D16_A, [7]: CAM_HSYNC_B */ + /* Selected: OSPI1_D3_C for "ISSI Flash" */ + {PORT_10, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_1 on pin M15. Functions: [0]: GPIO10_1, [1]: >>>OSPI1_D4_C<<<, [2]: Reserved, [3]: + LPI2S_SDI_B, [4]: UT0_T1_C, [5]: LPCAM_VSYNC_A, [6]: CDC_D17_A, [7]: CAM_VSYNC_B */ + /* Selected: OSPI1_D4_C for "ISSI Flash" */ + {PORT_10, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_2 on pin N18. Functions: [0]: GPIO10_2, [1]: >>>OSPI1_D5_C<<<, [2]: Reserved, [3]: + LPI2S_SDO_B, [4]: UT1_T0_C, [5]: LPCAM_PCLK_A, [6]: CDC_D18_A, [7]: CAM_PCLK_B */ + /* Selected: OSPI1_D5_C for "ISSI Flash" */ + {PORT_10, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_3 on pin R15. Functions: [0]: GPIO10_3, [1]: >>>OSPI1_D6_C<<<, [2]: Reserved, [3]: + LPI2S_SCLK_B, [4]: UT1_T1_C, [5]: LPCAM_XVCLK_A, [6]: CDC_D19_A, [7]: CAM_XVCLK_B */ + /* Selected: OSPI1_D6_C for "ISSI Flash" */ + {PORT_10, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_4 on pin R16. Functions: [0]: GPIO10_4, [1]: >>>OSPI1_D7_C<<<, [2]: Reserved, [3]: + LPI2S_WS_B, [4]: I2C0_SDA_D, [5]: UT2_T0_C, [6]: ETH_TXD0_B, [7]: CDC_D20_A */ + /* Selected: OSPI1_D7_C for "ISSI Flash" */ + {PORT_10, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P10_5 on pin P14. Functions: [0]: GPIO10_5, [1]: UART6_RX_A, [2]: I2S2_SDI_B, [3]: + SPI3_MISO_B, [4]: I2C0_SCL_D, [5]: UT2_T1_C, [6]: >>>ETH_TXD1_B<<<, [7]: CDC_D21_A */ + /* Selected: ETH_TXD1_B for "RTL8201" */ + {PORT_10, PIN_5, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P10_6 on pin T15. Functions: [0]: GPIO10_6, [1]: UART6_TX_A, [2]: I2S2_SDO_B, [3]: + SPI3_MOSI_B, [4]: I2C1_SDA_D, [5]: UT3_T0_C, [6]: >>>ETH_TXEN_B<<<, [7]: CDC_D22_A */ + /* Selected: ETH_TXEN_B for "RTL8201" */ + {PORT_10, PIN_6, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P10_7 on pin T17. Functions: [0]: GPIO10_7, [1]: UART7_RX_A, [2]: I2S2_SCLK_B, [3]: + SPI3_SCLK_B, [4]: I2C1_SCL_D, [5]: UT3_T1_C, [6]: CDC_D23_A, [7]: >>>OSPI1_RXDS_C<<< */ + /* Selected: OSPI1_RXDS_C for "ISSI Flash" */ + {PORT_10, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_7, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P11_0 on pin P13. Functions: [0]: GPIO11_0, [1]: OSPI1_D0_A, [2]: UART7_TX_A, [3]: I2S2_WS_B, + [4]: SPI3_SS0_B, [5]: UT4_T0_C, [6]: >>>ETH_REFCLK_B<<<, [7]: CDC_D0_B */ + /* Selected: ETH_REFCLK_B for "RTL8201" */ + {PORT_11, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_1 on pin U18. Functions: [0]: GPIO11_1, [1]: OSPI1_D1_A, [2]: UART7_DE_A, [3]: SPI3_SS1_B, + [4]: UT4_T1_C, [5]: >>>ETH_MDIO_B<<<, [6]: CDC_D1_B, [7]: LPSPI_SS5_A */ + /* Selected: ETH_MDIO_B for "RTL8201" */ + {PORT_11, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_5, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_2 on pin N12. Functions: [0]: GPIO11_2, [1]: OSPI1_D2_A, [2]: UART6_DE_A, [3]: LPPDM_C2_B, + [4]: SPI3_SS2_B, [5]: UT5_T0_C, [6]: >>>ETH_MDC_B<<<, [7]: CDC_D2_B */ + /* Selected: ETH_MDC_B for "RTL8201" */ + {PORT_11, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_3 on pin M11. Functions: [0]: GPIO11_3, [1]: OSPI1_D3_A, [2]: UART5_RX_B, [3]: LPPDM_C3_B, + [4]: SPI3_SS3_B, [5]: UT5_T1_C, [6]: >>>ETH_RXD0_B<<<, [7]: CDC_D3_B */ + /* Selected: ETH_RXD0_B for "RTL8201" */ + {PORT_11, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_4 on pin Y13. Functions: [0]: GPIO11_4, [1]: OSPI1_D4_A, [2]: UART5_TX_B, [3]: PDM_C2_B, + [4]: LPSPI_MISO_B, [5]: UT6_T0_C, [6]: >>>ETH_RXD1_B<<<, [7]: CDC_D4_B */ + /* Selected: ETH_RXD1_B for "RTL8201" */ + {PORT_11, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_5 on pin AD17. Functions: [0]: GPIO11_5, [1]: OSPI1_D5_A, [2]: UART6_RX_B, [3]: PDM_C3_B, + [4]: LPSPI_MOSI_B, [5]: UT6_T1_C, [6]: >>>ETH_CRS_DV_B<<<, [7]: CDC_D5_B */ + /* Selected: ETH_CRS_DV_B for "RTL8201" */ + {PORT_11, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_6 on pin AA14. Functions: [0]: GPIO11_6, [1]: OSPI1_D6_A, [2]: UART6_TX_B, [3]: LPPDM_D2_B, + [4]: LPSPI_SCLK_B, [5]: UT7_T0_C, [6]: >>>ETH_RST_B<<<, [7]: CDC_D6_B */ + /* Selected: ETH_RST_B for "RTL8201" */ + {PORT_11, PIN_6, PINMUX_ALTERNATE_FUNCTION_6, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P11_7 on pin AC16. Functions: [0]: GPIO11_7, [1]: OSPI1_D7_A, [2]: UART5_DE_B, [3]: LPPDM_D3_B, + [4]: LPSPI_SS_B, [5]: UT7_T1_C, [6]: >>>ETH_IRQ_B<<<, [7]: CDC_D7_B */ + /* Selected: ETH_IRQ_B for "RTL8201" */ + {PORT_11, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_6, + PADCTRL_READ_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_0 on pin E2. Functions: [0]: >>>GPIO12_0<<<, [1]: OSPI0_SCLK_C, [2]: AUDIO_CLK_C, [3]: + I2S1_SDI_B, [4]: UT8_T0_C, [5]: CDC_D8_B, [7]: LPUT0_T0_B */ + /* Selected: GPIO12_0 for "LEDRGB0_B" */ + {PORT_12, PIN_0, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_1 on pin D1. Functions: [0]: GPIO12_1, [1]: OSPI0_SCLKN_C, [2]: >>>UART4_RX_B<<<, [3]: + I2S1_SDO_B, [4]: UT8_T1_C, [5]: CDC_D9_B, [7]: LPUT0_T1_B */ + /* Selected: UART4_RX_B for "UARTB" */ + {PORT_12, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_2 on pin K5. Functions: [0]: GPIO12_2, [1]: OSPI0_RXDS_C, [2]: >>>UART4_TX_B<<<, [3]: + I2S1_SCLK_B, [4]: UT9_T0_C, [5]: CDC_D10_B */ + /* Selected: UART4_TX_B for "UARTB" */ + {PORT_12, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_3 on pin J6. Functions: [0]: >>>GPIO12_3<<<, [1]: OSPI0_SS0_C, [2]: UART4_DE_B, [3]: + I2S1_WS_B, [4]: UT9_T1_C, [5]: CDC_D11_B */ + /* Selected: GPIO12_3 for "LEDRGB0_R" */ + {PORT_12, PIN_3, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_4 on pin A10. Functions: [0]: GPIO12_4, [1]: OSPI0_SS1_C, [2]: SPI3_MISO_A, [3]: + UT10_T0_C, [4]: >>>CAN_RXD_C<<<, [5]: CDC_D12_B */ + /* Selected: CAN_RXD_C for "CAN Transceiver" */ + {PORT_12, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_READ_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_5 on pin J10. Functions: [0]: GPIO12_5, [1]: Reserved, [2]: SPI3_MOSI_A, [3]: UT10_T1_C, + [4]: >>>CAN_TXD_C<<<, [5]: CDC_D13_B */ + /* Selected: CAN_TXD_C for "CAN Transceiver" */ + {PORT_12, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P12_6 on pin H11. Functions: [0]: GPIO12_6, [1]: Reserved, [2]: SPI3_SCLK_A, [3]: UT11_T0_C, + [4]: >>>CAN_STBY_C<<<, [5]: CDC_D14_B */ + /* Selected: CAN_STBY_C for "CAN Transceiver" */ + {PORT_12, PIN_6, PINMUX_ALTERNATE_FUNCTION_4, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_0 on pin H3. Functions: [0]: GPIO13_0, [1]: OSPI1_D0_B, [2]: Reserved, [3]: SPI3_SS1_A, + [4]: >>>QEC0_X_C<<<, [5]: SD_D0_B, [6]: CDC_D16_B */ + /* Selected: QEC0_X_C for "Encoder" */ + {PORT_13, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_4, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_1 on pin G2. Functions: [0]: GPIO13_1, [1]: OSPI1_D1_B, [2]: SPI3_SS2_A, [3]: + >>>QEC0_Y_C<<<, [4]: SD_D1_B, [5]: CDC_D17_B */ + /* Selected: QEC0_Y_C for "Encoder" */ + {PORT_13, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_2 on pin F1. Functions: [0]: GPIO13_2, [1]: OSPI1_D2_B, [2]: SPI3_SS3_A, [3]: + >>>QEC0_Z_C<<<, [4]: SD_D2_B, [5]: CDC_D18_B */ + /* Selected: QEC0_Z_C for "Encoder" */ + {PORT_13, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_3, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_4 on pin G4. Functions: [0]: >>>GPIO13_4<<<, [1]: OSPI1_D4_B, [2]: LPI2S_SDI_C, [3]: + QEC1_Y_C, [4]: SD_D4_B, [5]: CDC_D20_B */ + /* Selected: GPIO13_4 */ + {PORT_13, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_5 on pin D5. Functions: [0]: >>>GPIO13_5<<<, [1]: OSPI1_D5_B, [2]: LPI2S_SDO_C, [3]: + QEC1_Z_C, [4]: SD_D5_B, [5]: CDC_D21_B */ + /* Selected: GPIO13_5 */ + {PORT_13, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_6 on pin E6. Functions: [0]: >>>GPIO13_6<<<, [1]: OSPI1_D6_B, [2]: LPI2S_SCLK_C, [3]: + QEC2_X_C, [4]: SD_D6_B, [5]: CDC_D22_B */ + /* Selected: GPIO13_6 */ + {PORT_13, PIN_6, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P13_7 on pin A4. Functions: [0]: >>>GPIO13_7<<<, [1]: OSPI1_D7_B, [2]: LPI2S_WS_C, [3]: + QEC2_Y_C, [4]: SD_D7_B, [5]: CDC_D23_B */ + /* Selected: GPIO13_7 */ + {PORT_13, PIN_7, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_0 on pin B11. Functions: [0]: GPIO14_0 [1]: OSPI1_SCLK_B, [2]: >>>UART6_RX_C<<<,, [3]: + QEC2_Z_C, [4]: SD_CMD_B, [5]: LFRC_OUT_B */ + /* Selected: UART6_RX_C */ + {PORT_14, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_2, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP}, + + /* P14_1 on pin G14. Functions: [0]: GPIO14_1 [1]: OSPI1_SCLKN_B, [2]: >>>UART6_TX_C<<<,, [3]: + Reserved, [4]: QEC3_X_C, [5]: SD_CLK_B, [6]: LFXO_OUT_B */ + /* Selected: UART6_TX_C */ + {PORT_14, PIN_1, PINMUX_ALTERNATE_FUNCTION_2, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_2 on pin F15. Functions: [0]: >>>GPIO14_2<<<, [1]: OSPI1_SS0_B, [2]: UART7_RX_C, [3]: + LPI3C_SDA_C, [4]: QEC3_Y_C, [5]: SD_RST_B */ + /* Selected: GPIO14_2 for "QEC_Z_GPO" */ + {PORT_14, PIN_2, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_4 on pin W12. Functions: [0]: >>>GPIO14_4<<<, [1]: CMP3_OUT_B, [2]: SPI1_MISO_C, [3]: + FAULT0_C */ + /* Selected: GPIO14_4 */ + {PORT_14, PIN_4, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_5 on pin V11. Functions: [0]: >>>CGPIO14_5<<<, [1]: CMP2_OUT_B, [2]: SPI1_MOSI_C, [3]: + FAULT1_C */ + /* Selected: GPIO14_5 */ + {PORT_14, PIN_5, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_6 on pin Y11. Functions: [0]: >>>GPIO14_6<<<, [1]: CMP1_OUT_B, [2]: SPI1_SCLK_C, [3]: + FAULT2_C */ + /* Selected: GPIO14_6 */ + {PORT_14, PIN_6, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P14_7 on pin AD15. Functions: [0]: >>>GPIO14_7<<<, [1]: CMP0_OUT_B, [2]: SPI1_SS0_C, [3]: + FAULT3_C */ + /* Selected: GPIO14_7 */ + {PORT_14, PIN_7, PINMUX_ALTERNATE_FUNCTION_0, PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_0 on pin V2 {FLEX IO}. Functions: [0]: >>>GPIOV_0<<<, [1]: LPTMR0_CLK_IO. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_0 for "JOY_SW_A" */ + {PORT_15, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_1 on pin W2 {FLEX IO}. Functions: [0]: >>>GPIOV_1<<<, [1]: LPTMR1_CLK_OUT. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_1 for "JOY_SW_B" */ + {PORT_15, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_2 on pin U2 {FLEX IO}. Functions: [0]: >>>GPIOV_2<<<, [1]: LPTMR2_CLK_IO. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_2 for "JOY_SW_C" */ + {PORT_15, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_3 on pin V1 {FLEX IO}. Functions: [0]: >>>GPIOV_3<<<, [1]: LPTMR3_CLK_OUT. Note that + LPGPIO_CTRL_n register has a different layout! */ + /* Selected: GPIOV_3 for "JOY_SW_D" */ + {PORT_15, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_4 on pin T11. Functions: [0]: >>>GPIOV_4<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_4 for "JOY_SW_CENTER" */ + {PORT_15, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_READ_ENABLE | PADCTRL_SCHMITT_TRIGGER_ENABLE | PADCTRL_DRIVER_DISABLED_PULL_UP | + PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_5 on pin V13. Functions: [0]: >>>GPIOV_5<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_5 for "BT_HWAKE" */ + {PORT_15, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_6 on pin AC18. Functions: [0]: >>>GPIOV_6<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_6 for "WIFI_HWAKE" */ + {PORT_15, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P15_7 on pin W14. Functions: [0]: >>>GPIOV_7<<<. Note that LPGPIO_CTRL_n register has a + different layout! */ + /* Selected: GPIOV_7 for "HSPI1_RESETn" */ + {PORT_15, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_0, + PADCTRL_DRIVER_DISABLED_PULL_UP | PADCTRL_OUTPUT_DRIVE_STRENGTH_4MA}, + + /* P16_0 Functions: [0]: GPIO16_0, [1]: >>>HSPI0_D8<<< */ + /* Selected: HSPI0_D8 */ + {PORT_16, PIN_0, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_1 Functions: [0]: GPIO16_1, [1]: >>>HSPI0_D9<<< */ + /* Selected: HSPI0_D9 */ + {PORT_16, PIN_1, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_2 Functions: [0]: GPIO16_2, [1]: >>>HSPI0_D10<<< */ + /* Selected: HSPI0_D10 */ + {PORT_16, PIN_2, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_3 Functions: [0]: GPIO16_3, [1]: >>>HSPI0_D11<<< */ + /* Selected: HSPI0_D11 */ + {PORT_16, PIN_3, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_4 Functions: [0]: GPIO16_4, [1]: >>>HSPI0_D12<<< */ + /* Selected: HSPI0_D12 */ + {PORT_16, PIN_4, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_5 Functions: [0]: GPIO16_5, [1]: >>>HSPI0_D13<<< */ + /* Selected: HSPI0_D13 */ + {PORT_16, PIN_5, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_6 Functions: [0]: GPIO16_6, [1]: >>>HSPI0_D14<<< */ + /* Selected: HSPI0_D14 */ + {PORT_16, PIN_6, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P16_7 Functions: [0]: GPIO16_7, [1]: >>>HSPI0_D15<<< */ + /* Selected: HSPI0_D15 */ + {PORT_16, PIN_7, PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_0 Functions: [0]: GPIO17_0, [1]: >>>HSPI1_D8<<< */ + /* Selected: HSPI1_D8 */ + {PORT_17, + PIN_0, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_1 Functions: [0]: GPIO17_1, [1]: >>>HSPI1_D9<<< */ + /* Selected: HSPI1_D9 */ + {PORT_17, + PIN_1, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_2 Functions: [0]: GPIO17_2, [1]: >>>HSPI1_D10<<< */ + /* Selected: HSPI1_D10 */ + {PORT_17, + PIN_2, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_3 Functions: [0]: GPIO17_3, [1]: >>>HSPI1_D11<<< */ + /* Selected: HSPI1_D11 */ + {PORT_17, + PIN_3, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_4 Functions: [0]: GPIO17_4, [1]: >>>HSPI1_D12<<< */ + /* Selected: HSPI1_D12 */ + {PORT_17, + PIN_4, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_5 Functions: [0]: GPIO17_5, [1]: >>>HSPI1_D13<<< */ + /* Selected: HSPI1_D13 */ + {PORT_17, + PIN_5, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_6 Functions: [0]: GPIO17_6, [1]: >>>HSPI1_D14<<< */ + /* Selected: HSPI1_D14 */ + {PORT_17, + PIN_6, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, + + /* P17_7 Functions: [0]: GPIO17_7, [1]: >>>HSPI1_D15<<< */ + /* Selected: HSPI1_D15 */ + {PORT_17, + PIN_7, + PINMUX_ALTERNATE_FUNCTION_1, + PADCTRL_READ_ENABLE | PADCTRL_SLEW_RATE_FAST | PADCTRL_OUTPUT_DRIVE_STRENGTH_12MA}, +}; + +#endif /* __PINS_H__ */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h new file mode 100644 index 00000000..0ee8e2ab --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h @@ -0,0 +1,10854 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] +// Configuration settings for Driver_MRAM in component ::Drivers:MRAM +#define RTE_MRAM 1 +// MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] + +// CPI (Camera) [Driver_CPI] +// Configuration settings for Driver_CPI in component ::Drivers:CPI +#define RTE_CPI 1 +#if RTE_CPI + +// CPI interrupt priority <0-255> +// Defines CPI interrupt priority. +// Default: 0 +#define RTE_CPI_IRQ_PRI 0 + +// CPI CSI halt enable/disable +// <0=> disable +// <1=> enable +// Defines CPI CSI halt enable/disable. +// Default: 0 +#define RTE_CPI_CSI_HALT 0 + +// Select CPI AXI port +// <0=> disable +// <1=> enable +// Defines CPI AXI port +// Default: AXI port enable +#define RTE_CPI_AXI_PORT 1 + +// Select CPI ISP port +// <0=> disable +// <1=> enable +// Defines CPI ISP port +// Default: ISP port disable +#define RTE_CPI_ISP_PORT 1 + +// CPI Row roundup +// <0=> disable +// <1=> enable +// Defines CPI row roundup to 64 bit. +// Default: 0 +#define RTE_CPI_ROW_ROUNDUP 0 + +// CPI FIFO read watermark +// Defines FIFO read watermark. +// Default: 0x8 +#define RTE_CPI_FIFO_READ_WATERMARK 0x8 + +// CPI FIFO write watermark +// Defines CPI FIFO write watermark. +// Default: 0x18 +#define RTE_CPI_FIFO_WRITE_WATERMARK 0x18 + +// CPI horizontal back porch +// Defines CPI horizontal back porch. +// Default: 0x0 +#define RTE_CPI_HBP 0 + +// CPI horizontal front porch +// Defines CPI horizontal front porch. +// Default: 0x0 +#define RTE_CPI_HFP 0 + +// CPI horizontal cropping +// <0=> disable +// <1=> enable +// Defines CPI horizontal cropping +// Default: 0x1 +#define RTE_CPI_HFP_EN 0 + +// CPI vertical back porch +// Defines CPI vertical back porch. +// Default: 0x0 +#define RTE_CPI_VBP 0 + +// CPI vertical front porch +// Defines CPI vertical front porch. +// Default: 0x0 +#define RTE_CPI_VFP 0 + +// CPI vertical cropping +// <0=> disable +// <1=> enable +// Defines CPI vertical cropping +// Default: 0x1 +#define RTE_CPI_VFP_EN 0 + +// CPI number of active framebuffers +// Defines CPI number of active framebuffers +// Default: 2 +#define RTE_CPI_NUM_ACTIVE_FRAMEBUFFERS 0 + +// Enable CPI streaming +// <0=> Disable +// <1=> Enable +// Default: 1 +#define RTE_CPI_STREAMING_ENABLE 0 + +// MT9M114 [Driver_MT9M114] +// Enable/Disable MT9M114 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 camera sensor +// default: disable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE 0 + +#if (RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE) + +// Select camera MT9M114 pixel clock polarity +// <0=> not invert camera pixclk +// <1=> invert camera pixclk +// Defines camera MT9M114 pixel clock polarity +// Default: not invert camera pixclk +#define RTE_MT9M114_CAMERA_SENSOR_CPI_PIXEL_CLK_POL 0 + +// Select camera MT9M114 HSYNC polarity +// <0=> not invert HSYNC input +// <1=> invert HSYNC input +// Defines camera MT9M114 HSYNC polarity +// Default: not invert HSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_CPI_HSYNC_POL 0 + +// Select camera MT9M114 VSYNC polarity +// <0=> not invert VSYNC input +// <1=> invert VSYNC input +// Defines camera MT9M114 VSYNC polarity +// Default: not invert VSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_POL 0 + +// Select camera MT9M114 VSYNC wait +// <0=> vsync wait disable +// <1=> vsync wait enable +// Defines camera MT9M114 VSYNC wait +// Default: vsync wait disable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_WAIT 0 + +// Select camera MT9M114 VSYNC mode +// <0=> sync enable +// <1=> data enable +// Defines camera MT9M114 VSYNC mode +// Default: sync enable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_MODE 0 + +// Select video data mode +// <0=> 1 bit +// <1=> 2 bit +// <2=> 4 bit +// <3=> 8 bit +// <4=> 16 bit +// Defines video data mode +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MODE 3 + +// Select Data Endianness +// <0=> LSB First +// <1=> MSB First +// Select MSB/LSB +// Default: LSB +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_ENDIANNESS 0 + +// Select CODE10ON8 +// <0=> Disable +// <1=> Enable +// Defines transfer 10-bit coding over 8-bit data bus. +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_CODE10ON8 0 + +// Select camera MT9M114 data mask +// <0=> 16 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit +// Defines camera MT9M114 data mask +// Default: 10 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MASK 1 + +// select MT9M114 frame height +// defines select MT9M114 frame height. +// default: 480 +#define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_HEIGHT 480 + +// select MT9M114 frame width +// defines select MT9M114 frame width. +// default: 640 +#define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_WIDTH 640 + +#endif +// MT9M114 [Driver_MT9M114] + +#endif +// CPI (Camera) [Driver_CPI] + +// LPCPI (Camera) [Driver_LPCPI] +// Configuration settings for Driver_LPCPI in component ::Drivers:LPCPI +#define RTE_LPCPI 0 +#if RTE_LPCPI + +// LPCPI interrupt priority <0-255> +// Defines LPCPI interrupt priority. +// Default: 0 +#define RTE_LPCPI_IRQ_PRI 0 + +// Select LPCPI AXI port +// <0=> disable +// <1=> enable +// Defines LPCPI AXI port +// Default: AXI port enable +#define RTE_LPCPI_AXI_PORT 1 + +// Select LPCPI ISP port +// <0=> disable +// <1=> enable +// Defines LPCPI ISP port +// Default: ISP port disable +#define RTE_LPCPI_ISP_PORT 0 + +// LPCPI Row roundup +// <0=> disable +// <1=> enable +// Defines LPCPI row roundup to 64 bit. +// Default: 0 +#define RTE_LPCPI_ROW_ROUNDUP 0 + +// LPCPI FIFO read watermark +// Defines LPCPI FIFO read watermark. +// Default: 0x8 +#define RTE_LPCPI_FIFO_READ_WATERMARK 0x8 + +// LPCPI FIFO write watermark +// Defines LPCPI FIFO write watermark. +// Default: 0x18 +#define RTE_LPCPI_FIFO_WRITE_WATERMARK 0x18 + +// LPCPI horizontal back porch +// Defines LPCPI horizontal back porch. +// Default: 0x0 +#define RTE_LPCPI_HBP 0 + +// LPCPI horizontal front porch +// Defines LPCPI horizontal front porch. +// Default: 0x0 +#define RTE_LPCPI_HFP 0 + +// LPCPI horizontal cropping +// <0=> disable +// <1=> enable +// Defines LPCPI horizontal cropping +// Default: 0x1 +#define RTE_LPCPI_HFP_EN 0 + +// LPCPI vertical back porch +// Defines LPCPI vertical back porch. +// Default: 0x0 +#define RTE_LPCPI_VBP 0 + +// LPCPI vertical front porch +// Defines LPCPI vertical front porch. +// Default: 0x0 +#define RTE_LPCPI_VFP 0 + +// LPCPI vertical cropping +// <0=> disable +// <1=> enable +// Defines LPCPI vertical cropping +// Default: 0x1 +#define RTE_LPCPI_VFP_EN 0 + +// MT9M114 [Driver_MT9M114] +// Enable/Disable MT9M114 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 camera sensor +// default: disable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE 1 + +#if (RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE) + +// Select camera MT9M114 pixel clock polarity +// <0=> not invert camera pixclk +// <1=> invert camera pixclk +// Defines camera MT9M114 pixel clock polarity +// Default: not invert camera pixclk +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_PIXEL_CLK_POL 0 + +// Select camera MT9M114 HSYNC polarity +// <0=> not invert HSYNC input +// <1=> invert HSYNC input +// Defines camera MT9M114 HSYNC polarity +// Default: not invert HSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_HSYNC_POL 0 + +// Select camera MT9M114 VSYNC polarity +// <0=> not invert VSYNC input +// <1=> invert VSYNC input +// Defines camera MT9M114 VSYNC polarity +// Default: not invert VSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_POL 0 + +// Select camera MT9M114 VSYNC wait +// <0=> vsync wait disable +// <1=> vsync wait enable +// Defines camera MT9M114 VSYNC wait +// Default: vsync wait disable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_WAIT 0 + +// Select camera MT9M114 VSYNC mode +// <0=> sync enable +// <1=> data enable +// Defines camera MT9M114 VSYNC mode +// Default: sync enable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_MODE 0 + +// Select video data mode +// <0=> 1 bit +// <1=> 2 bit +// <2=> 4 bit +// <3=> 8 bit +// Defines video data mode +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_MODE 3 + +// Select Data Endianness +// <0=> LSB First +// <1=> MSB First +// Select MSB/LSB +// Default: LSB +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_ENDIANNESS 0 + +// Select CODE10ON8 +// <0=> Disable +// <1=> Enable +// Defines transfer 10-bit coding over 8-bit data bus. +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_CODE10ON8 0 + +// select MT9M114 frame height +// defines select MT9M114 frame height. +// default: 480 +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_HEIGHT 480 + +// select MT9M114 frame width +// defines select MT9M114 frame width. +// default: 640 +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_WIDTH 640 + +#endif +// MT9M114 [Driver_MT9M114] + +#endif +// LPCPI (Camera) [Driver_LPCPI] + +// ISP (ISP) [Driver_ISP] +// Configuration settings for Driver_ISP in component ::Drivers:ISP +#define RTE_ISP 0 +#if RTE_ISP + +// ISP IRQ priority <0-255> +// Defines Interrupt priority for ISP. +// Default: 0 +#define RTE_ISP_IRQ_PRIORITY 0 + +// ISP Enable AE Module +// <0=> disable +// <1=> enable +// defines if AE Module is enabled or not +// default: false +#define RTE_ISP_AE_MODULE 1 + +// ISP Enable BLS Module +// <0=> disable +// <1=> enable +// defines if Black Level Subtraction Module is enabled or not +// default: false +#define RTE_ISP_BLS_MODULE 1 + +// ISP Enable DMSC Module +// <0=> disable +// <1=> enable +// defines if Demosaic Module is enabled or not +// default: false +#define RTE_ISP_DMSC_MODULE 1 + +// ISP Enable FLT Module +// <0=> disable +// <1=> enable +// defines if Noise/Sharpening-Filter Module is enabled or not +// default: false +#define RTE_ISP_FLT_MODULE 1 + +// ISP Enable CCM Module +// <0=> disable +// <1=> enable +// defines if Color Correction Matrix Module is enabled or not +// default: false +#define RTE_ISP_CCM_MODULE 1 + +// ISP Enable CSM Module +// <0=> disable +// <1=> enable +// defines if Color Space Conversion Module is enabled or not +// default: false +#define RTE_ISP_CSM_MODULE 1 + +// ISP Enable WB Module +// <0=> disable +// <1=> enable +// defines if White Balancing Module is enabled or not +// default: false +#define RTE_ISP_WB_MODULE 1 + +// ISP Enable EXPM Module +// <0=> disable +// <1=> enable +// defines if Auto-Exposure Statistics Module is enabled or not +// default: false +#define RTE_ISP_EXPM_MODULE 1 + +// ISP Enable Gamma-out Module +// <0=> disable +// <1=> enable +// defines if Gamma-out Module is enabled or not +// default: false +#define RTE_ISP_GAMMAOUT_MODULE 1 + +// ISP Enable WBM Module +// <0=> disable +// <1=> enable +// defines if White-Balancing Statistics Module is enabled or not +// default: false +#define RTE_ISP_WBM_MODULE 1 + +// ISP Enable Binning Module +// <0=> disable +// <1=> enable +// defines if Binning Module is enabled or not +// default: false +#define RTE_ISP_BINNING_MODULE 1 + +// ISP Enable Scaling Module +// <0=> disable +// <1=> enable +// defines if scaling Module is enabled or not +// default: true +#define RTE_ISP_SCALAR_MODULE 1 + +// ISP log level +// <0=> NONE +// <1 => Logs all fatal errors. +// <2=> Logs all warnings. +// <3=> Logs all informational messages. +// <4=> Logs all debug messages. +// <5=> Log level verbose +// Defines ISP logging level +#define RTE_ISP_LOG_LEVEL 5 + +// ISP Buffer Count <2-8> +// Number of video buffers for ISP +#define RTE_ISP_BUFFER_COUNT 1 + +// ISP Output Format +// <20=> RAW8 (8-bit raw) +// <21=> RAW10 (10-bit raw) +// <22=> RAW12 (12-bit raw) +// <23=> NV12 (YUV420 semi-planar) +// <25=> NV16 (YUV422 semi-planar) +// <30=> YUV422P (YUV422 planar) +// <31=> YUV420P (YUV420 planar) +// <32=> YUYV (YUV422 packed) +// <37=> YUV400 (Grayscale) +// <38=> RGB888 (RGB interleaved) +// <39=> RGB888P (RGB planar) +// <40=> RAW420SP (RAW420 semi-planar) +// <41=> RAW422SP (RAW422 semi-planar) +// Defines ISP output pixel format for memory dump +// Default: RGB888 +#define RTE_ISP_OUTPUT_FORMAT 32 + +// ISP Scaler Output Width +// Width in pixels of the ISP scaler output (after scaling from sensor dimensions). +#define RTE_ISP_OUTPUT_WIDTH 480 + +// ISP Scaler Output Height +// Height in pixels of the ISP scaler output (after scaling from sensor dimensions). +#define RTE_ISP_OUTPUT_HEIGHT 480 + +// ISP Sensor Input Width +// Width in pixels of the sensor input to the ISP pipeline. +// Default: MT9M114 sensor resolution (1280). Change for different sensors. +#define RTE_ISP_SENSOR_INPUT_WIDTH RTE_MT9M114_CAMERA_SENSOR_FRAME_WIDTH + +// ISP Sensor Input Height +// Height in pixels of the sensor input to the ISP pipeline. +// Default: MT9M114 sensor resolution (720). Change for different sensors. +#define RTE_ISP_SENSOR_INPUT_HEIGHT RTE_MT9M114_CAMERA_SENSOR_FRAME_HEIGHT + +// ISP Crop Top offset <0-4095> +// Top offset in pixels for the cropped output window +#define RTE_ISP_CROP_TOP 0 + +// ISP Crop Left offset <0-4095> +// Left offset in pixels for the cropped output window +#define RTE_ISP_CROP_LEFT 0 + +// ISP Crop Width <1-4095> +// Width in pixels of the cropped output window. +// Default: full sensor input (no crop). Override with smaller value to crop. +#define RTE_ISP_CROP_WIDTH RTE_ISP_SENSOR_INPUT_WIDTH + +// ISP Crop Height <1-4095> +// Height in pixels of the cropped output window. +// Default: full sensor input (no crop). Override with smaller value to crop. +#define RTE_ISP_CROP_HEIGHT RTE_ISP_SENSOR_INPUT_HEIGHT + +#endif +// ISP (ISP) [Driver_ISP] + +// MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] +// Configuration settings for Driver_MIPI_CSI2 in component ::Drivers:MIPI_CSI2 +#define RTE_MIPI_CSI2 1 +#if RTE_MIPI_CSI2 + +// Select CSI2 DPHY backend +// <0=> CSI2 RX DPHY +// <1=> DSI TX DPHY used as RX +// Selects which DPHY hardware is used by Driver_MIPI_CSI2. +// Default: CSI2 RX DPHY +#define RTE_MIPI_CSI2_DPHY_BACKEND 0 + +// CSI pixel clock select +// <0=> Select AXI clock source +// <1=> Select PLL clock source +// Defines CSI pixel clock select +// Default: Select AXI clock source +#define RTE_CSI2_PIX_CLK_SEL 0 + +// select IPI mode +// <0=> camera mode +// <1=> controller mode +// defines select IPI mode +// default: camera mode +#define RTE_MIPI_CSI2_IPI_MODE 0 + +// select memory flush +// <0=> manual +// <1=> auto +// defines select memory flush +// default: auto +#define RTE_MIPI_CSI2_MEMFLUSH 1 + +// select sync event mode +// <0=> not trigger by frame start +// <1=> trigger by frame start +// defines select sync event mode +// default : not trigger by frame start +#define RTE_MIPI_CSI2_SYNC_ET_MODE 0 + +// select sync event select +// <0=> auto +// <1=> programmed +// defines select sync event select +// default : programmed +#define RTE_MIPI_CSI2_SYNC_ET_SEL 1 + +// embedded packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use embedded packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_EMBEDDED 0 + +// blanking packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use blanking packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_BLANKING 0 + +// null packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use null packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_NULL 0 + +// line start packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use line start packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_LINE_START 0 + +// video packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use video packets for IPI synchronization events +// default: enable +#define RTE_MIPI_CSI2_EN_VIDEO 1 + +// datatype to overwrite +// select CSI2 Data type to overwrite +// <24=> YUV420_8 +// <25=> YUV420_10 +// <26=> YUV420_8_LEGACY +// <28=> YUV420_8_SHIFT +// <29=> YUV420_10_SHIFT +// <30=> YUV422_8 +// <31=> YUV422_10 +// <32=> RGB444 +// <33=> RGB555 +// <34=> RGB565 +// <35=> RGB666 +// <36=> RGB888 +// <40=> RAW6 +// <41=> RAW7 +// <42=> RAW8 +// <43=> RAW10 +// <44=> RAW12 +// <45=> RAW14 +// <46=> RAW16 +// <48=> USER_DEFINED_1 +// <49=> USER_DEFINED_2 +// <50=> USER_DEFINED_3 +// <51=> USER_DEFINED_4 +// <52=> USER_DEFINED_5 +// <53=> USER_DEFINED_6 +// <54=> USER_DEFINED_7 +// <55=> USER_DEFINED_8 +// defines select CSI2 Data type to be overwrite +// default: RAW10 +#define RTE_MIPI_CSI2_EN_DT 43 + +// datatype to overwrite with programmed datatype +// define if want to use programmed datatype ignoring datatype of the header +// default: 0 +#define RTE_MIPI_CSI2_EN_DT_OVERWRITE 0 + +// Horizontal Synchronism Active Time range <0-2047> +// Defines possible range for selecting horizontal sync active time +// Default: 0 +#define RTE_MIPI_CSI2_IPI_HSA_TIME 5 + +// Horizontal Synchronism back porch Time range <0-2047> +// Defines possible range for selecting horizontal sync back porch time +// Default: 0 +#define RTE_MIPI_CSI2_IPI_HBP_TIME 10 + +// Horizontal sync delay Time range <0-2047> +// Defines possible range for selecting horizontal sync delay time +// Default: 560 +#define RTE_MIPI_CSI2_IPI_HSD_TIME 280 + +// Horizontal Active Time range <0-2047> +// Defines possible range for selecting horizontal active time +// Default: 560 +#define RTE_MIPI_CSI2_IPI_HACTIVE_TIME 560 + +// Vertical sync active period range <0-511> +// Defines possible range for selecting vertical sync active period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VSA_LINE 4 + +// Vertical back porch period range <0-511> +// Defines possible range for selecting vertical back porch period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VBP_LINE 4 + +// Vertical front porch period range <0-511> +// Defines possible range for selecting vertical front porch period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VFP_LINE 4 + +// Vertical active period range <0-8191> +// Defines possible range for selecting vertical active period +// Default: 560 +#define RTE_MIPI_CSI2_IPI_VACTIVE_LINE 560 + +// CSI2 interrupt priority <0-255> +// Defines CSI2 interrupt priority. +// Default: 0 +#define RTE_MIPI_CSI2_IRQ_PRI 0 + +// ARX3A0 [Driver_ARX3A0] +// Enable/Disable ARX3A0 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable ARX3A0 camera sensor +// default: enable +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera ARX3A0 frame per second +// <5=> 5 FPS +// <40=> 40 FPS +// <60=> 60 FPS +// <90=> 90 FPS +// Defines camera ARX3A0 frame per second +// Default: 90 FPS +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_CFG_FPS 90 + +// Select camera ARX3A0 frequency +// Defines camera ARX3A0 frequency +// Default: 400000000 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_FREQ 400000000 + +// select ARX3A0 CSI2 Data type +// defines select CSI2 Data type +// default: 43(RAW10) +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_DATA_TYPE 43 + +// select ARX3A0 number of lanes in DPHY +// defines select ARX3A0 number of lanes in DPHY. +// default: 2 two lane +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_N_LANES 2 + +// select ARX3A0 virtual channel ID +// defines select ARX3A0 virtual channel ID. +// default: 0 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_VC_ID 0 + +// select ARX3A0 override CPI color mode +// defines select ARX3A0 override CPI color mode. +// default: 1 (Ensable) +#define RTE_ARX3A0_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select ARX3A0 CPI color mode +// defines select ARX3A0 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_ARX3A0_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select ARX3A0 frame height +// defines select ARX3A0 frame height. +// default: 560 +#define RTE_ARX3A0_CAMERA_SENSOR_FRAME_HEIGHT 560 + +// select ARX3A0 frame width +// defines select ARX3A0 frame width. +// default: 560 +#define RTE_ARX3A0_CAMERA_SENSOR_FRAME_WIDTH 560 + +// Select camera sensor ARX3A0 CSI clock source division [Divisor] <2-511> +// Defines camera sensor ARX3A0 CSI clock source division +// Default: 20 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 + +// RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor ARX3A0 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// ARX3A0 [Driver_ARX3A0] + +// AR0144 [Driver_AR0144] +// Enable/Disable AR0144 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0144 camera sensor +// default: enable +#define RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0144 frequency +// Defines camera AR0144 frequency +// Default: 225000000 +#define RTE_AR0144_CAMERA_SENSOR_CSI_FREQ 225000000 + +// select AR0144 CSI2 Data type +// defines select CSI2 Data type +// default: 44(RAW12) +#define RTE_AR0144_CAMERA_SENSOR_CSI_DATA_TYPE 44 + +// select AR0144 number of lanes in DPHY +// defines select AR0144 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0144_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0144 virtual channel ID +// defines select AR0144 virtual channel ID. +// default: 0 +#define RTE_AR0144_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0144 override CPI color mode +// defines select AR0144 override CPI color mode. +// default: 1 (Ensable) +#define RTE_AR0144_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select AR0144 CPI color mode +// defines select AR0144 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_AR0144_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select AR0144 frame height +// defines select AR0144 frame height. +// default: 560 +#define RTE_AR0144_CAMERA_SENSOR_FRAME_HEIGHT 800 + +// select AR0144 frame width +// defines select AR0144 frame width. +// default: 560 +#define RTE_AR0144_CAMERA_SENSOR_FRAME_WIDTH 1280 + +// Select camera sensor AR0144 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0144 CSI clock source division +// Default: 20 +#define RTE_AR0144_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 + +// RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0144 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0114 [Driver_AR0114] + +// AR0145 [Driver_AR0145] +// Enable/Disable AR0145 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0145 camera sensor +// default: enable +#define RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0145 frequency +// Defines camera AR0145 frequency +// Default: 400000000 +#define RTE_AR0145_CAMERA_SENSOR_CSI_FREQ 400000000 + +// select AR0145 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2A(RAW8) +#define RTE_AR0145_CAMERA_SENSOR_CSI_DATA_TYPE 0x2A + +// select AR0145 number of lanes in DPHY +// defines select AR0145 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0145_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0145 virtual channel ID +// defines select AR0145 virtual channel ID. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0145 override CPI color mode +// defines select AR0145 override CPI color mode. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 + +// select AR0145 CPI color mode +// defines select AR0145 CPI color mode. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_CPI_COLOR_MODE 0 + +// select AR0145 Image configuration +// Defines camera sensor AR0145 Image configuration +// <0=> 1280x800_Full_1M +// <1=> 640x400_YSum2_XBin2 +// <2=> 640x400_YSkip2_XSkip2 +// <3=> 320x200_YSkip2_XSkip2 +// Default: 0 +#define RTE_AR0145_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// Select camera sensor AR0145 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0145 CSI clock source division +// Default: 16 +#define RTE_AR0145_CAMERA_SENSOR_CSI_CLK_SCR_DIV 16 + +// RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0145 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0145 [Driver_AR0145] + +// AR0246 [Driver_AR0246] +// Enable/Disable AR0246 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0246 camera sensor +// default: enable +#define RTE_AR0246_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0246_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0246 frequency +// Defines camera AR0246 frequency +// Default: 442000000 +#define RTE_AR0246_CAMERA_SENSOR_CSI_FREQ 442000000 + +// select AR0246 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2C(RAW12) +#define RTE_AR0246_CAMERA_SENSOR_CSI_DATA_TYPE 0x2C + +// select AR0246 number of lanes in DPHY +// defines select AR0246 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0246_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0246 virtual channel ID +// defines select AR0246 virtual channel ID. +// default: 0 +#define RTE_AR0246_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0246 override CPI color mode +// defines select AR0246 override CPI color mode. +// default: 1 (Enable) +#define RTE_AR0246_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select AR0246 CPI color mode +// defines select AR0246 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_AR0246_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select AR0246 frame height +// defines select AR0246 frame height. +// default: 472 +#define RTE_AR0246_CAMERA_SENSOR_FRAME_HEIGHT 472 + +// select AR0246 frame width +// defines select AR0246 frame width. +// default: 684 +#define RTE_AR0246_CAMERA_SENSOR_FRAME_WIDTH 684 + +// Select camera sensor AR0246 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0246 CSI clock source division +// Default: 15 +#define RTE_AR0246_CAMERA_SENSOR_CSI_CLK_SCR_DIV 15 + +// RTE_AR0246_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0246 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0246_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0246 [Driver_AR0246] + +// MT9M114_MIPI [Driver_MT9M114_MIPI] +// Enable/Disable MT9M114 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 MIPI camera sensor +// default: enable +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE 1 + +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE) + +// Select camera MT9M114 MIPI frequency +// Defines camera MT9M114 MIPI frequency +// Default: 296000000 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_FREQ 320000000 + +// select MT9M114 Image configuration +// Defines camera sensor MT9M114 Image configuration +// <0=> 1288x728_RAW10 +// <1=> 1280x720_RAW8 +// <2=> 1280x720_RGB565 +// <3=> 640x480_RGB565 +// <4=> 320x240_RGB565 +// <5=> 320x320_RGB565 +// Default: 1 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 1 + +// select MT9M114 MIPI number of lanes in DPHY +// defines select MT9M114 MIPI number of lanes in DPHY. +// default: 1 one lane +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_N_LANES 1 + +// select MT9M114 MIPI virtual channel ID +// defines select MT9M114 MIPI virtual channel ID. +// default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_VC_ID 0 + +// select MT9M114 MIPI override CPI color mode +// defines select MT9M114 MIPI override CPI color mode. +// default: 0 (Disable) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_OVERRIDE_CPI_COLOR_MODE 0 + +// select MT9M114 MIPI CPI color mode +// defines select MT9M114 MIPI CPI color mode. +// default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CPI_COLOR_MODE 0 + +// Select camera sensor MT9M114 MIPI CSI clock source division [Divisor] <2-511> +// Defines camera sensor MT9M114 MIPI CSI clock source division +// Default: 20 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 + +// RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE +// Defines camera sensor MT9M114 MIPI i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE 1 + +// MT9M114 sensor frame width for ISP / CSI2 pipeline +// Width in pixels of the MT9M114 MIPI sensor frame +#define RTE_MT9M114_CAMERA_SENSOR_FRAME_WIDTH 1280 + +// MT9M114 sensor frame height for ISP / CSI2 pipeline +// Height in pixels of the MT9M114 MIPI sensor frame +#define RTE_MT9M114_CAMERA_SENSOR_FRAME_HEIGHT 720 + +#endif +// MT9M114_MIPI [Driver_MT9M114_MIPI] + +// HM0360_MIPI [Driver_HM0360_MIPI] +// Enable/Disable HM0360 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable HM0360 MIPI camera sensor +// default: enable +#define RTE_HM0360_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_HM0360_CAMERA_SENSOR_ENABLE) + +// Select camera HM0360 frequency +// Defines camera HM0360 frequency +// Default: 176000000 +#define RTE_HM0360_CAMERA_SENSOR_CSI_FREQ 176000000 + +// Select camera HM0360 frame per second +// <30=> 30 FPS +// <60=> 60 FPS +// Defines camera HM0360 frame per second +// Default: 60 FPS +#define RTE_HM0360_CAMERA_SENSOR_CSI_CFG_FPS 60 + +// Select camera HM0360 context select +// <0=> CONTEXT_A +// <1=> CONTEXT_B +// Defines camera HM0360 context select +// Default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL 0 + +// select HM0360 CSI2 Data type +// defines select CSI2 Data type +// default: 42(RAW8) +#define RTE_HM0360_CAMERA_SENSOR_CSI_DATA_TYPE 42 + +// select HM0360 number of lanes in DPHY +// defines select HM0360 number of lanes in DPHY. +// default: 1 one lane +#define RTE_HM0360_CAMERA_SENSOR_CSI_N_LANES 1 + +// select HM0360 virtual channel ID +// defines select HM0360 virtual channel ID. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CSI_VC_ID 0 + +// select HM0360 override CPI color mode +// defines select HM0360 override CPI color mode. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 + +// select HM0360 CPI color mode +// defines select HM0360 CPI color mode. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CPI_COLOR_MODE 0 + +#if (RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL == 0) +// select HM0360 frame height +// defines select HM0360 frame height. +// default: 480 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 480 + +// select HM0360 frame width +// defines select HM0360 frame width. +// default: 640 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 640 +#else +// select HM0360 frame height +// defines select HM0360 frame height. +// default: 240 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 240 + +// select HM0360 frame width +// defines select HM0360 frame width. +// default: 320 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 320 +#endif + +// RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor HM0360 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// HM0360_MIPI [Driver_HM0360_MIPI] + +// OV5647_MIPI [Driver_OV5647_MIPI] +// Enable/Disable OV5647 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable OV5647 MIPI camera sensor +// default: enable +#define RTE_OV5647_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_OV5647_CAMERA_SENSOR_ENABLE) + +// Select camera OV5647 frequency +// Defines camera OV5647 frequency +// Default: 158000000 +#define RTE_OV5647_CAMERA_SENSOR_CSI_FREQ 158000000 + +// select OV5647 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2B (RAW10) +#define RTE_OV5647_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B + +// select OV5647 number of lanes in DPHY +// defines select OV5647 number of lanes in DPHY. +// default: 2 one lane +#define RTE_OV5647_CAMERA_SENSOR_CSI_N_LANES 2 + +// select OV5647 virtual channel ID +// defines select OV5647 virtual channel ID. +// default: 0 +#define RTE_OV5647_CAMERA_SENSOR_CSI_VC_ID 0 + +// select OV5647 override CPI color mode +// defines select OV5647 override CPI color mode. +// default: 1 +#define RTE_OV5647_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select OV5647 CPI color mode +// defines select OV5647 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_OV5647_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select OV5647 frame height +// defines select OV5647 frame height. +// default: 480 +#define RTE_OV5647_CAMERA_SENSOR_FRAME_HEIGHT 480 + +// select OV5647 frame width +// defines select OV5647 frame width. +// default: 640 +#define RTE_OV5647_CAMERA_SENSOR_FRAME_WIDTH 640 + +// Select camera sensor OV5647 i2c instance +// Defines camera sensor OV5647 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_OV5647_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// OV5647_MIPI [Driver_OV5647_MIPI] + +// OV5675_MIPI [Driver_OV5675_MIPI] +// Enable/Disable OV5675 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable OV5675 MIPI camera sensor +// default: enable +#define RTE_OV5675_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_OV5675_CAMERA_SENSOR_ENABLE) + +// Select camera OV5675 frequency +// Defines camera OV5675 frequency +// Default: 450000000 +#define RTE_OV5675_CAMERA_SENSOR_CSI_FREQ 450000000 + +// select OV5675 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2B (RAW10) +#define RTE_OV5675_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B + +// select OV5675 number of lanes in DPHY +// defines select OV5675 number of lanes in DPHY. +// default: 2 lane +#define RTE_OV5675_CAMERA_SENSOR_CSI_N_LANES 2 + +// select OV5675 virtual channel ID +// defines select OV5675 virtual channel ID. +// default: 0 +#define RTE_OV5675_CAMERA_SENSOR_CSI_VC_ID 0 + +// select OV5675 override CPI color mode +// defines select OV5675 override CPI color mode. +// default: 1 +#define RTE_OV5675_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select OV5675 CPI color mode +// defines select OV5675 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select OV5675 frame height +// defines select OV5675 frame height. +// default: 972 +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 + +// select OV5675 frame width +// defines select OV5675 frame width. +// default: 1296 +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 + +// Select camera sensor OV5675 i2c instance +// Defines camera sensor OV5675 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_OV5675_CAMERA_SENSOR_I2C_INSTANCE 1 + +// Select camera sensor OV5675 CSI clock source division [Divisor] <2-511> +// Defines camera sensor OV5675 CSI clock source division +// Default: 20 +#define RTE_OV5675_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 + +#endif +// OV5675_MIPI [Driver_OV5675_MIPI] + +#endif +// MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] + +// MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] +// Configuration settings for Driver_MIPI_DSI in component ::Drivers:MIPI_DSI +#ifndef RTE_MIPI_DSI +#define RTE_MIPI_DSI 1 +#endif // RTE_MIPI_DSI + +#if RTE_MIPI_DSI + +// DPHY PLL input division factor +// Defines DPHY PLL input division factor +// Default: 3 +#define RTE_MIPI_DSI_PLL_INPUT_DIV_FACTOR_N 3 + +// DSI TX escape clock division value. +// Defines DSI TX escape clock division value. +// Default: 2 +#define RTE_MIPI_DSI_TX_ESC_CLK_DIVISION 2 + +// DPI Video Mode +// <0=> NON_BURST SYNC_PULSES +// <1=> NON_BURST SYNC_EVENTS +// <2=> BURST MODE +// Defines DPI Video Mode +// Default:BURST MODE +#define RTE_MIPI_DSI_VID_MODE_TYPE 2 + +// DSI Video number of Chunks +// Defines Number of chunks used to transfer single video packet . +// Default: 0 +#define RTE_MIPI_DSI_VID_NUM_CHUNKS 0 + +// DSI Size of NULL packet +// Defines Size of the NULL packet. +// Default: 0 +#define RTE_MIPI_DSI_VID_NULL_SIZE 0 + +// DSI IRQ priority <0-255> +// Defines Interrupt priority. +// Default: 0 +#define RTE_MIPI_DSI_IRQ_PRI 0 + +// MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] +// DSI ILI9806E LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines DSI ILI9806E LCD PANEL +// Default: ENABLE +#define RTE_MIPI_DSI_ILI9806E_PANEL 1 + +#if RTE_MIPI_DSI_ILI9806E_PANEL + +// DSI ILI9806E panel variant +// <0=> E43RB_FW405 +// <1=> E43GB_MW405 +// <2=> E50RA_MW550 +// Defines ILI9806E panel variant +// Default: E43RB_FW405 +#define RTE_ILI9806E_PANEL_VARIANT 1 + +#if (RTE_ILI9806E_PANEL_VARIANT == 0) +#define RTE_ILI9806E_PANEL_E43RB_FW405_EN 1 +#elif (RTE_ILI9806E_PANEL_VARIANT == 1) +#define RTE_ILI9806E_PANEL_E43GB_MW405_EN 1 +#elif (RTE_ILI9806E_PANEL_VARIANT == 2) +#define RTE_ILI9806E_PANEL_E50RA_MW550_EN 1 +#endif + +// ILI9806 LCD panel maximum bitrate in mbps +// Defines ILI9806 LCD panel maximum bitrate in mbps. +// Default: 500 +#define RTE_ILI9806E_PANEL_MAX_BITRATE_MBPS 500 + +// DSI color mode +// <1=> 16bit +// <4=> 18bit +// <5=> 24bit +// Defines Color mode for display panel +// Default: 24bit +#define RTE_ILI9806E_PANEL_DSI_COLOR_MODE 5 + +// Number of data lanes +// <1=> ONE +// <2=> TWO +// Defines Number of data lanes +// Default: TWO +#define RTE_ILI9806E_PANEL_DSI_N_LANES 0x2 + +// Virtual channel ID +// Defines Virtual Channel ID +// Default: 0 +#define RTE_ILI9806E_PANEL_DSI_VC_ID 0 + +// MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] +#if (RTE_ILI9806E_PANEL_E43RB_FW405_EN || RTE_ILI9806E_PANEL_E43GB_MW405_EN) + +// Panel hsync time in pixels +// Defines ILI9806 LCD panel hsync time in pixels. +// Default: 4 +#define RTE_PANEL_HSYNC_TIME 4 + +// Panel FW405/MW405 hbp time in pixels +// Defines ILI9806 LCD panel hbp time in pixels. +// Default: 5 +#define RTE_PANEL_HBP_TIME 5 + +// Panel FW405/MW405 hfp time in pixels +// Defines ILI9806 LCD panel hfp time in pixels. +// Default: 5 +#define RTE_PANEL_HFP_TIME 5 + +// Panel FW405/MW405 hactive pixels +// Defines ILI9806 LCD panel hactive pixels. +// Default: 480 +#define RTE_PANEL_HACTIVE_TIME 480 + +// Panel FW405/MW405 vsync time in lines +// Defines ILI9806 LCD panel vsync time in lines. +// Default: 2 +#define RTE_PANEL_VSYNC_LINE 2 + +// Panel FW405/MW405 vbp time in lines +// Defines ILI9806 LCD panel vbp time in lines. +// Default: 10 +#define RTE_PANEL_VBP_LINE 10 + +// Panel FW405/MW405 vfp time in lines +// Defines ILI9806 LCD panel vfp time in lines. +// Default: 10 +#define RTE_PANEL_VFP_LINE 10 + +// Panel FW405/MW405 vactive lines +// Defines ILI9806 LCD panel vactive lines. +// Default: 800 +#define RTE_PANEL_VACTIVE_LINE 800 +// MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] + +// MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] +#elif RTE_ILI9806E_PANEL_E50RA_MW550_EN + +// Panel MW550 hsync time in pixels +// Defines ILI9806 LCD panel hsync time in pixels. +// Default: 4 +#define RTE_PANEL_HSYNC_TIME 4 + +// Panel MW550 hbp time in pixels +// Defines ILI9806 LCD panel hbp time in pixels. +// Default: 30 +#define RTE_PANEL_HBP_TIME 30 + +// Panel MW550 hfp time in pixels +// Defines ILI9806 LCD panel hfp time in pixels. +// Default: 18 +#define RTE_PANEL_HFP_TIME 18 + +// Panel MW550 hactive pixels +// Defines ILI9806 LCD panel hactive pixels. +// Default: 480 +#define RTE_PANEL_HACTIVE_TIME 480 + +// Panel MW550 vsync time in lines +// Defines ILI9806 LCD panel vsync time in lines. +// Default: 4 +#define RTE_PANEL_VSYNC_LINE 4 + +// Panel MW550 vbp time in lines +// Defines ILI9806 LCD panel vbp time in lines. +// Default: 30 +#define RTE_PANEL_VBP_LINE 30 + +// Panel MW550 vfp time in lines +// Defines ILI9806 LCD panel vfp time in lines. +// Default: 20 +#define RTE_PANEL_VFP_LINE 20 + +// Panel MW550 vactive lines +// Defines ILI9806 LCD panel vactive lines. +// Default: 854 +#define RTE_PANEL_VACTIVE_LINE 854 +#endif +// MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] + +// MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] +// DSI ILI9488 LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines DSI ILI9488 LCD PANEL +// Default: ENABLE +#define RTE_MIPI_DSI_ILI9488_PANEL 1 + +#if RTE_MIPI_DSI_ILI9488_PANEL + +// ILI9806 LCD panel maximum bitrate in mbps +// Defines ILI9806 LCD panel maximum bitrate in mbps. +// Default: 500 +#define RTE_ILI9488_PANEL_MAX_BITRATE_MBPS 500 + +// DSI color mode +// <1=> 16bit +// <4=> 18bit +// Defines Color mode for display panel +// Default: 16bit +#define RTE_ILI9488_PANEL_DSI_COLOR_MODE 1 + +// Virtual channel ID +// Defines Virtual Channel ID +// Default: 0 +#define RTE_ILI9488_PANEL_DSI_VC_ID 0 + +// Panel hsync time in pixels +// Defines ILI9488 LCD panel hsync time in pixels. +// Default: 10 +#define RTE_ILI9488_PANEL_HSYNC_TIME 10 + +// Panel ILI9488 hbp time in pixels +// Defines ILI9488 LCD panel hbp time in pixels. +// Default: 10 +#define RTE_ILI9488_PANEL_HBP_TIME 10 + +// Panel ILI9488 hfp time in pixels +// Defines ILI9488 LCD panel hfp time in pixels. +// Default: 40 +#define RTE_ILI9488_PANEL_HFP_TIME 40 + +// Panel ILI9488 hactive pixels +// Defines ILI9488 LCD panel hactive pixels. +// Default: 320 +#define RTE_ILI9488_PANEL_HACTIVE_TIME 320 + +// Panel ILI9488 vsync time in lines +// Defines ILI9488 LCD panel vsync time in lines. +// Default: 2 +#define RTE_ILI9488_PANEL_VSYNC_LINE 2 + +// Panel ILI9488 vbp time in lines +// Defines ILI9488 LCD panel vbp time in lines. +// Default: 16 +#define RTE_ILI9488_PANEL_VBP_LINE 16 + +// Panel ILI9488 vfp time in lines +// Defines ILI9488 LCD panel vfp time in lines. +// Default: 10 +#define RTE_ILI9488_PANEL_VFP_LINE 10 + +// Panel ILI9488 vactive lines +// Defines ILI9488 LCD panel vactive lines. +// Default: 480 +#define RTE_ILI9488_PANEL_VACTIVE_LINE 480 + +#endif +// MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] + +#endif +// MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] + +#endif +// MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] + +// TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] +// Configuration settings for Driver_Touch_Screen in component ::Drivers:touch screen +#define RTE_TOUCH_SCREEN 1 + +#if RTE_TOUCH_SCREEN + +// GT911 Touch screen +// <0=> DISABLE +// <1=> ENABLE +// Defines GT911 Touch screen +// Default: ENABLE +#define RTE_GT911 1 + +#if RTE_GT911 + +// select active touch points +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// defines select active touch points +// default: 5 +#define RTE_ACTIVE_TOUCH_POINTS 5 + +// RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL +// Defines GT911 Touchscreen i2c slave address selection +// <0x14=> I2C_SLAVE_ADDRESS_HEX_14 +// <0x5D=> I2C_SLAVE_ADDRESS_HEX_5D +// Default: 0x14 +#define RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL 0x14 +#endif + +#endif +// TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] + +// CDC200 (cdc200) [Driver_CDC200] +// Configuration settings for Driver_CDC200 in component ::Drivers:CDC200 +#define RTE_CDC200 1 + +#if RTE_CDC200 + +// CDC200 IRQ priority <0-255> +// Defines Interrupt priority. +// Default: 0 +#define RTE_CDC200_IRQ_PRI 0 + +// CDC200 clock select +// <0=> Select AXI clock source +// <1=> Select PLL clock source +// Defines CDC200 clock select +// Default: Select AXI clock source +#define RTE_CDC200_CLK_SEL 0 + +// CDC200 background color red <0-255> +// Defines CDC200 background color red. +// Default: 0 +#define RTE_CDC200_BGC_RED 0 + +// CDC200 background color green <0-255> +// Defines CDC200 background color green. +// Default: 0 +#define RTE_CDC200_BGC_GREEN 0 + +// CDC200 background color blue <0-255> +// Defines CDC200 background color blue. +// Default: 0 +#define RTE_CDC200_BGC_BLUE 0 + +// CDC200 pixel format +// <0=> ARGB8888 +// <1=> RGB888 +// <2=> RGB565 +//      <3=> RGBA8888 +//      <6=> ARGB1555 +//      <7=> ARGB4444 +// Defines CDC200 pixel format +// Default: RGB888 +#define RTE_CDC200_PIXEL_FORMAT 1 + +// CDC200 Constant alpha <0-255> +// Defines CDC200 constant alpha range from 0 (fully transparent) to 255 or 1.0 (fully opaque). +// Default: 255 +#define RTE_CDC200_CONSTANT_ALPHA 255 + +// CDC200 blending factor +// <0=> CONST_ALPHA +// <1=> PIXEL_ALPHA_X_CONST_ALPHA +// Defines CDC200 blending factor selection. +// Default: PIXEL_ALPHA_X_CONST_ALPHA +#define RTE_CDC200_BLEND_FACTOR 1 + +// CDC200 DPI interface FPS +// Defines CDC200 DPI interface Framrate per second. +// Default: 60 +#define RTE_CDC200_DPI_FPS 60 + +// Parallel ILI6122 LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines Parallel ILI6122 LCD PANEL +// Default: ENABLE +#ifndef RTE_ILI6122_PANEL +#define RTE_ILI6122_PANEL 0 +#endif // RTE_ILI6122_PANEL + +#if RTE_ILI6122_PANEL + +// CDC HSYNC pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC HSYNC pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_HSYNC_ACTIVE_LOW 0 + +// CDC VSYNC pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC VSYNC pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_VSYNC_ACTIVE_LOW 0 + +// CDC Pixel Clock Output pin active state +// <0=> FEED THROUGH +// <1=> INVERTED +// Defines CDC Pixel Clock pin active state +// Default: FEED THROUGH +#define RTE_ILI6122_PANEL_CDC_PIXCLK_FEED_THROUGH 0 + +// CDC BLANKING pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC BLANKINg pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_BLANK_ACTIVE_LOW 0 + +// Panel hsync time in pixels +// Defines ILI6122 LCD panel hsync time in pixels. +// Default: 1 +#define RTE_PANEL_HSYNC_TIME 1 + +// Panel hbp time in pixels +// Defines ILI6122 LCD panel hbp time in pixels. +// Default: 46 +#define RTE_PANEL_HBP_TIME 46 + +// Panel hfp time in pixels +// Defines ILI6122 LCD panel hfp time in pixels. +// Default: 210 +#define RTE_PANEL_HFP_TIME 210 + +// Panel hactive pixels +// Defines ILI6122 LCD panel hactive pixels. +// Default: 800 +#define RTE_PANEL_HACTIVE_TIME 800 + +// Panel vsync time in lines +// Defines ILI6122 LCD panel vsync time in lines. +// Default: 1 +#define RTE_PANEL_VSYNC_LINE 1 + +// Panel vbp time in lines +// Defines ILI6122 LCD panel vbp time in lines. +// Default: 23 +#define RTE_PANEL_VBP_LINE 23 + +// Panel vfp time in lines +// Defines ILI6122 LCD panel vfp time in lines. +// Default: 22 +#define RTE_PANEL_VFP_LINE 22 + +// Panel vactive lines +// Defines ILI6122 LCD panel vactive lines. +// Default: 480 +#define RTE_PANEL_VACTIVE_LINE 480 +#endif + +#endif +// CDC200 (cdc200) [Driver_CDC200] + +// I3C (Improved Inter Integrated Circuit) +// I3C (Improved Inter-Integrated Circuit) [Driver_I3C] +// Configuration settings for Driver_I3C in component ::Drivers:I3C +#define RTE_I3C 1 + +#if RTE_I3C + +// I3C IRQ priority <0-255> +// Defines I3C Interrupt priority +// Default: 0 +#define RTE_I3C_IRQ_PRI 0 + +// I2C (Inter Integrated Circuit) [Driver_I2CI3C] +// Configuration settings for Driver_I2CI3C in component ::Drivers:I2CI3C +#define RTE_I2CI3C 1 +// I2C (Inter Integrated Circuit) [Driver_I2CI3C] + +// I3C DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I3C +// Default: DISABLE +#define RTE_I3C_DMA_ENABLE 0 + +// I3C DMA Selection +// <0=> DMA2(M55-HE) +// <1=> DMA0 +// Defines Select DMA0 for I3C. By default DMA0 will be considered +// Default: DMA0 +#define RTE_I3C_SELECT_DMA0 1 + +// I3C DMA IRQ priority <0-255> +// Defines I3C DMA Interrupt priority +// Default: 0 +#define RTE_I3C_DMA_IRQ_PRI 0 + +// I3C blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I3C +// Default: DISABLE +#define RTE_I3C_BLOCKING_MODE_ENABLE 0 + +// I3C Slave I2C/I3C Adaptive mode Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines whether I3C Slave starts with I2C mode or not. +// It is for for enabling some features for I2C/I3C mode +// Default: DISABLE +#define RTE_I3C_SLAVE_ADAPTIVE_MODE_ENABLE 0 + +#endif +// I3C (Improved Inter-Integrated Circuit) [Driver_I3C] + +// LPI3C (Low Power Improved Inter-Integrated Circuit) [Driver_LPI3C] +// Configuration settings for Driver_LPI3C in component ::Drivers:LPI3C +#if defined(RTSS_HE) +#define RTE_LPI3C 1 + +#if RTE_LPI3C + +// LPI3C IRQ priority <0-255> +// Defines LPI3C Interrupt priority +// Default: 0 +#define RTE_LPI3C_IRQ_PRI 0 + +// LPI3C DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPI3C +// Default: DISABLE +#define RTE_LPI3C_DMA_ENABLE 0 + +#if RTE_LPI3C_DMA_ENABLE + +// LPI3C DMA IRQ priority <0-255> +// Defines LPI3C DMA Interrupt priority +// Default: 0 +#define RTE_LPI3C_DMA_IRQ_PRI 0 +#endif +// LPI3C blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPI3C +// Default: DISABLE +#define RTE_LPI3C_BLOCKING_MODE_ENABLE 0 + +// LPI3C Slave I2C/I3C Adaptive mode Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines whether LPI3C Slave starts with I2C mode or not. +// It is for for enabling some features for I2C/I3C mode +// Default: DISABLE +#define RTE_LPI3C_SLAVE_ADAPTIVE_MODE_ENABLE 0 + +#endif +#endif +// LPI3C (Low Power Improved Inter-Integrated Circuit) [Driver_LPI3C] +// + +// IMU (Initial Measurement Unit) [Driver_IMU] +// Configuration settings for Driver_IMU in component ::Drivers:IMU +#define RTE_IMU 1 + +#if RTE_IMU + +// ICM42670 (Initial Measurement Unit) [Driver_ICM42670] +// Configuration settings for Driver_ICM42670 in component ::Drivers:IMU +#define RTE_ICM42670 1 + +#if RTE_ICM42670 + +// ICM42670 IMU enable In-band_interrupt +// <0=> DISABLE +// <1=> ENABLE +// Defines whether In-band-interrupt to be enabled +// If disabled, then Normal-GPIO interrupt will be enabled +// Default: DISABLE +#define RTE_ICM42670_IBI_ENABLE 0 + +#endif +// ICM42670 (Initial Measurement Unit) [Driver_ICM42670] + +// BMI323 (Initial Measurement Unit) [Driver_BMI323] +// Configuration settings for Driver_BMI323 in component ::Drivers:IMU +#define RTE_BMI323 1 + +// BMI323 (Initial Measurement Unit) [Driver_BMI323] +#endif +// IMU (Initial Measurement Unit) [Driver_IMU] + +// SPI (Serial Peripheral Interface) +// SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] +// Configuration settings for Driver_SPI0 in component ::Drivers:SPI +#define RTE_SPI0 1 + +#ifdef RTE_SPI0 + +// SPI0 IRQ priority <0-255> +// Defines Interrupt priority for SPI0. +// Default: 0 +#define RTE_SPI0_IRQ_PRIORITY 0 + +// SPI0 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI0. +// Default: 0 +#define RTE_SPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI0 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI0. +// Default: 0 +#define RTE_SPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI0 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI0. +// Default: 0 +#define RTE_SPI0_TX_FIFO_THRESHOLD 0 + +// SPI0 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI0. +// Default: 0 +#define RTE_SPI0_RX_FIFO_THRESHOLD 0 + +// SPI0 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// Defines slave selection for SPI0. +// Default: 0 +#define RTE_SPI0_CHIP_SELECTION_PIN 0 + +// SPI0 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI0. +// Default: 0 +#define RTE_SPI0_RX_SAMPLE_DELAY 0 + +// SPI0 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI0. +// Default: 1 +#define RTE_SPI0_SSTE_ENABLE 1 + +// SPI0 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI0_USE_MASTER_SS_SW 0 + +#if RTE_SPI0_USE_MASTER_SS_SW + +// SPI0 SW SS Port <0-15> +// Defines SPI0 port of SS pin in software controlled mode. +// Default: 0 +#define RTE_SPI0_SW_SPI_PORT 0 + +// SPI0 SW SS Pin <0-7> +// Defines SPI0 SS pin number in software controlled mode. +// Default: 0 +#define RTE_SPI0_SW_SPI_PIN 0 + +// SPI0 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI0. +// Default: 0 +#define RTE_SPI0_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI0_USE_MASTER_SS_SW + +// SPI0 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI0 MicroWire frame format. +// Default: 0 +#define RTE_SPI0_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI0_MICROWIRE_FRF_ENABLE + +// SPI0 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI0 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI0_MW_TRANSFER_MODE 0 + +// SPI0 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI0 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI0_MW_HANDSAHKE_ENABLE 0 + +// SPI0 MW Control Frame Size +// Defines MW Control Frame Size for SPI0. +// Default: 0 +#define RTE_SPI0_MW_CFS 16 +#endif // RTE_SPI0_MICROWIRE_FRF_ENABLE + +// SPI0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI0 +// Default: DISABLE +#define RTE_SPI0_DMA_ENABLE 0 + +// SPI0 DMA IRQ priority <0-255> +// Defines SPI0 DMA Interrupt priority +// Default: 0 +#define RTE_SPI0_DMA_IRQ_PRI 0 + +// SPI0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI0 +// Default: DISABLE +#define RTE_SPI0_BLOCKING_MODE_ENABLE 0 +#endif +// SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SPI1 1 + +#ifdef RTE_SPI1 + +// SPI1 IRQ priority <0-255> +// Defines Interrupt priority for SPI1. +// Default: 0 +#define RTE_SPI1_IRQ_PRIORITY 0 + +// SPI1 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI1. +// Default: 0 +#define RTE_SPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI1 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI1. +// Default: 0 +#define RTE_SPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI1 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI1. +// Default: 0 +#define RTE_SPI1_TX_FIFO_THRESHOLD 0 + +// SPI1 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI1. +// Default: 0 +#define RTE_SPI1_RX_FIFO_THRESHOLD 0 + +// SPI1 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// Defines slave selection for SPI1. +// Default: 0 +#define RTE_SPI1_CHIP_SELECTION_PIN 0 + +// SPI1 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI1. +// Default: 0 +#define RTE_SPI1_RX_SAMPLE_DELAY 0 + +// SPI1 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI1. +// Default: 1 +#define RTE_SPI1_SSTE_ENABLE 1 + +// SPI1 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI1_USE_MASTER_SS_SW 0 + +#if RTE_SPI1_USE_MASTER_SS_SW + +// SPI1 SW SS Port <0-15> +// Defines SPI1 port of SS pin in software controlled mode. +// Default: 0 +#define RTE_SPI1_SW_SPI_PORT 0 + +// SPI1 SW SS pin number <0-7> +// Defines SPI1 SS pin number in software controlled mode. +// Default: 0 +#define RTE_SPI1_SW_SPI_PIN 0 + +// SPI1 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI1. +// Default: 0 +#define RTE_SPI1_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI1_USE_MASTER_SS_SW + +// SPI1 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI1 MicroWire frame format. +// Default: 0 +#define RTE_SPI1_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI1_MICROWIRE_FRF_ENABLE + +// SPI1 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI1 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI1_MW_TRANSFER_MODE 0 + +// SPI1 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI1 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI1_MW_HANDSAHKE_ENABLE 0 + +// SPI1 MW Control Frame Size +// Defines MW Control Frame Size for SPI1. +// Default: 0 +#define RTE_SPI1_MW_CFS 16 +#endif // RTE_SPI1_MICROWIRE_FRF_ENABLE + +// SPI1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI1 +// Default: DISABLE +#define RTE_SPI1_DMA_ENABLE 0 + +// SPI1 DMA IRQ priority <0-255> +// Defines SPI1 DMA Interrupt priority +// Default: 0 +#define RTE_SPI1_DMA_IRQ_PRI 0 + +// SPI1 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI1 +// Default: DISABLE +#define RTE_SPI1_BLOCKING_MODE_ENABLE 0 +#endif +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI2 1 + +#ifdef RTE_SPI2 + +// SPI2 IRQ priority <0-255> +// Defines Interrupt priority for SPI2. +// Default: 0 +#define RTE_SPI2_IRQ_PRIORITY 0 + +// SPI2 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI2. +// Default: 0 +#define RTE_SPI2_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI2 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI2. +// Default: 0 +#define RTE_SPI2_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI2 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI2. +// Default: 0 +#define RTE_SPI2_TX_FIFO_THRESHOLD 0 + +// SPI2 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI2. +// Default: 0 +#define RTE_SPI2_RX_FIFO_THRESHOLD 0 + +// SPI2 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// Defines slave selection for SPI2. +// Default: 0 +#define RTE_SPI2_CHIP_SELECTION_PIN 0 + +// SPI2 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI2. +// Default: 0 +#define RTE_SPI2_RX_SAMPLE_DELAY 0 + +// SPI2 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI2. +// Default: 1 +#define RTE_SPI2_SSTE_ENABLE 1 + +// SPI2 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI2_USE_MASTER_SS_SW 0 + +#if RTE_SPI2_USE_MASTER_SS_SW + +// SPI2 SW SS Port <0-15> +// Defines SPI2 port of SS pin in software controlled mode +// Default: 0 +#define RTE_SPI2_SW_SPI_PORT 0 + +// SPI2 SW SS pin number <0-7> +// Defines SPI2 SS pin number in software controlled mode +// Default: 0 +#define RTE_SPI2_SW_SPI_PIN 0 + +// SPI2 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI2. +// Default: 0 +#define RTE_SPI2_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI2_USE_MASTER_SS_SW + +// SPI2 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI2 MicroWire frame format. +// Default: 0 +#define RTE_SPI2_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI2_MICROWIRE_FRF_ENABLE + +// SPI2 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI2 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI2_MW_TRANSFER_MODE 0 + +// SPI2 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI2 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI2_MW_HANDSAHKE_ENABLE 0 + +// SPI2 MW Control Frame Size +// Defines MW Control Frame Size for SPI2. +// Default: 0 +#define RTE_SPI2_MW_CFS 0 +#endif // RTE_SPI2_MICROWIRE_FRF_ENABLE + +// SPI2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI2 +// Default: DISABLE +#define RTE_SPI2_DMA_ENABLE 0 + +// SPI2 DMA IRQ priority <0-255> +// Defines SPI2 DMA Interrupt priority +// Default: 0 +#define RTE_SPI2_DMA_IRQ_PRI 0 + +// SPI2 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI2 +// Default: DISABLE +#define RTE_SPI2_BLOCKING_MODE_ENABLE 0 +#endif +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::Drivers:SPI +#define RTE_SPI3 1 + +#ifdef RTE_SPI3 + +// SPI3 IRQ priority <0-255> +// Defines Interrupt priority for SPI3. +// Default: 0 +#define RTE_SPI3_IRQ_PRIORITY 0 + +// SPI3 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI3. +// Default: 0 +#define RTE_SPI3_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI3 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI3. +// Default: 0 +#define RTE_SPI3_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI3 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI3. +// Default: 0 +#define RTE_SPI3_TX_FIFO_THRESHOLD 0 + +// SPI3 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI3. +// Default: 0 +#define RTE_SPI3_RX_FIFO_THRESHOLD 0 + +// SPI3 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// Defines slave selection for SPI3. +// Default: 0 +#define RTE_SPI3_CHIP_SELECTION_PIN 1 + +// SPI3 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI3. +// Default: 0 +#define RTE_SPI3_RX_SAMPLE_DELAY 0 + +// SPI3 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI3. +// Default: 1 +#define RTE_SPI3_SSTE_ENABLE 1 + +// SPI3 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI3_USE_MASTER_SS_SW 0 + +#if RTE_SPI3_USE_MASTER_SS_SW + +// SPI3 SW SS Port <0-15> +// Defines SPI3 port of SS pin in software controlled mode +// Default: 0 +#define RTE_SPI3_SW_SPI_PORT 0 + +// SPI3 SW SS pin number <0-7> +// Defines SPI3 SS pin number in software controlled mode +// Default: 0 +#define RTE_SPI3_SW_SPI_PIN 0 + +// SPI3 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI3. +// Default: 0 +#define RTE_SPI3_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI3_USE_MASTER_SS_SW + +// SPI3 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI3 MicroWire frame format. +// Default: 0 +#define RTE_SPI3_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI3_MICROWIRE_FRF_ENABLE + +// SPI3 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI3 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI3_MW_TRANSFER_MODE 0 + +// SPI3 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI3 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI3_MW_HANDSAHKE_ENABLE 0 + +// SPI3 MW Control Frame Size +// Defines MW Control Frame Size for SPI3. +// Default: 0 +#define RTE_SPI3_MW_CFS 0 +#endif // RTE_SPI3_MICROWIRE_FRF_ENABLE + +// SPI3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI3 +// Default: DISABLE +#define RTE_SPI3_DMA_ENABLE 0 + +// SPI3 DMA IRQ priority <0-255> +// Defines SPI3 DMA Interrupt priority +// Default: 0 +#define RTE_SPI3_DMA_IRQ_PRI 0 + +// SPI3 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI3 +// Default: DISABLE +#define RTE_SPI3_BLOCKING_MODE_ENABLE 0 +#endif +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] + +// LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] +// Configuration settings for Driver_LPSPI in component ::Drivers:SPI +#if defined(RTSS_HE) + +#define RTE_LPSPI 1 + +#ifdef RTE_LPSPI + +// LPSPI mode configuration +// <0=> SLAVE +// <1=> MASTER +// Configure LPSPI mode. +// Default: 1 +#define RTE_LPSPI_CONFIG_MASTER_SLAVE 1 + +// LPSPI IRQ priority <0-255> +// Defines Interrupt priority for LPSPI. +// Default: 0 +#define RTE_LPSPI_IRQ_PRIORITY 0 + +// LPSPI TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// LPSPI load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// LPSPI TX FIFO threshold <0-15> +// Defines TX FIFO threshold for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_FIFO_THRESHOLD 0 + +// LPSPI RX FIFO threshold <0-15> +// Defines RX FIFO threshold for LPSPI. +// Default: 0 +#define RTE_LPSPI_RX_FIFO_THRESHOLD 0 + +// LPSPI slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// <4=> SS_4 +// <5=> SS_5 +// Defines slave selection for LPSPI. +// Default: 0 +#define RTE_LPSPI_CHIP_SELECTION_PIN 0 + +// LPSPI Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for LPSPI. +// Default: 1 +#define RTE_LPSPI_SSTE_ENABLE 1 + +// LPSPI Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_LPSPI_USE_MASTER_SS_SW 0 + +#if RTE_LPSPI_USE_MASTER_SS_SW + +// LPSPI SW SS Port <0-15> +// Defines LPSPI port of SS pin in software controlled mode +// Default: 0 +#define RTE_LPSPI_SW_SPI_PORT 0 + +// LPSPI SW SS pin number <0-7> +// Defines LPSPI SS pin number in software controlled mode +// Default: 0 +#define RTE_LPSPI_SW_SPI_PIN 0 + +// LPSPI SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for LPSPI. +// Default: 0 +#define RTE_LPSPI_SW_SPI_SS_POLARITY 0 +#endif // RTE_LPSPI_USE_MASTER_SS_SW + +// LPSPI Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of LPSPI MicroWire frame format. +// Default: 0 +#define RTE_LPSPI_MICROWIRE_FRF_ENABLE 0 + +#if RTE_LPSPI_MICROWIRE_FRF_ENABLE + +// LPSPI MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines LPSPI MicroWire transfer mode. +// Default: 0 +#define RTE_LPSPI_MW_TRANSFER_MODE 0 + +// LPSPI MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines LPSPI MicroWire handshake enable. +// Default: 0 +#define RTE_LPSPI_MW_HANDSAHKE_ENABLE 0 + +// LPSPI MW Control Frame Size +// Defines MW Control Frame Size for LPSPI. +// Default: 0 +#define RTE_LPSPI_MW_CFS 8 +#endif // RTE_LPSPI_MICROWIRE_FRF_ENABLE + +// LPSPI DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPSPI +// Default: DISABLE +#define RTE_LPSPI_DMA_ENABLE 0 +#if RTE_LPSPI_DMA_ENABLE + +// LPSPI DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPSPI. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPSPI_SELECT_DMA0 0 +#if RTE_LPSPI_SELECT_DMA0 + +// LPSPI DMA0 Group Selection +// <1=> DMA0_GROUP_1 +// <2=> DMA0_GROUP_2 +// Defines DMA0 Group for LPSPI. By default DMA0 Group 1 will be considered +// Default: DMA0_GROUP_1 +#define RTE_LPSPI_SELECT_DMA0_GROUP 1 +#endif // RTE_LPSPI_SELECT_DMA0 +#endif // RTE_LPSPI_DMA_ENABLE + +// LPSPI DMA IRQ priority <0-255> +// Defines LPSPI DMA Interrupt priority +// Default: 0 +#define RTE_LPSPI_DMA_IRQ_PRI 0 + +// LPSPI blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPSPI +// Default: DISABLE +#define RTE_LPSPI_BLOCKING_MODE_ENABLE 0 +#endif // RTE_LPSPI +#endif // RTSS_HE + +// LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] +// SPI (Serial Peripheral Interface) + +// OSPI (Octal Serial Peripheral Interface) +// OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] +// Configuration settings for Driver_OSPI in component ::Drivers:OSPI +#define RTE_OSPI0 1 +#if RTE_OSPI0 +// OSPI0 IRQ priority <0-255> +// Defines OSPI0 Interrupt priority +// Default: 0 +#define RTE_OSPI0_IRQ_PRIORITY 0 + +// OSPI0 Frame format +// <0=> Standard SPI FRF +// <1=> Dual SPI FRF +// <2=> Quad SPI FRF +// <3=> Octal SPI FRF +// <4=> Dual Octal SPI FRF +// Defines OSPI0 Frame format +// Default: Octal SPI FRF +#define RTE_OSPI0_SPI_FRAME_FORMAT 3 + +// OSPI0 Bus speed +// Defines the OSPI0 Bus speed +// Default: 100000000 +#define RTE_OSPI0_BUS_SPEED 100000000 + +// OSPI0 Wait Cycles +// Defines the OSPI0 Wait Cycles for connected device +// Default: 6 +#define RTE_OSPI0_WAIT_CYCLES 6 + +// OSPI0 DFS +// Defines OSPI0 Data Frame Size +// Default: 32 +#define RTE_OSPI0_DFS 32 + +// OSPI0 TX FIFO Start level <0-255> +// Defines TX FIFO transfer start level for OSPI0 +// Default: 0 +#define RTE_OSPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// OSPI0 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// Load dummy data to start transfer for OSPI0 +// Default: DISABLE +#define RTE_OSPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// OSPI0 TX FIFO threshold <0-255> +// Defines TX FIFO threshold for OSPI0 +// Default: 64 +#define RTE_OSPI0_TX_FIFO_THRESHOLD 64 + +// OSPI0 RX FIFO threshold <0-255> +// Defines RX FIFO threshold for OSPI0 +// Default: 0 +#define RTE_OSPI0_RX_FIFO_THRESHOLD 0 + +// OSPI0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Enable DMA for OSPI0 +// Default: DISABLE +#define RTE_OSPI0_DMA_ENABLE 0 +#if RTE_OSPI0_DMA_ENABLE + +// OSPI0 TX DMA Data level +// Defines TX DMA Data level for OSPI0 +// Default: 64 +#define RTE_OSPI0_TX_DMA_DATA_LEVEL 64 + +// OSPI0 RX DMA Data level +// Defines RX DMA Data level for OSPI0 +// Default: 15 +#define RTE_OSPI0_RX_DMA_DATA_LEVEL 15 + +// OSPI0 DMA IRQ priority <0-255> +// Defines OSPI0 DMA Interrupt priority +// Default: 0 +#define RTE_OSPI0_DMA_IRQ_PRIORITY 0 +#endif + +// OSPI0 slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for OSPI0 +// Default: 0 +#define RTE_OSPI0_CHIP_SELECTION_PIN 0 + +// OSPI0 RX SAMPLE DELAY +// Defines RX SAMPLE DELAY for OSPI0 +// Default: 0 +#define RTE_OSPI0_RX_SAMPLE_DELAY 0 + +// OSPI0 DDR DRIVE EDGE +// Defines DDR DRIVE EDGE for OSPI0 +// Default: 0 +#define RTE_OSPI0_DDR_DRIVE_EDGE 1 + +// OSPI0 RXDS Delay <0-23> +// Defines the delay applied to the RXDS signal of OSPI0 +// Default: 0 +#define RTE_OSPI0_RXDS_DELAY 11 + +// OSPI0 Signal Delay <0-23> +// Defines the delay applied to signals of OSPI0 +// Default: 0 +#define RTE_OSPI0_SIGNAL_DELAY 22 +#endif +// OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] + +// OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] +// Configuration settings for Driver_OSPI in component ::Drivers:OSPI +#define RTE_OSPI1 1 +#if RTE_OSPI1 +// OSPI1 IRQ priority <0-255> +// Defines OSPI1 Interrupt priority +// Default: 0 +#define RTE_OSPI1_IRQ_PRIORITY 0 + +// OSPI1 Frame format +// <0=> Standard SPI FRF +// <1=> Dual SPI FRF +// <2=> Quad SPI FRF +// <3=> Octal SPI FRF +// <4=> Dual Octal SPI FRF +// Defines OSPI0 Frame format +// Default: Octal SPI FRF +#define RTE_OSPI1_SPI_FRAME_FORMAT 3 + +// OSPI1 Bus speed +// Defines the OSPI1 Bus speed +// Default: 100000000 +#define RTE_OSPI1_BUS_SPEED 100000000 + +// OSPI1 Wait Cycles +// Defines the OSPI1 Wait Cycles for connected device +// Default: 16 +#define RTE_OSPI1_WAIT_CYCLES 3 + +// OSPI1 DFS +// Defines OSPI1 Data Frame Size +// Default: 32 +#define RTE_OSPI1_DFS 32 + +// OSPI1 TX FIFO Start level <0-255> +// Defines TX FIFO transfer start level for OSPI1 +// Default: 0 +#define RTE_OSPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// OSPI1 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// Load dummy data to start transfer for OSPI1 +// Default: DISABLE +#define RTE_OSPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// OSPI1 TX FIFO threshold <0-255> +// Defines TX FIFO threshold for OSPI1 +// Default: 64 +#define RTE_OSPI1_TX_FIFO_THRESHOLD 64 + +// OSPI1 RX FIFO threshold <0-255> +// Defines RX FIFO threshold for OSPI1 +// Default: 0 +#define RTE_OSPI1_RX_FIFO_THRESHOLD 0 + +// OSPI1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Enable DMA for OSPI1 +// Default: DISABLE +#define RTE_OSPI1_DMA_ENABLE 0 +#if RTE_OSPI1_DMA_ENABLE + +// OSPI1 TX DMA Data level +// Defines TX DMA Data level for OSPI1 +// Default: 130 +#define RTE_OSPI1_TX_DMA_DATA_LEVEL 130 + +// OSPI1 RX DMA Data level +// Defines RX DMA Data level for OSPI1 +// Default: 15 +#define RTE_OSPI1_RX_DMA_DATA_LEVEL 15 + +// OSPI1 DMA IRQ priority <0-255> +// Defines OSPI1 DMA Interrupt priority +// Default: 0 +#define RTE_OSPI1_DMA_IRQ_PRIORITY 0 +#endif + +// OSPI1 slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for OSPI1. +// Default: 0 +#define RTE_OSPI1_CHIP_SELECTION_PIN 0 + +// OSPI1 RX SAMPLE DELAY +// Defines RX SAMPLE DELAY for OSPI1 +// Default: 0 +#define RTE_OSPI1_RX_SAMPLE_DELAY 0 + +// OSPI1 DDR DRIVE EDGE +// Defines DDR DRIVE EDGE for OSPI1 +// Default: 1 +#define RTE_OSPI1_DDR_DRIVE_EDGE 1 + +// OSPI1 RXDS Delay <0-23> +// Defines the delay applied to the RXDS signal of OSPI1 +// Default: 11 +#define RTE_OSPI1_RXDS_DELAY 11 + +// OSPI1 Signal Delay <0-23> +// Defines the delay applied to signals of OSPI1 +// Default: 0 +#define RTE_OSPI1_SIGNAL_DELAY 0 +#endif +// OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] +// OSPI (Octal Serial Peripheral Interface) + +// FLASH +// FLASH (ISSI FLASH) [Driver_Flash] +// Configuration settings for Driver_Flash in component ::Drivers:Flash +#define RTE_ISSI_FLASH 1 +#if RTE_ISSI_FLASH + +// ISSI FLASH SIZE +// ISSI flash density in bytes +// Default: 0x4000000 +#define RTE_ISSI_FLASH_SIZE 0x4000000 + +// ISSI FLASH OSPI Instance +// Defines the OSPI controller instance the ISSI flash is connected to +// Default: 1 +#define RTE_ISSI_FLASH_OSPI_DRV_NUM 1 + +// ISSI FLASH OSPI Bus speed +// Defines the OSPI Bus speed +// Default: 100000000 +#define RTE_ISSI_FLASH_OSPI_BUS_SPEED 100000000 + +// ISSI FLASH Wait cycles +// Defines the number of wait (dummy) cycles needed for fast read operations +// Default: 16 +#define RTE_ISSI_FLASH_WAIT_CYCLES 16 +#endif +// FLASH (ISSI FLASH) [Driver_Flash] + +// FLASH (MX66UW1G FLASH) [Driver_MX66UW1G_FLASH] +// Configuration settings for Driver_MX66UW1G_FLASH in component ::Drivers:Flash +#define RTE_MX66UW1G_FLASH 1 +#if RTE_MX66UW1G_FLASH + +// MX66UW1G FLASH SIZE +// MX66UW1G flash density in bytes +// Default: 0x4000000 +#define RTE_MX66UW1G_FLASH_SIZE 0x4000000 + +// MX66UW1G FLASH OSPI Instance +// Defines the OSPI controller instance the MX66UW1G flash is connected to +// Default: 1 +#define RTE_MX66UW1G_FLASH_OSPI_DRV_NUM 1 + +// MX66UW1G FLASH OSPI Bus speed +// Defines the OSPI Bus speed +// Default: 100000000 +#define RTE_MX66UW1G_FLASH_OSPI_BUS_SPEED 100000000 + +// MX66UW1G FLASH Wait cycles +// Defines the number of wait (dummy) cycles needed for fast read operations +// Default: 10 +#define RTE_MX66UW1G_FLASH_WAIT_CYCLES 10 +#endif +// FLASH (MX66UW1G FLASH) [Driver_MX66UW1G_FLASH] +// FLASH + +// APS512XXN PSRAM +// APS512XXN PSRAM [Driver_APS512XXN_PSRAM] +// Configuration settings for Driver_APS512XXN_PSRAM in component ::Drivers:APS512XXN_PSRAM +#define RTE_APS512XXN_PSRAM 1 +#if RTE_APS512XXN_PSRAM + +// APS512XXN PSRAM Wait cycles +// Defines the number of wait cycles needed for fast read write operations. +// Default: 4 +#define RTE_APS512XXN_PSRAM_WAIT_CYCLES 4 + +// APS512XXN PSRAM Enable Dual Octal Mode +// <0=> Disable +// <1=> Enable +// Defines APS512XXN PSRAM SPI Mode. +// Default: 0 +#define RTE_APS512XXN_PSRAM_DUAL_OCTAL_MODE_ENABLE 1 + +// APS512XXN PSRAM OSPI slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for APS512XXN PSRAM. +// Default: 0 +#define RTE_APS512XXN_PSRAM_OSPI_SS_LINE 0 +#endif +// APS512XXN PSRAM [Driver_APS512XXN_PSRAM] +// APS512XXN PSRAM + +// S80K HYPERRAM +// S80K HYPERRAM [Driver_S80K_HYPERRAM] +// Configuration settings for Driver_S80K_HYPERRAM in component ::Drivers:S80K_HYPERRAM +#define RTE_S80K_HYPERRAM 1 +#if RTE_S80K_HYPERRAM + +// S80K HYPERRAM Wait cycles +// Defines the number of wait cycles needed for fast read write operations. +// Default: 3 +#define RTE_S80K_HYPERRAM_WAIT_CYCLES 3 + +// S80K HYPERRAM SPI MODE +// <0=> Octal mode +// <1=> Dual Octal mode +// Defines S80K HYPERRAM SPI Mode. +// Default: 0 +#define RTE_S80K_HYPERRAM_SPI_MODE 1 +#endif +// S80K HYPERRAM [Driver_S80K_HYPERRAM] +// S80K HYPERRAM + +// I2S (Integrated Interchip Sound) +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] +// Configuration settings for Driver_SAI0 in component ::Drivers:SAI +#define RTE_I2S0 1 + +#if RTE_I2S0 + +// I2S0 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S0 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S0_WSS_CLOCK_CYCLES 2 + +// I2S0 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S0 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S0_SCLKG_CLOCK_CYCLES 0 + +// I2S0 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S0 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S0_RX_TRIG_LVL 7 + +// I2S0 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S0 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S0_TX_TRIG_LVL 8 + +// I2S0 IRQ priority <0-255> +// Defines I2S0 Interrupt priority +// Default: 0 +#define RTE_I2S0_IRQ_PRI 0 + +// I2S0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S0 +// Default: ENABLE +#define RTE_I2S0_DMA_ENABLE 0 + +// I2S0 DMA IRQ priority <0-255> +// Defines I2S0 DMA Interrupt priority +// Default: 0 +#define RTE_I2S0_DMA_IRQ_PRI 0 + +// I2S0 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S0 +// Default: DISABLE +#define RTE_I2S0_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] + +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] +// Configuration settings for Driver_SAI1 in component ::Drivers:SAI +#define RTE_I2S1 1 + +#if RTE_I2S1 + +// I2S1 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S1 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S1_WSS_CLOCK_CYCLES 2 + +// I2S1 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S1 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S1_SCLKG_CLOCK_CYCLES 0 + +// I2S1 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S1 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S1_RX_TRIG_LVL 7 + +// I2S1 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S1 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S1_TX_TRIG_LVL 8 + +// I2S1 IRQ priority <0-255> +// Defines I2S1 Interrupt priority +// Default: 1 +#define RTE_I2S1_IRQ_PRI 1 + +// I2S1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S1 +// Default: ENABLE +#define RTE_I2S1_DMA_ENABLE 0 + +// I2S1 DMA IRQ priority <0-255> +// Defines I2S1 DMA Interrupt priority +// Default: 0 +#define RTE_I2S1_DMA_IRQ_PRI 0 + +// I2S1 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S1 +// Default: DISABLE +#define RTE_I2S1_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] + +// I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] +// Configuration settings for Driver_SAI2 in component ::Drivers:SAI +#define RTE_I2S2 1 + +#if RTE_I2S2 + +// I2S2 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S2 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S2_WSS_CLOCK_CYCLES 2 + +// I2S2 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S2 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S2_SCLKG_CLOCK_CYCLES 0 + +// I2S2 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S2 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S2_RX_TRIG_LVL 7 + +// I2S2 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S2 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S2_TX_TRIG_LVL 8 + +// I2S2 IRQ priority <0-255> +// Defines I2S2 Interrupt priority +// Default: 0 +#define RTE_I2S2_IRQ_PRI 10 + +// I2S2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S2 +// Default: ENABLE +#define RTE_I2S2_DMA_ENABLE 0 + +// I2S2 DMA IRQ priority <0-255> +// Defines I2S2 DMA Interrupt priority +// Default: 0 +#define RTE_I2S2_DMA_IRQ_PRI 0 + +// I2S2 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S2 +// Default: DISABLE +#define RTE_I2S2_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] + +// I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] +// Configuration settings for Driver_SAI3 in component ::Drivers:SAI +#define RTE_I2S3 1 + +#if RTE_I2S3 + +// I2S3 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S3 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S3_WSS_CLOCK_CYCLES 2 + +// I2S3 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S3 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S3_SCLKG_CLOCK_CYCLES 0 + +// I2S3 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S3 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S3_RX_TRIG_LVL 7 + +// I2S3 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S3 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S3_TX_TRIG_LVL 8 + +// I2S3 IRQ priority <0-255> +// Defines I2S3 Interrupt priority +// Default: 0 +#define RTE_I2S3_IRQ_PRI 0 + +// I2S3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S3 +// Default: ENABLE +#define RTE_I2S3_DMA_ENABLE 0 + +// I2S3 DMA IRQ priority <0-255> +// Defines I2S3 DMA Interrupt priority +// Default: 0 +#define RTE_I2S3_DMA_IRQ_PRI 0 + +// I2S3 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S3 +// Default: DISABLE +#define RTE_I2S3_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] + +// LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] +// Configuration settings for Driver_SAILP in component ::Drivers:SAI +#if defined(RTSS_HE) + +#define RTE_LPI2S 1 + +#if RTE_LPI2S + +// LPI2S WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines LPI2S size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_LPI2S_WSS_CLOCK_CYCLES 2 + +// LPI2S SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines LPI2S SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_LPI2S_SCLKG_CLOCK_CYCLES 0 + +// LPI2S RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines LPI2S receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_LPI2S_RX_TRIG_LVL 7 + +// LPI2S TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines LPI2S transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_LPI2S_TX_TRIG_LVL 8 + +// LPI2S IRQ priority <0-255> +// Defines LPI2S Interrupt priority +// Default: 1 +#define RTE_LPI2S_IRQ_PRI 1 + +// LPI2S DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPI2S +// Default: ENABLE +#define RTE_LPI2S_DMA_ENABLE 0 +#if RTE_LPI2S_DMA_ENABLE + +// LPI2S DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPI2S. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPI2S_SELECT_DMA0 0 +#endif + +// LPI2S DMA IRQ priority <0-255> +// Defines LPI2S DMA Interrupt priority +// Default: 0 +#define RTE_LPI2S_DMA_IRQ_PRI 0 + +// LPI2S Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPI2S +// Default: DISABLE +#define RTE_LPI2S_BLOCKING_MODE_ENABLE 0 + +#endif // RTE_LPI2S +#endif // defined(RTSS_HE) + +// LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] +// I2S (Integrated Interchip Sound) + +// WM8904 Codec [Driver_WM8904] +// Configuration settings for Driver_WM8904 in component ::Drivers:WM8904 +#define RTE_WM8904_CODEC 1 + +#if RTE_WM8904_CODEC + +// Select WM8904 i2c instance +// Defines WM8904 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_WM8904_CODEC_I2C_INSTANCE 1 +#endif + +// WM8904 Codec [Driver_WM8904] + +// UART (Universal asynchronous receiver transmitter) +// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_UART0 1 + +#if RTE_UART0 + +// UART0 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART0 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART0_RX_TRIG_LVL 0 + +// UART0 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART0 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART0_TX_TRIG_LVL 0 + +// UART0 IRQ priority <0-255> +// Defines Interrupt priority for UART0. +// Default: 0 +#define RTE_UART0_IRQ_PRI 0 + +// UART0 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART0 clock source. +// Default: CLK_100MHz +#define RTE_UART0_CLK_SOURCE 1 + +// UART0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART0 +// Default: DISABLE +#define RTE_UART0_DMA_ENABLE 0 + +// UART0 DMA IRQ priority <0-255> +// Defines UART0 DMA Interrupt priority +// Default: 0 +#define RTE_UART0_DMA_IRQ_PRI 0 + +// UART0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART0 +// Default: DISABLE +#define RTE_UART0_BLOCKING_MODE_ENABLE 0 + +#endif // UART0 + +// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_UART1 1 + +#if RTE_UART1 + +// UART1 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART1 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART1_RX_TRIG_LVL 0 + +// UART1 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART1 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART1_TX_TRIG_LVL 0 + +// UART1 IRQ priority <0-255> +// Defines Interrupt priority for UART1. +// Default: 0 +#define RTE_UART1_IRQ_PRI 0 + +// UART1 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART1 clock source. +// Default: CLK_100MHz +#define RTE_UART1_CLK_SOURCE 1 + +// UART1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART1 +// Default: DISABLE +#define RTE_UART1_DMA_ENABLE 0 + +// UART1 DMA IRQ priority <0-255> +// Defines UART1 DMA Interrupt priority +// Default: 0 +#define RTE_UART1_DMA_IRQ_PRI 0 + +// UART1 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART1 +// Default: DISABLE +#define RTE_UART1_BLOCKING_MODE_ENABLE 0 + +#endif // UART1 + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] + +// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::Drivers:USART +#define RTE_UART2 1 + +#if RTE_UART2 + +// UART2 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART2 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART2_RX_TRIG_LVL 0 + +// UART2 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART2 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART2_TX_TRIG_LVL 0 + +// UART2 IRQ priority <0-255> +// Defines Interrupt priority for UART2. +// Default: 0 +#define RTE_UART2_IRQ_PRI 0 + +// UART2 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART2 clock source. +// Default: CLK_100MHz +#define RTE_UART2_CLK_SOURCE 1 + +// UART2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART2 +// Default: DISABLE +#define RTE_UART2_DMA_ENABLE 0 + +// UART2 DMA IRQ priority <0-255> +// Defines UART2 DMA Interrupt priority +// Default: 0 +#define RTE_UART2_DMA_IRQ_PRI 0 + +// UART2 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART2 +// Default: DISABLE +#define RTE_UART2_BLOCKING_MODE_ENABLE 0 + +#endif // UART2 + +// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] + +// UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::Drivers:USART +#define RTE_UART3 1 + +#if RTE_UART3 + +// UART3 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART3 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART3_RX_TRIG_LVL 0 + +// UART3 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART3 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART3_TX_TRIG_LVL 0 + +// UART3 IRQ priority <0-255> +// Defines Interrupt priority for UART3. +// Default: 0 +#define RTE_UART3_IRQ_PRI 0 + +// UART3 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART3 clock source. +// Default: CLK_100MHz +#define RTE_UART3_CLK_SOURCE 1 + +// UART3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART3 +// Default: DISABLE +#define RTE_UART3_DMA_ENABLE 0 + +// UART3 DMA IRQ priority <0-255> +// Defines UART3 DMA Interrupt priority +// Default: 0 +#define RTE_UART3_DMA_IRQ_PRI 0 + +// UART3 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART3 +// Default: DISABLE +#define RTE_UART3_BLOCKING_MODE_ENABLE 0 + +#endif // UART3 + +// UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] +// Configuration settings for Driver_USART4 in component ::Drivers:USART +#define RTE_UART4 1 + +#if RTE_UART4 + +// UART4 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART4 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART4_RX_TRIG_LVL 0 + +// UART4 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART4 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART4_TX_TRIG_LVL 0 + +// UART4 IRQ priority <0-255> +// Defines Interrupt priority for UART4. +// Default: 0 +#define RTE_UART4_IRQ_PRI 0 + +// UART4 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART4 clock source. +// Default: CLK_100MHz +#define RTE_UART4_CLK_SOURCE 1 + +#define RTE_UART4_RS485_ENABLE 0 +#if RTE_UART4_RS485_ENABLE +#define RTE_UART4_RS485_TRANSFER_MODE 2 +#define RTE_UART4_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART4_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART4_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART4_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART4 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART4 +// Default: DISABLE +#define RTE_UART4_DMA_ENABLE 0 + +// UART4 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART4. By default DMA0 will be considered. +// Default: DMA0 +#define RTE_UART4_SELECT_DMA0 1 + +// UART4 DMA IRQ priority <0-255> +// Defines UART4 DMA Interrupt priority +// Default: 0 +#define RTE_UART4_DMA_IRQ_PRI 0 + +// UART4 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART4 +// Default: DISABLE +#define RTE_UART4_BLOCKING_MODE_ENABLE 1 + +#endif // UART4 + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] +// Configuration settings for Driver_USART5 in component ::Drivers:USART +#define RTE_UART5 1 + +#if RTE_UART5 + +// UART5 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART5 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART5_RX_TRIG_LVL 0 + +// UART5 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART5 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART5_TX_TRIG_LVL 0 + +// UART5 IRQ priority <0-255> +// Defines Interrupt priority for UART5. +// Default: 0 +#define RTE_UART5_IRQ_PRI 0 + +// UART5 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART5 clock source. +// Default: CLK_100MHz +#define RTE_UART5_CLK_SOURCE 1 + +#define RTE_UART5_RS485_ENABLE 0 +#if RTE_UART5_RS485_ENABLE +#define RTE_UART5_RS485_TRANSFER_MODE 2 +#define RTE_UART5_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART5_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART5_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART5_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART5 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART5 +// Default: DISABLE +#define RTE_UART5_DMA_ENABLE 0 + +// UART5 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART5. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART5_SELECT_DMA0 1 + +// UART5 DMA IRQ priority <0-255> +// Defines UART5 DMA Interrupt priority +// Default: 0 +#define RTE_UART5_DMA_IRQ_PRI 0 + +// UART5 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART5 +// Default: DISABLE +#define RTE_UART5_BLOCKING_MODE_ENABLE 0 + +#endif // UART5 + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] + +// UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] +// Configuration settings for Driver_USART6 in component ::Drivers:USART +#define RTE_UART6 1 + +#if RTE_UART6 + +// UART6 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART6 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART6_RX_TRIG_LVL 0 + +// UART6 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART6 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART6_TX_TRIG_LVL 0 + +// UART6 IRQ priority <0-255> +// Defines Interrupt priority for UART6. +// Default: 0 +#define RTE_UART6_IRQ_PRI 0 + +// UART6 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART6 clock source. +// Default: CLK_100MHz +#define RTE_UART6_CLK_SOURCE 1 + +#define RTE_UART6_RS485_ENABLE 0 +#if RTE_UART6_RS485_ENABLE +#define RTE_UART6_RS485_TRANSFER_MODE 2 +#define RTE_UART6_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART6_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART6_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART6_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART6 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART6 +// Default: DISABLE +#define RTE_UART6_DMA_ENABLE 0 + +// UART6 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART6. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART6_SELECT_DMA0 1 + +// UART6 DMA IRQ priority <0-255> +// Defines UART6 DMA Interrupt priority +// Default: 0 +#define RTE_UART6_DMA_IRQ_PRI 0 + +// UART6 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART6 +// Default: DISABLE +#define RTE_UART6_BLOCKING_MODE_ENABLE 0 + +#endif // UART6 + +// UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] +// Configuration settings for Driver_USART7 in component ::Drivers:USART +#define RTE_UART7 1 + +#if RTE_UART7 + +// UART7 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART7 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART7_RX_TRIG_LVL 0 + +// UART7 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART7 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART7_TX_TRIG_LVL 0 + +// UART7 IRQ priority <0-255> +// Defines Interrupt priority for UART7. +// Default: 0 +#define RTE_UART7_IRQ_PRI 0 + +// UART7 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART7 clock source. +// Default: CLK_100MHz +#define RTE_UART7_CLK_SOURCE 1 + +#define RTE_UART7_RS485_ENABLE 0 +#if RTE_UART7_RS485_ENABLE +#define RTE_UART7_RS485_TRANSFER_MODE 2 +#define RTE_UART7_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART7_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART7_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART7_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART7 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART7 +// Default: DISABLE +#define RTE_UART7_DMA_ENABLE 0 + +// UART7 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART7. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART7_SELECT_DMA0 1 + +// UART7 DMA IRQ priority <0-255> +// Defines UART7 DMA Interrupt priority +// Default: 0 +#define RTE_UART7_DMA_IRQ_PRI 0 + +// UART7 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART7 +// Default: DISABLE +#define RTE_UART7_BLOCKING_MODE_ENABLE 0 + +#endif // UART7 + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] + +// LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] +// Configuration settings for Driver_USARTLP in component ::Drivers:USART +#if defined(RTSS_HE) +#define RTE_LPUART 1 +#endif + +#if RTE_LPUART + +// LPUART RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines LPUART receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_LPUART_RX_TRIG_LVL 0 + +// LPUART TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines LPUART transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_LPUART_TX_TRIG_LVL 0 + +// LPUART IRQ priority <0-255> +// Defines Interrupt priority for LPUART. +// Default: 0 +#define RTE_LPUART_IRQ_PRI 0 + +// LPUART DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPUART +// Default: DISABLE +#define RTE_LPUART_DMA_ENABLE 0 + +// LPUART DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPUART. By default DMA0 will be considered +// Default: DMA0 +#define RTE_LPUART_SELECT_DMA0 1 + +// LPUART DMA IRQ priority <0-255> +// Defines LPUART DMA Interrupt priority +// Default: 0 +#define RTE_LPUART_DMA_IRQ_PRI 0 + +// LPUART blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPUART +// Default: DISABLE +#define RTE_LPUART_BLOCKING_MODE_ENABLE 0 + +#endif // RTE_LPUART + +// LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] +// UART (Universal asynchronous receiver transmitter) + +// LPTIMER (Low power timer) +// LPTIMER (Low power timer) [Driver_LPTIMER] +// Configuration settings for Driver_LPTIMER in component ::Drivers:LPTIMER +#define RTE_LPTIMER 1 + +#if RTE_LPTIMER + +// LPTIMER CHANNEL 0 +// Configuration settings for Driver_LPTIMER channel 0 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL0 1 + +// CHANNEL0 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 0. +// Default: 0 +#define RTE_LPTIMER_CHANNEL0_IRQ_PRIORITY (0) + +// CHANNEL0 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel0. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL0_FREE_RUN_MODE (0) + +// CHANNEL0 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// Defines clock source for channel0. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL0_CLK_SRC (0) +// LPTIMER CHANNEL 0 + +// LPTIMER CHANNEL 1 +// Configuration settings for Driver_LPTIMER channel 1 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL1 1 + +// CHANNEL1 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 1. +// Default: 0 +#define RTE_LPTIMER_CHANNEL1_IRQ_PRIORITY (0) + +// CHANNEL1 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel1. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL1_FREE_RUN_MODE (0) + +// CHANNEL1 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// <3=> CLK_CASCADE +// Defines clock source for channel1. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL1_CLK_SRC (0) +// LPTIMER CHANNEL 1 + +// LPTIMER CHANNEL 2 +// Configuration settings for Driver_LPTIMER channel 2 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL2 1 + +// CHANNEL2 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 2. +// Default: 0 +#define RTE_LPTIMER_CHANNEL2_IRQ_PRIORITY (0) + +// CHANNEL2 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel2. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL2_FREE_RUN_MODE (0) + +// CHANNEL2 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// Defines clock source for channel2. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL2_CLK_SRC (0) +// LPTIMER CHANNEL 2 + +// LPTIMER CHANNEL 3 +// Configuration settings for Driver_LPTIMER channel 3 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL3 1 + +// CHANNEL3 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 3. +// Default: 0 +#define RTE_LPTIMER_CHANNEL3_IRQ_PRIORITY (0) + +// CHANNEL3 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel3. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL3_FREE_RUN_MODE (0) + +// CHANNEL3 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// <3=> CLK_CASCADE +// Defines clock source for channel3. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL3_CLK_SRC (0) +// LPTIMER CHANNEL 3 +#endif /* RTE_LPTIMER */ +// LPTIMER (Low power timer) [Driver_LPTIMER] +// LPTIMER (Low power timer) + +// RTC (Real time clock) +// RTC0 (Real time clock) [Driver_RTC0] +// Configuration settings for Driver_RTC0 in component ::Drivers:RTC +#define RTE_RTC0 1 + +#if RTE_RTC0 + +// RTC0 IRQ priority <0-255> +// Defines Interrupt priority for RTC0. +// Default: 0 +#define RTE_RTC0_IRQ_PRI 0 +#endif +// RTC0 (Real time clock) [Driver_RTC0] +// RTC (Real time clock) + +// WDT (Watchdog Timer) +// WDT0 (Watchdog Timer) [Driver_WDT0] +// Configuration settings for Driver_WDT0 in component ::Drivers:WDT +#define RTE_WDT0 1 +// WDT0 (Watchdog Timer) [Driver_WDT0] +// WDT (Watchdog Timer) + +// UTIMER (Universal Timer) +// UTIMER (Universal Timer) [Driver_UTIMER] +// Configuration settings for Driver_UTIMER in component ::Drivers:UTIMER +#define RTE_UTIMER 1 + +#if RTE_UTIMER + +// UTIMER CHANNEL 0 +// Configuration settings for UTIMER channel 0 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL0 1 + +// CHANNEL0 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_FIXED_BUFFER 0 + +// CHANNEL0 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DMA_CLEAR_ENABLE 0 + +// CHANNEL0 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 0. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL0_FAULT_TYPE 0 + +// CHANNEL0 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 0. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL0_BUF_TROUGH_N_CREST 0 + +// CHANNEL0 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DRIVER_A 1 + +// CHANNEL0 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DRIVER_B 0 + +// CHANNEL0 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_A_START_STATE 0 + +// CHANNEL0 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_A_STOP_STATE 0 + +// CHANNEL0 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL0 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_B_START_STATE 0 + +// CHANNEL0 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_B_STOP_STATE 0 + +// CHANNEL0 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL0 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_EVENT_AT_CREST 1 + +// CHANNEL0 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_EVENT_AT_TROUGH 0 + +// CHANNEL0 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 0. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE 0 + +// CHANNEL0 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 0. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL0_BUFFER_OPERATION 0 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 0 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_A 2 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 0 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_B 0 + +// CHANNEL0 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL0 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_ENABLE 0 + +// CHANNEL0 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 0 + +// UTIMER CHANNEL 1 +// Configuration settings for UTIMER channel 1 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL1 1 + +// CHANNEL1 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_FIXED_BUFFER 0 + +// CHANNEL1 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DMA_CLEAR_ENABLE 0 + +// CHANNEL1 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 1. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL1_FAULT_TYPE 0 + +// CHANNEL1 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL1_BUF_TROUGH_N_CREST 0 + +// CHANNEL1 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DRIVER_A 0 + +// CHANNEL1 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DRIVER_B 0 + +// CHANNEL1 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_A_START_STATE 0 + +// CHANNEL1 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_A_STOP_STATE 0 + +// CHANNEL1 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL1 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_B_START_STATE 0 + +// CHANNEL1 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_B_STOP_STATE 0 + +// CHANNEL1 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL1 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_EVENT_AT_CREST 1 + +// CHANNEL1 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_EVENT_AT_TROUGH 0 + +// CHANNEL1 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 1. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE 1 + +// CHANNEL1 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 1. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL1_BUFFER_OPERATION 1 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 1 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_A 0 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 1 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_B 0 + +// CHANNEL1 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL1 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 1 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL1 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 1 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL1 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_ENABLE 0 + +// CHANNEL1 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 1 + +// UTIMER CHANNEL 2 +// Configuration settings for UTIMER channel 2 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL2 1 + +// CHANNEL2 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_FIXED_BUFFER 0 + +// CHANNEL2 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DMA_CLEAR_ENABLE 0 + +// CHANNEL2 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 2. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL2_FAULT_TYPE 0 + +// CHANNEL2 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 2. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL2_BUF_TROUGH_N_CREST 0 + +// CHANNEL2 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DRIVER_A 0 + +// CHANNEL2 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DRIVER_B 0 + +// CHANNEL2 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_A_START_STATE 0 + +// CHANNEL2 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_A_STOP_STATE 0 + +// CHANNEL2 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL2 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_B_START_STATE 0 + +// CHANNEL2 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_B_STOP_STATE 0 + +// CHANNEL2 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL2 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_EVENT_AT_CREST 1 + +// CHANNEL2 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_EVENT_AT_TROUGH 0 + +// CHANNEL2 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 2. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE 1 + +// CHANNEL2 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 2. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL2_BUFFER_OPERATION 1 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 2 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_A 2 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 2 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_B 0 + +// CHANNEL2 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel2 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL2 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 2 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL2 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 2 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL2 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_ENABLE 0 + +// CHANNEL2 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 2 + +// UTIMER CHANNEL 3 +// Configuration settings for UTIMER channel 3 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL3 1 + +// CHANNEL3 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_FIXED_BUFFER 0 + +// CHANNEL3 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DMA_CLEAR_ENABLE 0 + +// CHANNEL3 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 3. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL3_FAULT_TYPE 0 + +// CHANNEL3 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 3. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL3_BUF_TROUGH_N_CREST 0 + +// CHANNEL3 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DRIVER_A 0 + +// CHANNEL3 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DRIVER_B 0 + +// CHANNEL3 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_A_START_STATE 0 + +// CHANNEL3 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_A_STOP_STATE 0 + +// CHANNEL3 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL3 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL3 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_B_START_STATE 0 + +// CHANNEL3 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_B_STOP_STATE 0 + +// CHANNEL3 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL3 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL3 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_EVENT_AT_CREST 1 + +// CHANNEL3 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_EVENT_AT_TROUGH 0 + +// CHANNEL3 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 3. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE 0 + +// CHANNEL3 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 3. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL3_BUFFER_OPERATION 0 + +// CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 3 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_A 0 + +// CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 3 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_B 0 + +// CHANNEL3 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL3 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 3 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL3 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 3 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL3 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_ENABLE 0 + +// CHANNEL3 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 3 + +// UTIMER CHANNEL 4 +// Configuration settings for UTIMER channel 4 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL4 1 + +// CHANNEL4 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_FIXED_BUFFER 0 + +// CHANNEL4 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DMA_CLEAR_ENABLE 0 + +// CHANNEL4 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 4. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL4_FAULT_TYPE 0 + +// CHANNEL4 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL4_BUF_TROUGH_N_CREST 0 + +// CHANNEL4 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DRIVER_A 1 + +// CHANNEL4 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DRIVER_B 0 + +// CHANNEL4 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_A_START_STATE 0 + +// CHANNEL4 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_A_STOP_STATE 0 + +// CHANNEL4 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL4 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL4 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_B_START_STATE 0 + +// CHANNEL4 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_B_STOP_STATE 0 + +// CHANNEL4 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL4 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL4 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_EVENT_AT_CREST 1 + +// CHANNEL4 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_EVENT_AT_TROUGH 1 + +// CHANNEL4 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 4. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE 1 + +// CHANNEL4 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 4. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL4_BUFFER_OPERATION 1 + +// CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 4 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_A 2 + +// CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 4 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_B 2 + +// CHANNEL4 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL4 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 4 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL4 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 4 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL4 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_ENABLE 0 + +// CHANNEL4 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 4 + +// UTIMER CHANNEL 5 +// Configuration settings for UTIMER channel 5 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL5 1 + +// CHANNEL5 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_FIXED_BUFFER 0 + +// CHANNEL5 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DMA_CLEAR_ENABLE 0 + +// CHANNEL5 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 5. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL5_FAULT_TYPE 0 + +// CHANNEL5 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 5. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL5_BUF_TROUGH_N_CREST 0 + +// CHANNEL5 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DRIVER_A 1 + +// CHANNEL5 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DRIVER_B 0 + +// CHANNEL5 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_A_START_STATE 0 + +// CHANNEL5 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_A_STOP_STATE 0 + +// CHANNEL5 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_MATCH_COUNT 3 + +// CHANNEL5 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_CYCLE_END 3 + +// CHANNEL5 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_B_START_STATE 0 + +// CHANNEL5 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_B_STOP_STATE 0 + +// CHANNEL5 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL5 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL5 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_EVENT_AT_CREST 1 + +// CHANNEL5 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_EVENT_AT_TROUGH 0 + +// CHANNEL5 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 5. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE 1 + +// CHANNEL5 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 5. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL5_BUFFER_OPERATION 1 + +// CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 5 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_A 2 + +// CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 5 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_B 0 + +// CHANNEL5 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL5 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 5 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL5 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 5 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL5 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_ENABLE 0 + +// CHANNEL5 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 5 + +// UTIMER CHANNEL 6 +// Configuration settings for UTIMER channel 6 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL6 1 + +// CHANNEL6 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_FIXED_BUFFER 0 + +// CHANNEL6 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DMA_CLEAR_ENABLE 0 + +// CHANNEL6 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 6. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL6_FAULT_TYPE 0 + +// CHANNEL6 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 6. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL6_BUF_TROUGH_N_CREST 0 + +// CHANNEL6 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DRIVER_A 1 + +// CHANNEL6 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DRIVER_B 0 + +// CHANNEL6 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_A_START_STATE 0 + +// CHANNEL6 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_A_STOP_STATE 0 + +// CHANNEL6 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_MATCH_COUNT 3 + +// CHANNEL6 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_CYCLE_END 3 + +// CHANNEL6 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_B_START_STATE 0 + +// CHANNEL6 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_B_STOP_STATE 0 + +// CHANNEL6 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL6 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL6 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_EVENT_AT_CREST 1 + +// CHANNEL6 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_EVENT_AT_TROUGH 0 + +// CHANNEL6 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 6. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE 0 + +// CHANNEL6 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 6. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL6_BUFFER_OPERATION 0 + +// CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 6 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_A 0 + +// CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 6 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_B 0 + +// CHANNEL6 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL6 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 6 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL6 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 6 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL6 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_ENABLE 0 + +// CHANNEL6 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 6 + +// UTIMER CHANNEL 7 +// Configuration settings for UTIMER channel 7 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL7 1 + +// CHANNEL7 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_FIXED_BUFFER 0 + +// CHANNEL7 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DMA_CLEAR_ENABLE 0 + +// CHANNEL7 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 7. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL7_FAULT_TYPE 0 + +// CHANNEL7 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 7. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL7_BUF_TROUGH_N_CREST 0 + +// CHANNEL7 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DRIVER_A 0 + +// CHANNEL7 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DRIVER_B 0 + +// CHANNEL7 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_A_START_STATE 0 + +// CHANNEL7 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_A_STOP_STATE 0 + +// CHANNEL7 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL7 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL7 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_B_START_STATE 0 + +// CHANNEL7 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_B_STOP_STATE 0 + +// CHANNEL7 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL7 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL7 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_EVENT_AT_CREST 1 + +// CHANNEL7 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_EVENT_AT_TROUGH 0 + +// CHANNEL7 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 7. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE 1 + +// CHANNEL7 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 7. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL7_BUFFER_OPERATION 1 + +// CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 7 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_A 2 + +// CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 7 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_B 0 + +// CHANNEL7 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL7 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 7 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL7 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 7 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL7 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_ENABLE 0 + +// CHANNEL7 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 7 + +// UTIMER CHANNEL 8 +// Configuration settings for UTIMER channel 8 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL8 1 + +// CHANNEL8 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_FIXED_BUFFER 0 + +// CHANNEL8 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DMA_CLEAR_ENABLE 0 + +// CHANNEL8 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 8. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL8_FAULT_TYPE 0 + +// CHANNEL8 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 8. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL8_BUF_TROUGH_N_CREST 0 + +// CHANNEL8 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DRIVER_A 1 + +// CHANNEL8 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DRIVER_B 0 + +// CHANNEL8 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_A_START_STATE 0 + +// CHANNEL8 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_A_STOP_STATE 0 + +// CHANNEL8 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_MATCH_COUNT 1 + +// CHANNEL8 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_CYCLE_END 2 + +// CHANNEL8 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_B_START_STATE 0 + +// CHANNEL8 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_B_STOP_STATE 0 + +// CHANNEL8 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL8 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL8 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_EVENT_AT_CREST 1 + +// CHANNEL8 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_EVENT_AT_TROUGH 0 + +// CHANNEL8 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 8. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE 0 + +// CHANNEL8 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 8. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL8_BUFFER_OPERATION 0 + +// CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 8 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_A 2 + +// CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 8 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_B 0 + +// CHANNEL8 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL8 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 8 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL8 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 8 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL8 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_ENABLE 0 + +// CHANNEL8 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 8 + +// UTIMER CHANNEL 9 +// Configuration settings for UTIMER channel 9 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL9 1 + +// CHANNEL9 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_FIXED_BUFFER 0 + +// CHANNEL9 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DMA_CLEAR_ENABLE 0 + +// CHANNEL9 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 9. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL9_FAULT_TYPE 0 + +// CHANNEL9 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 9. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL9_BUF_TROUGH_N_CREST 0 + +// CHANNEL9 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DRIVER_A 0 + +// CHANNEL9 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DRIVER_B 1 + +// CHANNEL9 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_A_START_STATE 0 + +// CHANNEL9 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_A_STOP_STATE 0 + +// CHANNEL9 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL9 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL9 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_B_START_STATE 0 + +// CHANNEL9 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_B_STOP_STATE 0 + +// CHANNEL9 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_MATCH_COUNT 1 + +// CHANNEL9 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_CYCLE_END 2 + +// CHANNEL9 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_EVENT_AT_CREST 1 + +// CHANNEL9 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_EVENT_AT_TROUGH 0 + +// CHANNEL9 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 9. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE 0 + +// CHANNEL9 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 9. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL9_BUFFER_OPERATION 0 + +// CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 9 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_A 0 + +// CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 9 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_B 0 + +// CHANNEL9 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL9 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 9 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL9 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 9 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL9 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_ENABLE 0 + +// CHANNEL9 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 9 + +// UTIMER CHANNEL 10 +// Configuration settings for UTIMER channel 10 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL10 1 + +// CHANNEL10 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_FIXED_BUFFER 0 + +// CHANNEL10 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DMA_CLEAR_ENABLE 0 + +// CHANNEL10 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 10. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL10_FAULT_TYPE 0 + +// CHANNEL10 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 10. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL10_BUF_TROUGH_N_CREST 0 + +// CHANNEL10 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DRIVER_A 1 + +// CHANNEL10 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DRIVER_B 0 + +// CHANNEL10 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_A_START_STATE 0 + +// CHANNEL10 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_A_STOP_STATE 0 + +// CHANNEL10 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_MATCH_COUNT 1 + +// CHANNEL10 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_CYCLE_END 2 + +// CHANNEL10 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_B_START_STATE 0 + +// CHANNEL10 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_B_STOP_STATE 0 + +// CHANNEL10 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL10 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL10 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_EVENT_AT_CREST 1 + +// CHANNEL10 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_EVENT_AT_TROUGH 0 + +// CHANNEL10 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 10. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE 0 + +// CHANNEL10 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 10. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL10_BUFFER_OPERATION 0 + +// CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 10 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_A 2 + +// CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 10 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_B 0 + +// CHANNEL10 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL10 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 10 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL10 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 10 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL10 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_ENABLE 0 + +// CHANNEL10 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 10 + +// UTIMER CHANNEL 11 +// Configuration settings for UTIMER channel 11 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL11 1 + +// CHANNEL11 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_FIXED_BUFFER 0 + +// CHANNEL11 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DMA_CLEAR_ENABLE 0 + +// CHANNEL11 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 11. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL11_FAULT_TYPE 0 + +// CHANNEL11 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 11. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL11_BUF_TROUGH_N_CREST 0 + +// CHANNEL11 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DRIVER_A 0 + +// CHANNEL11 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DRIVER_B 0 + +// CHANNEL11 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_A_START_STATE 0 + +// CHANNEL11 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_A_STOP_STATE 0 + +// CHANNEL11 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL11 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL11 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_B_START_STATE 0 + +// CHANNEL11 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_B_STOP_STATE 0 + +// CHANNEL11 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL11 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL11 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_EVENT_AT_CREST 1 + +// CHANNEL11 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_EVENT_AT_TROUGH 0 + +// CHANNEL11 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 11. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE 1 + +// CHANNEL11 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 11. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL11_BUFFER_OPERATION 1 + +// CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 11 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_A 2 + +// CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 11 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_B 0 + +// CHANNEL11 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL11 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 11 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL11 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 11 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL11 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_ENABLE 0 +// UTIMER CHANNEL 11 + +// UTIMER CHANNEL 12 +// Configuration settings for UTIMER channel 12 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL12 1 + +// CHANNEL11 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_VALUE 0 + +// CHANNEL12 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_FIXED_BUFFER 0 + +// CHANNEL12 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DMA_CLEAR_ENABLE 0 + +// CHANNEL12 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 12. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL12_FAULT_TYPE 0 + +// CHANNEL12 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 12. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL12_BUF_TROUGH_N_CREST 0 + +// CHANNEL12 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DRIVER_A 1 + +// CHANNEL12 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DRIVER_B 0 + +// CHANNEL12 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_A_START_STATE 0 + +// CHANNEL12 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_A_STOP_STATE 0 + +// CHANNEL12 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL12 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL12 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_B_START_STATE 0 + +// CHANNEL12 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_B_STOP_STATE 0 + +// CHANNEL12 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL12 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL12 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_EVENT_AT_CREST 1 + +// CHANNEL12 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_EVENT_AT_TROUGH 0 + +// CHANNEL12 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 12. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE 0 + +// CHANNEL12 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 12. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL12_BUFFER_OPERATION 0 + +// CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 12 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_A 0 + +// CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 12 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_B 0 + +// CHANNEL12 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL12 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 12 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL12 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 12 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL12 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_ENABLE 0 + +// CHANNEL12 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 12 + +// UTIMER CHANNEL 13 +// Configuration settings for UTIMER channel 13 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL13 1 + +// CHANNEL13 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_FIXED_BUFFER 0 + +// CHANNEL13 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DMA_CLEAR_ENABLE 0 + +// CHANNEL13 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 13. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL13_FAULT_TYPE 0 + +// CHANNEL13 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 13. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL13_BUF_TROUGH_N_CREST 0 + +// CHANNEL13 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DRIVER_A 1 + +// CHANNEL13 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DRIVER_B 0 + +// CHANNEL13 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_A_START_STATE 0 + +// CHANNEL13 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_A_STOP_STATE 0 + +// CHANNEL13 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL13 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL13 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_B_START_STATE 0 + +// CHANNEL13 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_B_STOP_STATE 0 + +// CHANNEL13 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL13 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL13 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_EVENT_AT_CREST 1 + +// CHANNEL13 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_EVENT_AT_TROUGH 0 + +// CHANNEL13 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 13. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE 0 + +// CHANNEL13 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 13. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL13_BUFFER_OPERATION 0 + +// CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 13 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_A 0 + +// CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 13 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_B 0 + +// CHANNEL13 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL13 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 13 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL13 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 13 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL13 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_ENABLE 0 + +// CHANNEL13 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 13 + +// UTIMER CHANNEL 14 +// Configuration settings for UTIMER channel 14 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL14 1 + +// CHANNEL14 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_FIXED_BUFFER 0 + +// CHANNEL14 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DMA_CLEAR_ENABLE 0 + +// CHANNEL14 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 14. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL14_FAULT_TYPE 0 + +// CHANNEL14 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 14. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL14_BUF_TROUGH_N_CREST 0 + +// CHANNEL14 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DRIVER_A 1 + +// CHANNEL14 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DRIVER_B 0 + +// CHANNEL14 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_A_START_STATE 0 + +// CHANNEL14 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_A_STOP_STATE 0 + +// CHANNEL14 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL14 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL14 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_B_START_STATE 0 + +// CHANNEL14 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_B_STOP_STATE 0 + +// CHANNEL14 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL14 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL14 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_EVENT_AT_CREST 1 + +// CHANNEL14 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_EVENT_AT_TROUGH 0 + +// CHANNEL14 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 14. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE 0 + +// CHANNEL14 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 14. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL14_BUFFER_OPERATION 0 + +// CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 14 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_A 0 + +// CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 14 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_B 0 + +// CHANNEL14 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL14 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 14 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL14 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 14 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL14 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_ENABLE 0 + +// CHANNEL14 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 14 + +// UTIMER CHANNEL 15 +// Configuration settings for UTIMER channel 15 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL15 1 + +// CHANNEL15 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_FIXED_BUFFER 0 + +// CHANNEL15 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DMA_CLEAR_ENABLE 0 + +// CHANNEL15 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 15. +// Default: LOW_UNTIL_CYCLE_END +#define RTE_UTIMER_CHANNEL15_FAULT_TYPE 0 + +// CHANNEL15 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 15. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL15_BUF_TROUGH_N_CREST 0 + +// CHANNEL15 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DRIVER_A 1 + +// CHANNEL15 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DRIVER_B 0 + +// CHANNEL15 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_A_START_STATE 0 + +// CHANNEL15 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_A_STOP_STATE 0 + +// CHANNEL15 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL15 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL15 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_B_START_STATE 0 + +// CHANNEL15 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_B_STOP_STATE 0 + +// CHANNEL15 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL15 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL15 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_EVENT_AT_CREST 1 + +// CHANNEL15 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_EVENT_AT_TROUGH 0 + +// CHANNEL15 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 15. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE 0 + +// CHANNEL15 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 15. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL15_BUFFER_OPERATION 0 + +// CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 15 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_A 0 + +// CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 15 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_B 0 + +// CHANNEL15 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL15 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 15 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL15 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 15 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL15 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_ENABLE 0 + +// CHANNEL15 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 15 +#endif /*RTE_UTIMER*/ +// UTIMER (Universal timer) [Driver_UTIMER] + +// LPUTIMER (Low-Power Universal Timer) [Driver_UTIMERLP] +// Configuration settings for Driver_UTIMERLP in component ::Drivers:UTIMER +#define RTE_LPUTIMER 1 + +#if RTE_LPUTIMER + +// LPUTIMER CHANNEL 0 +// Configuration settings for LPUTIMER channel 0 in component ::Drivers:UTIMERLP +#define RTE_LPUTIMER_CHANNEL0 1 + +// CHANNEL0 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for LP UT channel 0. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL0_FIXED_BUFFER 0 + +// CHANNEL0 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for LP UT channel 0. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL0_DMA_CLEAR_ENABLE 0 + +// CHANNEL0 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for LP UT channel 0. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_LPUTIMER_CHANNEL0_FAULT_TYPE 0 + +// CHANNEL0 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of LP UT channel 0. +// Default: BUF_AT_TROUGH +#define RTE_LPUTIMER_CHANNEL0_BUF_TROUGH_N_CREST 0 + +// CHANNEL0 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for LP UT channel 0. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL0_DRIVER_A 1 + +// CHANNEL0 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for LP UT channel 0. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL0_DRIVER_B 0 + +// CHANNEL0 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for LP UT channel 0. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL0_DRV_A_START_STATE 0 + +// CHANNEL0 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for LP UT channel 0. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL0_DRV_A_STOP_STATE 0 + +// CHANNEL0 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL0 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for LP UT channel 0. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL0_DRV_B_START_STATE 0 + +// CHANNEL0 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for LP UT channel 0. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL0_DRV_B_STOP_STATE 0 + +// CHANNEL0 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL0 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_EVENT_AT_CREST 1 + +// CHANNEL0 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for LP UT channel 0. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL0_EVENT_AT_TROUGH 0 + +// CHANNEL0 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for LP UT channel 0. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL0_BUFFERING_TYPE 0 + +// CHANNEL0 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for LP UT channel 0. +// Default: ENABLE +#define RTE_LPUTIMER_CHANNEL0_BUFFER_OPERATION 0 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 0 capture mode. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL0_BUFFERING_TYPE_A 2 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 0 capture mode. +// Default: NO BUFFER +#define RTE_LPUTIMER_CHANNEL0_BUFFERING_TYPE_B 0 + +// CHANNEL0 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture A. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture B. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture C. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture D. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture E. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture F. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL0 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 overflow interrupt. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 underflow interrupt. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for LP UT channel 0. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL0_DUTY_CYCLE_ENABLE 0 + +// CHANNEL0 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for LP UT channel 0. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL0_DUTY_CYCLE_VALUE 0 +// LPUTIMER CHANNEL 0 + +// LPUTIMER CHANNEL 1 +// Configuration settings for LPUTIMER channel 1 in component ::Drivers:UTIMERLP +#define RTE_LPUTIMER_CHANNEL1 1 + +// CHANNEL1 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for LP UT channel 1. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL1_FIXED_BUFFER 0 + +// CHANNEL1 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for LP UT channel 1. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL1_DMA_CLEAR_ENABLE 0 + +// CHANNEL1 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for LP UT channel 1. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_LPUTIMER_CHANNEL1_FAULT_TYPE 0 + +// CHANNEL1 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of LP UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_LPUTIMER_CHANNEL1_BUF_TROUGH_N_CREST 0 + +// CHANNEL1 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for LP UT channel 1. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL1_DRIVER_A 0 + +// CHANNEL1 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for LP UT channel 1. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL1_DRIVER_B 0 + +// CHANNEL1 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for LP UT channel 1. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL1_DRV_A_START_STATE 0 + +// CHANNEL1 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for LP UT channel 1. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL1_DRV_A_STOP_STATE 0 + +// CHANNEL1 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL1 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for LP UT channel 1. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL1_DRV_B_START_STATE 0 + +// CHANNEL1 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for LP UT channel 1. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL1_DRV_B_STOP_STATE 0 + +// CHANNEL1 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL1 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_EVENT_AT_CREST 1 + +// CHANNEL1 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for LP UT channel 1. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL1_EVENT_AT_TROUGH 0 + +// CHANNEL1 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for LP UT channel 1. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL1_BUFFERING_TYPE 1 + +// CHANNEL1 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for LP UT channel 1. +// Default: ENABLE +#define RTE_LPUTIMER_CHANNEL1_BUFFER_OPERATION 1 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 1 capture mode. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL1_BUFFERING_TYPE_A 0 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 1 capture mode. +// Default: NO BUFFER +#define RTE_LPUTIMER_CHANNEL1_BUFFERING_TYPE_B 0 + +// CHANNEL1 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for LP UT channel 1. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL1_DUTY_CYCLE_ENABLE 0 + +// CHANNEL1 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for LP UT channel 1. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL1_DUTY_CYCLE_VALUE 0 +// LPUTIMER CHANNEL 1 + +// LPUTIMER CHANNEL 2 +// Configuration settings for LPUTIMER channel 2 in component ::Drivers:UTIMERLP +#define RTE_LPUTIMER_CHANNEL2 1 + +// CHANNEL2 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for LP UT channel 2. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL2_FIXED_BUFFER 0 + +// CHANNEL2 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for LP UT channel 2. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL2_DMA_CLEAR_ENABLE 0 + +// CHANNEL2 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for LP UT channel 2. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_LPUTIMER_CHANNEL2_FAULT_TYPE 0 + +// CHANNEL2 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of LP UT channel 2. +// Default: BUF_AT_TROUGH +#define RTE_LPUTIMER_CHANNEL2_BUF_TROUGH_N_CREST 0 + +// CHANNEL2 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for LP UT channel 2. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL2_DRIVER_A 0 + +// CHANNEL2 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for LP UT channel 2. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL2_DRIVER_B 0 + +// CHANNEL2 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for LP UT channel 2. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL2_DRV_A_START_STATE 0 + +// CHANNEL2 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for LP UT channel 2. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL2_DRV_A_STOP_STATE 0 + +// CHANNEL2 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL2 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for LP UT channel 2. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL2_DRV_B_START_STATE 0 + +// CHANNEL2 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for LP UT channel 2. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL2_DRV_B_STOP_STATE 0 + +// CHANNEL2 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL2 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_EVENT_AT_CREST 1 + +// CHANNEL2 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for LP UT channel 2. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL2_EVENT_AT_TROUGH 0 + +// CHANNEL2 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for LP UT channel 2. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL2_BUFFERING_TYPE 1 + +// CHANNEL2 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for LP UT channel 2. +// Default: ENABLE +#define RTE_LPUTIMER_CHANNEL2_BUFFER_OPERATION 1 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 2 capture mode. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL2_BUFFERING_TYPE_A 2 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 2 capture mode. +// Default: NO BUFFER +#define RTE_LPUTIMER_CHANNEL2_BUFFERING_TYPE_B 0 + +// CHANNEL2 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for LP UT channel 2. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL2_DUTY_CYCLE_ENABLE 0 + +// CHANNEL2 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for LP UT channel 2. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL2_DUTY_CYCLE_VALUE 0 +// LPUTIMER CHANNEL 2 +#endif /*RTE_LPUTIMER*/ + +// LPUTIMER (Low-Power Universal timer) [Driver_UTIMERLP] +// UTIMER (Universal Timer) + +// DAC (Digital to analog converter ) +// DAC0 (Digital to analog converter ) [Driver_DAC0] +// Configuration settings for Driver_DAC0 in component ::Drivers:DAC +#define RTE_DAC0 1 +#if RTE_DAC0 + +// DAC input through bypass mode +// <0=> DISABLE (DAC input data source through DAC_IN reg) +// <1=> ENABLE (DAC input data source through DAC_REG1 reg) +// Default: DISABLE +#define RTE_DAC0_INPUT_BYP_MUX_EN 0 + +// DAC converts two's complement to unsigned binary data +// DAC_out = (DAC_Input / 2^12) * Vref +// DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v +// 2^12 represents DAC supports 12 bit resolution. +// if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), +// DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). +// if dac_input > 2047 then, +// DAC_out = ((dac_input - 2047) / 2^12) *vref +// if dac_input < 2047 then, +// DAC_out = ((dac_input + 2047) / 2^12) *vref +// <0=> DISABLE(input will be positive) +// <1=> ENABLE (Input can be positive or negative) +// Default: DISABLE +#define RTE_DAC0_TWOSCOMP_EN 0 +#endif +// DAC0 (Digital to analog converter) [Driver_DAC0] + +// DAC1 (Digital to analog converter ) [Driver_DAC1] +// Configuration settings for Driver_DAC1 in component ::Drivers:DAC +#define RTE_DAC1 1 +#if RTE_DAC1 + +// DAC input through bypass mode +// <0=> DISABLE (DAC input data source through DAC_IN reg) +// <1=> ENABLE (DAC input data source through DAC_REG1 reg) +// Default: DISABLE +#define RTE_DAC1_INPUT_BYP_MUX_EN 0 + +// DAC converts two's complement to unsigned binary data +// DAC_out = (DAC_Input / 2^12) * Vref +// DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v +// 2^12 represents DAC supports 12 bit resolution. +// if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), +// DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). +// if dac_input > 2047 then, +// DAC_out = ((dac_input - 2047) / 2^12) *vref +// if dac_input < 2047 then, +// DAC_out = ((dac_input + 2047) / 2^12) *vref +// <0=> DISABLE(input will be positive) +// <1=> ENABLE (Input can be positive or negative) +// Default: DISABLE +#define RTE_DAC1_TWOSCOMP_EN 0 +#endif +// DAC1 (Digital to Analog converter) [Driver_DAC1] +// DAC(Digital to analog converter) + +// ADC (Analog to Digital Converter) +// ADC120 (Analog to Digital Converter 0) [Driver_ADC120] +// Configuration settings for Driver_ADC120 in component ::Drivers:ADC12 +#define RTE_ADC120 1 +#if RTE_ADC120 +#define RTE_ADC120_IRQ_PRIORITY 0 + +// ADC120 DONE0 IRQ PRIORITY <0-225> +// defines ADC120 done0 interrupt priority +// default: 0 +#define RTE_ADC120_DONE0_IRQ_PRIORITY 0 + +// ADC120 DONE1 IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_DONE1_IRQ_PRIORITY 0 + +// ADC120 CMPA IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_CMPA_IRQ_PRIORITY 0 + +// ADC120 CMPB IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC120_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC120_CLOCK_DIV (2) + +// Sample Width <2-32> +// Defines Width in divided clocks of the sample output signal +// Default: 16 +#define RTE_ADC120_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC120_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC120_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC120_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC120_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC120_DIFFERENTIAL_EN 0 + +// Enable PGA +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC120 PGA enable +// Default: DISABLE +#define RTE_ADC120_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC120_PGA_GAIN (0) +// RTE_ADC121_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC120_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC120_COMPARATOR_BIAS 2 + +#endif +// ADC120 (Analog to Digital Converter 0) [Driver_ADC120] + +// ADC121 (Analog to Digital Converter 1) [Driver_ADC121] +// Configuration settings for Driver_ADC121 in component ::Drivers:ADC +#define RTE_ADC121 1 +#if RTE_ADC121 + +// ADC121 DONE0 IRQ PRIORITY <0-225> +// defines ADC121 done0 interrupt priority +// default: 0 +#define RTE_ADC121_DONE0_IRQ_PRIORITY 0 + +// ADC121 DONE1 IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_DONE1_IRQ_PRIORITY 0 + +// ADC121 CMPA IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_CMPA_IRQ_PRIORITY 0 + +// ADC121 CMPB IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC121_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC121_CLOCK_DIV (2) + +// Sample Width <2-32> +// Defines Width in divided clocks of the sample output signal +// Default: 16 +#define RTE_ADC121_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC121_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC121_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC121_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC121_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC121_DIFFERENTIAL_EN 0 + +// Pga enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC121 using PGA gain +// Default: DISABLE +#define RTE_ADC121_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC121_PGA_GAIN (0) +// RTE_ADC121_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC121_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC121_COMPARATOR_BIAS 2 + +#endif +// ADC121 (Analog to Digital Converter 1) [Driver_ADC121] + +// ADC122 (Analog to Digital Converter 2) [Driver_ADC122] +// Configuration settings for Driver_ADC122 in component ::Drivers:ADC +#define RTE_ADC122 1 +#if RTE_ADC122 + +// ADC122 DONE0 IRQ PRIORITY <0-225> +// defines ADC122 done0 interrupt priority +// default: 0 +#define RTE_ADC122_DONE0_IRQ_PRIORITY 0 + +// ADC122 DONE1 IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_DONE1_IRQ_PRIORITY 0 + +// ADC122 CMPA IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_CMPA_IRQ_PRIORITY 0 + +// ADC122 CMPB IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC122_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC122_CLOCK_DIV (2) + +// Sample Width <2-32> +// defines Width in divided clocks of the sample output signal +// default: 16 +#define RTE_ADC122_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC122_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC122_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC122_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC122_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC122_DIFFERENTIAL_EN 0 + +// Enable PGA ADC122 +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC122 using PGA gain +// Default: DISABLE +#define RTE_ADC122_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC122_PGA_GAIN (0) +// RTE_ADC122_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC122_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC122_COMPARATOR_BIAS 2 + +#endif +// ADC122 (Analog to Digital Converter 2) [Driver_ADC122] + +// ADC24 (Analog to Digital Converter 0) [Driver_ADC24] +// Configuration settings for Driver_ADC24 in component ::Drivers:ADC +#define RTE_ADC24 1 +#if RTE_ADC24 + +// ADC24 DONE0 IRQ PRIORITY <0-225> +// defines ADC24 done0 interrupt priority +// default: 0 +#define RTE_ADC24_DONE0_IRQ_PRIORITY 0 + +// ADC24 DONE1 IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_DONE1_IRQ_PRIORITY 0 + +// ADC24 CMPA IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_CMPA_IRQ_PRIORITY 0 + +// ADC24 CMPB IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-4> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC24_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC24_CLOCK_DIV (2) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC24_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC24_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC24_SHIFT_LEFT_OR_RIGHT (1) + +// Ouput rate select +// <0=> 1 KS/s +// <1=> 2 KS/s +// <2=> 4 KS/s +// <3=> 8 KS/s +// <4=> 16 KS/s +// Defines Select adc24 output rate +// Default: 0 +#define RTE_ADC24_OUTPUT_RATE (0) + +// PGA enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable PGA to set PGA gain +// Default: DISABLE +#define RTE_ADC24_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC24_PGA_GAIN (0) + +// Bias Control +// <0=> 5 uA +// <1=> 6.25 uA +// <3=> 7.5 uA +// <7=> 8.75 uA +// Defines Bias control +// Default: 3 +#define RTE_ADC24_BIAS (3) + +#endif +// ADC24 (Analog to Digital Converter 0) [Driver_ADC24] +// ADC (Analog to Digital Converter) + +// CRC (Cyclic Redundancy Check) +// CRC0 (Cyclic Redundancy Check) [Driver_CRC0] +// Configuration settings for Driver_CRC0 in component ::Drivers:CRC +#define RTE_CRC0 1 +#if RTE_CRC0 + +// CRC0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for CRC0 +// Default: 0 +#define RTE_CRC0_DMA_ENABLE 0 +#if RTE_CRC0_DMA_ENABLE + +// CRC0 DMA Selection +// <0=> DMA0 +// <1=> DMA1 +// <2=> DMA2 +// Defines Select DMA for CRC0. By default DMA0 will be considered +// Default: 0 +#define RTE_CRC0_SELECT_DMA 0 +#endif + +// CRC0 DMA IRQ priority <0-255> +// Defines CRC0 DMA Interrupt priority +// Default: 0 +#define RTE_CRC0_DMA_IRQ_PRI 0 +#endif +// CRC0 (Cyclic Redundancy Check) [Driver_CRC0] + +// CRC1 (Cyclic Redundancy Check) [Driver_CRC1] +// Configuration settings for Driver_CRC1 in component ::Drivers:CRC +#define RTE_CRC1 1 +#if RTE_CRC1 + +// CRC1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for CRC1 +// Default: 0 +#define RTE_CRC1_DMA_ENABLE 0 +#if RTE_CRC1_DMA_ENABLE + +// CRC1 DMA Selection +// <0=> DMA0 +// <1=> DMA1 +// <2=> DMA2 +// Defines Select DMA for CRC1. By default DMA0 will be considered +// Default: 0 +#define RTE_CRC1_SELECT_DMA 0 +#endif + +// CRC1 DMA IRQ priority <0-255> +// Defines CRC1 DMA Interrupt priority +// Default: 0 +#define RTE_CRC1_DMA_IRQ_PRI 0 +#endif +// CRC1 (Cyclic Redundancy Check) [Driver_CRC1] +// + +// HWSEM (Hardware Semaphore) +// HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] +// Configuration settings for Driver_HWSEM0 in component ::Drivers:HWSEM +#define RTE_HWSEM0 1 +#if RTE_HWSEM0 + +// HWSEM0 IRQ priority <0-255> +// Defines HWSEM0 Interrupt priority +// Default: 0 +#define RTE_HWSEM0_IRQPRIORITY 0 +#endif + +// HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] + +// HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] +// Configuration settings for Driver_HWSEM1 in component ::Drivers:HWSEM +#define RTE_HWSEM1 0 +#if RTE_HWSEM1 + +// HWSEM1 IRQ priority <0-255> +// Defines HWSEM1 Interrupt priority +// Default: 0 +#define RTE_HWSEM1_IRQPRIORITY 0 +#endif + +// HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] + +// HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] +// Configuration settings for Driver_HWSEM2 in component ::Drivers:HWSEM +#define RTE_HWSEM2 0 +#if RTE_HWSEM2 + +// HWSEM2 IRQ priority <0-255> +// Defines HWSEM2 Interrupt priority +// Default: 0 +#define RTE_HWSEM2_IRQPRIORITY 0 +#endif + +// HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] + +// HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] +// Configuration settings for Driver_HWSEM3 in component ::Drivers:HWSEM +#define RTE_HWSEM3 0 +#if RTE_HWSEM3 + +// HWSEM3 IRQ priority <0-255> +// Defines HWSEM3 Interrupt priority +// Default: 0 +#define RTE_HWSEM3_IRQPRIORITY 0 +#endif + +// HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] + +// HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] +// Configuration settings for Driver_HWSEM4 in component ::Drivers:HWSEM +#define RTE_HWSEM4 0 +#if RTE_HWSEM4 + +// HWSEM4 IRQ priority <0-255> +// Defines HWSEM4 Interrupt priority +// Default: 0 +#define RTE_HWSEM4_IRQPRIORITY 0 +#endif + +// HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] + +// HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] +// Configuration settings for Driver_HWSEM5 in component ::Drivers:HWSEM +#define RTE_HWSEM5 0 +#if RTE_HWSEM5 + +// HWSEM5 IRQ priority <0-255> +// Defines HWSEM5 Interrupt priority +// Default: 0 +#define RTE_HWSEM5_IRQPRIORITY 0 +#endif + +// HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] + +// HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] +// Configuration settings for Driver_HWSEM6 in component ::Drivers:HWSEM +#define RTE_HWSEM6 0 +#if RTE_HWSEM6 + +// HWSEM6 IRQ priority <0-255> +// Defines HWSEM6 Interrupt priority +// Default: 0 +#define RTE_HWSEM6_IRQPRIORITY 0 +#endif + +// HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] + +// HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] +// Configuration settings for Driver_HWSEM7 in component ::Drivers:HWSEM +#define RTE_HWSEM7 0 +#if RTE_HWSEM7 + +// HWSEM7 IRQ priority <0-255> +// Defines HWSEM7 Interrupt priority +// Default: 0 +#define RTE_HWSEM7_IRQPRIORITY 0 +#endif + +// HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] + +// HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] +// Configuration settings for Driver_HWSEM8 in component ::Drivers:HWSEM +#define RTE_HWSEM8 0 +#if RTE_HWSEM8 + +// HWSEM8 IRQ priority <0-255> +// Defines HWSEM8 Interrupt priority +// Default: 0 +#define RTE_HWSEM8_IRQPRIORITY 0 +#endif + +// HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] + +// HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] +// Configuration settings for Driver_HWSEM9 in component ::Drivers:HWSEM +#define RTE_HWSEM9 0 +#if RTE_HWSEM9 + +// HWSEM9 IRQ priority <0-255> +// Defines HWSEM9 Interrupt priority +// Default: 0 +#define RTE_HWSEM9_IRQPRIORITY 0 +#endif + +// HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] + +// HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] +// Configuration settings for Driver_HWSEM10 in component ::Drivers:HWSEM +#define RTE_HWSEM10 0 +#if RTE_HWSEM10 + +// HWSEM10 IRQ priority <0-255> +// Defines HWSEM10 Interrupt priority +// Default: 0 +#define RTE_HWSEM10_IRQPRIORITY 0 +#endif + +// HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] + +// HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] +// Configuration settings for Driver_HWSEM11 in component ::Drivers:HWSEM +#define RTE_HWSEM11 0 +#if RTE_HWSEM11 + +// HWSEM11 IRQ priority <0-255> +// Defines HWSEM11 Interrupt priority +// Default: 0 +#define RTE_HWSEM11_IRQPRIORITY 0 +#endif + +// HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] + +// HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] +// Configuration settings for Driver_HWSEM12 in component ::Drivers:HWSEM +#define RTE_HWSEM12 0 +#if RTE_HWSEM12 + +// HWSEM12 IRQ priority <0-255> +// Defines HWSEM12 Interrupt priority +// Default: 0 +#define RTE_HWSEM12_IRQPRIORITY 0 +#endif + +// HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] + +// HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] +// Configuration settings for Driver_HWSEM13 in component ::Drivers:HWSEM +#define RTE_HWSEM13 0 +#if RTE_HWSEM13 + +// HWSEM13 IRQ priority <0-255> +// Defines HWSEM13 Interrupt priority +// Default: 0 +#define RTE_HWSEM13_IRQPRIORITY 0 +#endif + +// HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] + +// HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] +// Configuration settings for Driver_HWSEM14 in component ::Drivers:HWSEM +#define RTE_HWSEM14 0 +#if RTE_HWSEM14 + +// HWSEM14 IRQ priority <0-255> +// Defines HWSEM14 Interrupt priority +// Default: 0 +#define RTE_HWSEM14_IRQPRIORITY 0 +#endif + +// HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] + +// HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] +// Configuration settings for Driver_HWSEM15 in component ::Drivers:HWSEM +#define RTE_HWSEM15 0 +#if RTE_HWSEM15 + +// HWSEM15 IRQ priority <0-255> +// Defines HWSEM15 Interrupt priority +// Default: 0 +#define RTE_HWSEM15_IRQPRIORITY 0 +#endif + +// HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] +// + +// High speed Analog Comparator +// CMP0 (Analog Comparator ) [Driver_CMP0] +// Configuration settings for Driver_CMP0 in component ::Drivers:Comparator +#define RTE_HSCMP0 1 +#if RTE_HSCMP0 + +// CMP0 IRQ priority <0-255> +// Defines Interrupt priority for CMP0. +// Default: 0 +#define RTE_CMP0_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_0 +// <1=> PIN_P0_6 +// <2=> PIN_P1_4 +// <3=> PIN_P0_4 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_0; 01 = P0_6; 10 = P1_4; 11 = P0_4 +// Default : 0 +#define RTE_CMP0_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP0_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP0_SEL_HYSTERISIS 7 + +#endif +// CMP0 (Analog Comparator) [Driver_CMP0] + +// CMP1 (Analog Comparator ) [Driver_CMP1] +// Configuration settings for Driver_CMP1 in component ::Drivers:Comparator +#define RTE_HSCMP1 1 +#if RTE_HSCMP1 + +// CMP1 IRQ priority <0-255> +// Defines Interrupt priority for CMP1. +// Default: 0 +#define RTE_CMP1_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_1 +// <1=> PIN_P0_7 +// <2=> PIN_P1_5 +// <3=> PIN_P0_5 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_1; 01 = P0_7; 10 = P1_5; 11 = P0_5 +// Default : 0 +#define RTE_CMP1_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP1_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP1_SEL_HYSTERISIS 7 + +#endif +// CMP1 (Analog Comparator) [Driver_CMP1] + +// CMP2 (Analog Comparator ) [Driver_CMP2] +// Configuration settings for Driver_CMP2 in component ::Drivers:Comparator +#define RTE_HSCMP2 1 +#if RTE_HSCMP2 + +// CMP2 IRQ priority <0-255> +// Defines Interrupt priority for CMP2. +// Default: 0 +#define RTE_CMP2_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_2 +// <1=> PIN_P1_0 +// <2=> PIN_P1_6 +// <3=> PIN_P1_2 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_2; 01 = P1_0; 10 = P1_6; 11 = P1_2 +// Default : 0 +#define RTE_CMP2_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP2_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP2_SEL_HYSTERISIS 7 + +#endif +// CMP2 (Analog Comparator) [Driver_CMP2] + +// CMP3 (Analog Comparator ) [Driver_CMP3] +// Configuration settings for Driver_CMP3 in component ::Drivers:Comparator +#define RTE_HSCMP3 1 +#if RTE_HSCMP3 + +// CMP3 IRQ priority <0-255> +// Defines Interrupt priority for CMP3. +// Default: 0 +#define RTE_CMP3_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_3 +// <1=> PIN_P1_1 +// <2=> PIN_P1_7 +// <3=> PIN_P1_3 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_3; 01 = P1_1; 10 = P1_7; 11 = P1_3 +// Default : 0 +#define RTE_CMP3_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP3_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP3_SEL_HYSTERISIS 7 + +#endif +// CMP3 (Analog Comparator) [Driver_CMP3] + +#if defined(RTSS_HE) +// LPCMP (Low Power Analog Comparator) [Driver_LPCMP] +// Configuration settings for Driver_LPCMP in component ::Drivers:LPCMP +#define RTE_LPCMP 1 + +#if RTE_LPCMP + +// LPCMP IRQ priority <0-255> +// Defines Interrupt priority for LPCMP. +// Default: 0 +#define RTE_LPCMP_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P2_4 +// <1=> PIN_P2_5 +// <2=> PIN_P2_6 +// <3=> PIN_P2_7 +// Defines:select input to the positive terminal of LPCMP; +// 00 = P2_4; 01 = P2_5; 10 = P2_6; 11 = P2_7 +// Default : 0 +#define RTE_LPCMP_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> AON_VREF +// <1=> PIN_P2_0 +// <2=> PIN_P2_1 +// <3=> PIN_P2_2 +// Defines: select input to the negative terminal of LPCMP; +// 00 = AON Vref(0.8v); 01 = P2_0; 10 = P2_1 Vref; 11 = P2_2 +// Default : 0 +#define RTE_LPCMP_SEL_NEGATIVE 0 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select LPCMP hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_LPCMP_SEL_HYSTERISIS 7 + +#endif +// LPCMP (Low Power Analog Comparator) [Driver_LPCMP] +#endif // defined(RTSS_HE) +// CMP (Analog Comparator) + +// I2C (Inter Integrated Circuit) +// I2C (Inter Integrated Circuit) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#if RTE_I2C0 + +// I2C0 IRQ priority <0-255> +// Defines Interrupt priority for I2C0. +// Default: 0 +#define RTE_I2C0_IRQ_PRIORITY 0 +// I2C0 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C0. +// Default: 16 +#define RTE_I2C0_TX_FIFO_THRESHOLD 16 + +// I2C0 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C0. +// Default: 0 +#define RTE_I2C0_RX_FIFO_THRESHOLD 0 + +// I2C0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C0 +// Default: DISABLE +#define RTE_I2C0_DMA_ENABLE 0 +#if RTE_I2C0_DMA_ENABLE + +// I2C0 DMA IRQ priority <0-255> +// Defines I2C0 DMA Interrupt priority +// Default: 0 +#define RTE_I2C0_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C0] + +// I2C (Inter Integrated Circuit) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C + +#define RTE_I2C1 1 +#if RTE_I2C1 + +// I2C1 IRQ priority <0-255> +// Defines Interrupt priority for I2C1. +// Default: 0 +#define RTE_I2C1_IRQ_PRIORITY 0 +// I2C1 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C1. +// Default: 16 +#define RTE_I2C1_TX_FIFO_THRESHOLD 16 + +// I2C1 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C1. +// Default: 0 +#define RTE_I2C1_RX_FIFO_THRESHOLD 0 + +// I2C1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C1 +// Default: DISABLE +#define RTE_I2C1_DMA_ENABLE 0 +#if RTE_I2C1_DMA_ENABLE + +// I2C1 DMA IRQ priority <0-255> +// Defines I2C1 DMA Interrupt priority +// Default: 0 +#define RTE_I2C1_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C1] + +// I2C (Inter Integrated Circuit) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C + +#define RTE_I2C2 1 +#if RTE_I2C2 + +// I2C2 IRQ priority <0-255> +// Defines Interrupt priority for I2C2. +// Default: 0 +#define RTE_I2C2_IRQ_PRIORITY 0 +// I2C2 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C2. +// Default: 16 +#define RTE_I2C2_TX_FIFO_THRESHOLD 16 + +// I2C2 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C2. +// Default: 0 +#define RTE_I2C2_RX_FIFO_THRESHOLD 0 + +// I2C2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C2 +// Default: DISABLE +#define RTE_I2C2_DMA_ENABLE 0 +#if RTE_I2C2_DMA_ENABLE + +// I2C2 DMA IRQ priority <0-255> +// Defines I2C2 DMA Interrupt priority +// Default: 0 +#define RTE_I2C2_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C2] + +// I2C (Inter Integrated Circuit) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::Drivers:I2C + +#define RTE_I2C3 1 + +#if RTE_I2C3 + +// I2C3 IRQ priority <0-255> +// Defines Interrupt priority for I2C3. +// Default: 0 +#define RTE_I2C3_IRQ_PRIORITY 0 +// I2C3 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C3. +// Default: 16 +#define RTE_I2C3_TX_FIFO_THRESHOLD 16 + +// I2C3 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C3. +// Default: 0 +#define RTE_I2C3_RX_FIFO_THRESHOLD 0 + +// I2C3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C3 +// Default: DISABLE +#define RTE_I2C3_DMA_ENABLE 0 +#if RTE_I2C3_DMA_ENABLE + +// I2C3 DMA IRQ priority <0-255> +// Defines I2C3 DMA Interrupt priority +// Default: 0 +#define RTE_I2C3_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C3] + +// LPI2C0 (Low Power Inter-Integrated Circuit) [Driver_LPI2C0] +// Configuration settings for Driver_LPI2C0 in component ::Drivers:LPI2C +#if defined(RTSS_HE) +#define RTE_LPI2C0 1 +#if RTE_LPI2C0 + +// LPI2C0 IRQ PRIORITY <0-225> +// defines LPI2C0 interrupt priority +// default: 0 +#define RTE_LPI2C0_IRQ_PRIORITY 0 + +// LPI2C0 Bus-Speed <1-400000> +// defines LPI2C0 Bus-Speed - It is used for Bit-time calculation in driver +// default: 400KHz +#define RTE_LPI2C0_BUS_SPEED 400000 + +#endif +// LPI2C0(Low Power Inter-Integrated Circuit) [Driver_LPI2C0] + +// LPI2C (Low Power Inter Integrated Circuit) [Driver_LPI2C1] +// Configuration settings for Driver_LPI2C1 in component ::Drivers:LPI2C1 +#define RTE_LPI2C1 1 + +#if RTE_LPI2C1 + +// LPI2C1 IRQ priority <0-255> +// Defines Interrupt priority for LPI2C1. +// Default: 0 +#define RTE_LPI2C1_IRQ_PRIORITY 0 + +// LPI2C1 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for LPI2C1. +// Default: 16 +#define RTE_LPI2C1_TX_FIFO_THRESHOLD 16 + +// LPI2C1 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for LPI2C1. +// Default: 0 +#define RTE_LPI2C1_RX_FIFO_THRESHOLD 0 + +// LPI2C1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPI2C1 +// Default: DISABLE +#define RTE_LPI2C1_DMA_ENABLE 0 +#if RTE_LPI2C1_DMA_ENABLE + +// LPI2C1 DMA IRQ priority <0-255> +// Defines LPI2C1 DMA Interrupt priority +// Default: 0 +#define RTE_LPI2C1_DMA_IRQ_PRI 0 +#endif + +#endif +// LPI2C (Low Power Inter Integrated Circuit) [Driver_LPI2C1] +#endif // defined(RTSS_HE) +// I2C (Inter Integrated Circuit) + +// RANGE_SENSOR (Range Sensor) +// RANGE_SENSOR (Object Range Measurement Unit) [Driver_RANGE_SENSOR] +// Configuration settings for Driver_RANGE_SENSOR in component::Drivers:RANGE_SENSOR +#define RTE_RANGE_SENSOR 1 + +#if RTE_RANGE_SENSOR + +// CH201 (Time of Flight Sensor) [Driver_CH201] +// Configuration settings for Driver_CH201 in component::Drivers:CH201 +#define RTE_CH201 1 + +#if RTE_CH201 + +// CH201 I2C Bus speed range <0-400000> +// Defines CH201 I2C speed in Hertz +// Default: 400000 +#define RTE_CH201_I2C_SPEED_HZ 400000 + +// CH201 RTC calibration pulse range <1-1000> +// Defines CH201 sensor's internal RTC calculation pulse in millisec +// Default: 100 +#define RTE_CH201_RTC_CAL_PULSE_MS 100 + +// CH201 LPTIMER channel for Timeout trigger +// Defines LPTIMER's channel number for CH201 Timeout trigger +// <0=> LPTIMER_CHANNEL_0 +// <1=> LPTIMER_CHANNEL_1 +// <2=> LPTIMER_CHANNEL_2 +// <3=> LPTIMER_CHANNEL_3 +// Default: 1 +#define RTE_CH201_LPTIMER_CHANNEL 1 + +#endif +// CH201 (Time of Flight Sensor) [Driver_CH201] + +#endif +// RANGE_SENSOR (Object Range Measurement Unit) [Driver_RANGE_SENSOR] +// RANGE_SENSOR (Range Sensor) + +// DMA0 (Direct Memory Access Controller) [Driver_DMA0] +// Configuration settings for Driver_DMA0 in component ::Drivers:DMA +#define RTE_DMA0 1 +#if RTE_DMA0 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA0_APB_INTERFACE 0 +// DMA0 Abort interrupt priority <0-255> +// Defines DMA0 Abort interrupt priority. +// Default: 0 +#define RTE_DMA0_ABORT_IRQ_PRI 0 +// DMA0 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA0 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA0_BOOT_IRQ_NS_STATE 0 +// DMA0 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA0 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA0_BOOT_PERIPH_NS_STATE 0 +#endif +// DMA0 (Direct Memory Access Controller) [Driver_DMA0] + +// DMA1 (Direct Memory Access Controller) [Driver_DMA1] +#if defined(RTSS_HP) + +// Configuration settings for Driver_DMA1 in component ::Drivers:DMA +#define RTE_DMA1 1 +#if RTE_DMA1 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA1_APB_INTERFACE 0 +// DMA1 Abort interrupt priority <0-255> +// Defines DMA1 Abort interrupt priority. +// Default: 0 +#define RTE_DMA1_ABORT_IRQ_PRI 0 +// DMA1 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA1 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA1_BOOT_IRQ_NS_STATE 0 +// DMA1 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA1 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA1_BOOT_PERIPH_NS_STATE 0 +#endif + +#endif +// DMA1 (Direct Memory Access Controller) [Driver_DMA1] + +// DMA2 (Direct Memory Access Controller) [Driver_DMA2] +// Configuration settings for Driver_DMA2 in component ::Drivers:DMA +#if defined(RTSS_HE) + +#define RTE_DMA2 1 +#if RTE_DMA2 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA2_APB_INTERFACE 0 +// DMA2 Abort interrupt priority <0-255> +// Defines DMA2 Abort interrupt priority. +// Default: 0 +#define RTE_DMA2_ABORT_IRQ_PRI 0 +// DMA2 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA2 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA2_BOOT_IRQ_NS_STATE 0 +// DMA2 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA2 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA2_BOOT_PERIPH_NS_STATE 0 +#endif + +#endif +// DMA2 (Direct Memory Access Controller) [Driver_DMA2] + +// GPIO (general purpose input and output) +// GPIO0 +// Configuration settings for Driver_GPIO0 in component ::Drivers:GPIO +#define RTE_GPIO0 1 + +#if RTE_GPIO0 + +// GPIO0 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO0. +// Default: 1 +#define RTE_GPIO0_DB_CLK_DIV 1 + +// GPIO0 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO0. +// Default: DISABLED +#define RTE_GPIO0_BIT_MANIPULATION 0 + +// GPIO0_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN0. +// Default: 0 +#define RTE_GPIO0_PIN0_IRQ_PRIORITY 0 + +// GPIO0_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN1. +// Default: 0 +#define RTE_GPIO0_PIN1_IRQ_PRIORITY 0 + +// GPIO0_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN2. +// Default: 0 +#define RTE_GPIO0_PIN2_IRQ_PRIORITY 0 + +// GPIO0_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN3. +// Default: 0 +#define RTE_GPIO0_PIN3_IRQ_PRIORITY 0 + +// GPIO0_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN4. +// Default: 0 +#define RTE_GPIO0_PIN4_IRQ_PRIORITY 0 + +// GPIO0_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN5. +// Default: 0 +#define RTE_GPIO0_PIN5_IRQ_PRIORITY 0 + +// GPIO0_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN6. +// Default: 0 +#define RTE_GPIO0_PIN6_IRQ_PRIORITY 0 + +// GPIO0_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN7. +// Default: 0 +#define RTE_GPIO0_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO0 + +// GPIO1 +// Configuration settings for Driver_GPIO1 in component ::Drivers:GPIO +#define RTE_GPIO1 1 + +#if RTE_GPIO1 + +// GPIO1 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO1. +// Default: 1 +#define RTE_GPIO1_DB_CLK_DIV 1 + +// GPIO1 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO1. +// Default: DISABLED +#define RTE_GPIO1_BIT_MANIPULATION 0 + +// GPIO1_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN0. +// Default: 0 +#define RTE_GPIO1_PIN0_IRQ_PRIORITY 0 + +// GPIO1_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN1. +// Default: 0 +#define RTE_GPIO1_PIN1_IRQ_PRIORITY 0 + +// GPIO1_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN2. +// Default: 0 +#define RTE_GPIO1_PIN2_IRQ_PRIORITY 0 + +// GPIO1_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN3. +// Default: 0 +#define RTE_GPIO1_PIN3_IRQ_PRIORITY 0 + +// GPIO1_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN4. +// Default: 0 +#define RTE_GPIO1_PIN4_IRQ_PRIORITY 0 + +// GPIO1_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN5. +// Default: 0 +#define RTE_GPIO1_PIN5_IRQ_PRIORITY 0 + +// GPIO1_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN6. +// Default: 0 +#define RTE_GPIO1_PIN6_IRQ_PRIORITY 0 + +// GPIO1_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN7. +// Default: 0 +#define RTE_GPIO1_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO1 + +// GPIO2 +// Configuration settings for Driver_GPIO2 in component ::Drivers:GPIO +#define RTE_GPIO2 1 + +#if RTE_GPIO2 + +// GPIO2 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO2. +// Default: 1 +#define RTE_GPIO2_DB_CLK_DIV 1 + +// GPIO2 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO2. +// Default: DISABLED +#define RTE_GPIO2_BIT_MANIPULATION 0 + +// GPIO2_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN0. +// Default: 0 +#define RTE_GPIO2_PIN0_IRQ_PRIORITY 0 + +// GPIO2_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN1. +// Default: 0 +#define RTE_GPIO2_PIN1_IRQ_PRIORITY 0 + +// GPIO2_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN2. +// Default: 0 +#define RTE_GPIO2_PIN2_IRQ_PRIORITY 0 + +// GPIO2_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN3. +// Default: 0 +#define RTE_GPIO2_PIN3_IRQ_PRIORITY 0 + +// GPIO2_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN4. +// Default: 0 +#define RTE_GPIO2_PIN4_IRQ_PRIORITY 0 + +// GPIO2_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN5. +// Default: 0 +#define RTE_GPIO2_PIN5_IRQ_PRIORITY 0 + +// GPIO2_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN6. +// Default: 0 +#define RTE_GPIO2_PIN6_IRQ_PRIORITY 0 + +// GPIO2_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN7. +// Default: 0 +#define RTE_GPIO2_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO2 + +// GPIO3 +// Configuration settings for Driver_GPIO3 in component ::Drivers:GPIO +#define RTE_GPIO3 1 + +#if RTE_GPIO3 + +// GPIO3 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO3. +// Default: 1 +#define RTE_GPIO3_DB_CLK_DIV 1 + +// GPIO3 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO3. +// Default: DISABLED +#define RTE_GPIO3_BIT_MANIPULATION 0 + +// GPIO3_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN0. +// Default: 0 +#define RTE_GPIO3_PIN0_IRQ_PRIORITY 0 + +// GPIO3_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN1. +// Default: 0 +#define RTE_GPIO3_PIN1_IRQ_PRIORITY 0 + +// GPIO3_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN2. +// Default: 0 +#define RTE_GPIO3_PIN2_IRQ_PRIORITY 0 + +// GPIO3_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN3. +// Default: 0 +#define RTE_GPIO3_PIN3_IRQ_PRIORITY 0 + +// GPIO3_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN4. +// Default: 0 +#define RTE_GPIO3_PIN4_IRQ_PRIORITY 0 + +// GPIO3_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN5. +// Default: 0 +#define RTE_GPIO3_PIN5_IRQ_PRIORITY 0 + +// GPIO3_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN6. +// Default: 0 +#define RTE_GPIO3_PIN6_IRQ_PRIORITY 0 + +// GPIO3_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN7. +// Default: 0 +#define RTE_GPIO3_PIN7_IRQ_PRIORITY 0 + +// GPIO3_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO3 + +// GPIO4 +// Configuration settings for Driver_GPIO4 in component ::Drivers:GPIO +#define RTE_GPIO4 1 + +#if RTE_GPIO4 + +// GPIO4 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO4. +// Default: 1 +#define RTE_GPIO4_DB_CLK_DIV 1 + +// GPIO4 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO4. +// Default: DISABLED +#define RTE_GPIO4_BIT_MANIPULATION 0 + +// GPIO4_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN0. +// Default: 0 +#define RTE_GPIO4_PIN0_IRQ_PRIORITY 0 + +// GPIO4_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN1. +// Default: 0 +#define RTE_GPIO4_PIN1_IRQ_PRIORITY 0 + +// GPIO4_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN2. +// Default: 0 +#define RTE_GPIO4_PIN2_IRQ_PRIORITY 0 + +// GPIO4_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN3. +// Default: 0 +#define RTE_GPIO4_PIN3_IRQ_PRIORITY 0 + +// GPIO4_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN4. +// Default: 0 +#define RTE_GPIO4_PIN4_IRQ_PRIORITY 0 + +// GPIO4_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN5. +// Default: 0 +#define RTE_GPIO4_PIN5_IRQ_PRIORITY 0 + +// GPIO4_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN6. +// Default: 0 +#define RTE_GPIO4_PIN6_IRQ_PRIORITY 0 + +// GPIO4_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN7. +// Default: 0 +#define RTE_GPIO4_PIN7_IRQ_PRIORITY 0 + +// GPIO4_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN7_DMA_GLITCH_FILTER_ENABLE 0 + +#endif +// GPIO4 + +// GPIO5 +// Configuration settings for Driver_GPIO5 in component ::Drivers:GPIO +#define RTE_GPIO5 1 + +#if RTE_GPIO5 + +// GPIO5 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO5. +// Default: 1 +#define RTE_GPIO5_DB_CLK_DIV 1 + +// GPIO5 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO5. +// Default: DISABLED +#define RTE_GPIO5_BIT_MANIPULATION 0 + +// GPIO5_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN0. +// Default: 0 +#define RTE_GPIO5_PIN0_IRQ_PRIORITY 0 + +// GPIO5_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN1. +// Default: 0 +#define RTE_GPIO5_PIN1_IRQ_PRIORITY 0 + +// GPIO5_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN2. +// Default: 0 +#define RTE_GPIO5_PIN2_IRQ_PRIORITY 0 + +// GPIO5_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN3. +// Default: 0 +#define RTE_GPIO5_PIN3_IRQ_PRIORITY 0 + +// GPIO5_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN4. +// Default: 0 +#define RTE_GPIO5_PIN4_IRQ_PRIORITY 0 + +// GPIO5_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN5. +// Default: 0 +#define RTE_GPIO5_PIN5_IRQ_PRIORITY 0 + +// GPIO5_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN6. +// Default: 0 +#define RTE_GPIO5_PIN6_IRQ_PRIORITY 0 + +// GPIO5_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN7. +// Default: 0 +#define RTE_GPIO5_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO5 + +// GPIO6 +// Configuration settings for Driver_GPIO6 in component ::Drivers:GPIO +#define RTE_GPIO6 1 + +#if RTE_GPIO6 + +// GPIO6 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO6. +// Default: 1 +#define RTE_GPIO6_DB_CLK_DIV 1 + +// GPIO6 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO6. +// Default: DISABLED +#define RTE_GPIO6_BIT_MANIPULATION 0 + +// GPIO6_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN0. +// Default: 0 +#define RTE_GPIO6_PIN0_IRQ_PRIORITY 0 + +// GPIO6_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN1. +// Default: 0 +#define RTE_GPIO6_PIN1_IRQ_PRIORITY 0 + +// GPIO6_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN2. +// Default: 0 +#define RTE_GPIO6_PIN2_IRQ_PRIORITY 0 + +// GPIO6_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN3. +// Default: 0 +#define RTE_GPIO6_PIN3_IRQ_PRIORITY 0 + +// GPIO6_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN4. +// Default: 0 +#define RTE_GPIO6_PIN4_IRQ_PRIORITY 0 + +// GPIO6_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN5. +// Default: 0 +#define RTE_GPIO6_PIN5_IRQ_PRIORITY 0 + +// GPIO6_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN6. +// Default: 0 +#define RTE_GPIO6_PIN6_IRQ_PRIORITY 0 + +// GPIO6_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN7. +// Default: 0 +#define RTE_GPIO6_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO6 + +// GPIO7 +// Configuration settings for Driver_GPIO7 in component ::Drivers:GPIO +#define RTE_GPIO7 1 + +#if RTE_GPIO7 + +// GPIO7 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO7. +// Default: 1 +#define RTE_GPIO7_DB_CLK_DIV 1 + +// GPIO7 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO7. +// Default: DISABLED +#define RTE_GPIO7_BIT_MANIPULATION 0 + +// GPIO7_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN0. +// Default: 0 +#define RTE_GPIO7_PIN0_IRQ_PRIORITY 0 + +// GPIO7_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN1. +// Default: 0 +#define RTE_GPIO7_PIN1_IRQ_PRIORITY 0 + +// GPIO7_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN2. +// Default: 0 +#define RTE_GPIO7_PIN2_IRQ_PRIORITY 0 + +// GPIO7_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN3. +// Default: 0 +#define RTE_GPIO7_PIN3_IRQ_PRIORITY 0 + +// GPIO7_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN4. +// Default: 0 +#define RTE_GPIO7_PIN4_IRQ_PRIORITY 0 + +// GPIO7_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN5. +// Default: 0 +#define RTE_GPIO7_PIN5_IRQ_PRIORITY 0 + +// GPIO7_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN6. +// Default: 0 +#define RTE_GPIO7_PIN6_IRQ_PRIORITY 0 + +// GPIO7_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN7. +// Default: 0 +#define RTE_GPIO7_PIN7_IRQ_PRIORITY 0 + +// GPIO7_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO7 + +// GPIO8 +// Configuration settings for Driver_GPIO8 in component ::Drivers:GPIO +#define RTE_GPIO8 1 + +#if RTE_GPIO8 + +// GPIO8 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO8. +// Default: 1 +#define RTE_GPIO8_DB_CLK_DIV 1 + +// GPIO8 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO8. +// Default: DISABLED +#define RTE_GPIO8_BIT_MANIPULATION 0 + +// GPIO8_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN0. +// Default: 0 +#define RTE_GPIO8_PIN0_IRQ_PRIORITY 0 + +// GPIO8_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN1. +// Default: 0 +#define RTE_GPIO8_PIN1_IRQ_PRIORITY 0 + +// GPIO8_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN2. +// Default: 0 +#define RTE_GPIO8_PIN2_IRQ_PRIORITY 0 + +// GPIO8_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN3. +// Default: 0 +#define RTE_GPIO8_PIN3_IRQ_PRIORITY 0 + +// GPIO8_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN4. +// Default: 0 +#define RTE_GPIO8_PIN4_IRQ_PRIORITY 0 + +// GPIO8_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN5. +// Default: 0 +#define RTE_GPIO8_PIN5_IRQ_PRIORITY 0 + +// GPIO8_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN6. +// Default: 0 +#define RTE_GPIO8_PIN6_IRQ_PRIORITY 0 + +// GPIO8_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN7. +// Default: 0 +#define RTE_GPIO8_PIN7_IRQ_PRIORITY 0 + +// GPIO8_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO8 + +// GPIO9 +// Configuration settings for Driver_GPIO9 in component ::Drivers:GPIO +#define RTE_GPIO9 1 + +#if RTE_GPIO9 + +// GPIO9 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO9. +// Default: 1 +#define RTE_GPIO9_DB_CLK_DIV 1 + +// GPIO9 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO9. +// Default: DISABLED +#define RTE_GPIO9_BIT_MANIPULATION 0 + +// GPIO9_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN0. +// Default: 0 +#define RTE_GPIO9_PIN0_IRQ_PRIORITY 0 + +// GPIO9_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN1. +// Default: 0 +#define RTE_GPIO9_PIN1_IRQ_PRIORITY 0 + +// GPIO9_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN2. +// Default: 0 +#define RTE_GPIO9_PIN2_IRQ_PRIORITY 0 + +// GPIO9_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN3. +// Default: 0 +#define RTE_GPIO9_PIN3_IRQ_PRIORITY 0 + +// GPIO9_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN4. +// Default: 0 +#define RTE_GPIO9_PIN4_IRQ_PRIORITY 0 + +// GPIO9_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN5. +// Default: 0 +#define RTE_GPIO9_PIN5_IRQ_PRIORITY 0 + +// GPIO9_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN6. +// Default: 0 +#define RTE_GPIO9_PIN6_IRQ_PRIORITY 0 + +// GPIO9_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN7. +// Default: 0 +#define RTE_GPIO9_PIN7_IRQ_PRIORITY 0 + +// GPIO9_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO9 + +// GPIO10 +// Configuration settings for Driver_GPIO10 in component ::Drivers:GPIO +#define RTE_GPIO10 1 + +#if RTE_GPIO10 + +// GPIO10 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO10. +// Default: 1 +#define RTE_GPIO10_DB_CLK_DIV 1 + +// GPIO10 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO10. +// Default: DISABLED +#define RTE_GPIO10_BIT_MANIPULATION 0 + +// GPIO10_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN0. +// Default: 0 +#define RTE_GPIO10_PIN0_IRQ_PRIORITY 0 + +// GPIO10_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN1. +// Default: 0 +#define RTE_GPIO10_PIN1_IRQ_PRIORITY 0 + +// GPIO10_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN2. +// Default: 0 +#define RTE_GPIO10_PIN2_IRQ_PRIORITY 0 + +// GPIO10_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN3. +// Default: 0 +#define RTE_GPIO10_PIN3_IRQ_PRIORITY 0 + +// GPIO10_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN4. +// Default: 0 +#define RTE_GPIO10_PIN4_IRQ_PRIORITY 0 + +// GPIO10_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN5. +// Default: 0 +#define RTE_GPIO10_PIN5_IRQ_PRIORITY 0 + +// GPIO10_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN6. +// Default: 0 +#define RTE_GPIO10_PIN6_IRQ_PRIORITY 0 + +// GPIO10_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN7. +// Default: 0 +#define RTE_GPIO10_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO10 + +// GPIO11 +// Configuration settings for Driver_GPIO11 in component ::Drivers:GPIO +#define RTE_GPIO11 1 + +#if RTE_GPIO11 + +// GPIO11 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO11. +// Default: 1 +#define RTE_GPIO11_DB_CLK_DIV 1 + +// GPIO11 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO11. +// Default: DISABLED +#define RTE_GPIO11_BIT_MANIPULATION 0 + +// GPIO11_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN0. +// Default: 0 +#define RTE_GPIO11_PIN0_IRQ_PRIORITY 0 + +// GPIO11_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN1. +// Default: 0 +#define RTE_GPIO11_PIN1_IRQ_PRIORITY 0 + +// GPIO11_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN2. +// Default: 0 +#define RTE_GPIO11_PIN2_IRQ_PRIORITY 0 + +// GPIO11_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN3. +// Default: 0 +#define RTE_GPIO11_PIN3_IRQ_PRIORITY 0 + +// GPIO11_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN4. +// Default: 0 +#define RTE_GPIO11_PIN4_IRQ_PRIORITY 0 + +// GPIO11_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN5. +// Default: 0 +#define RTE_GPIO11_PIN5_IRQ_PRIORITY 0 + +// GPIO11_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN6. +// Default: 0 +#define RTE_GPIO11_PIN6_IRQ_PRIORITY 0 + +// GPIO11_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN7. +// Default: 0 +#define RTE_GPIO11_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO11 + +// GPIO12 +// Configuration settings for Driver_GPIO12 in component ::Drivers:GPIO +#define RTE_GPIO12 1 + +#if RTE_GPIO12 + +// GPIO12 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO12. +// Default: 1 +#define RTE_GPIO12_DB_CLK_DIV 1 + +// GPIO12 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO12. +// Default: DISABLED +#define RTE_GPIO12_BIT_MANIPULATION 0 + +// GPIO12_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN0. +// Default: 0 +#define RTE_GPIO12_PIN0_IRQ_PRIORITY 0 + +// GPIO12_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN1. +// Default: 0 +#define RTE_GPIO12_PIN1_IRQ_PRIORITY 0 + +// GPIO12_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN2. +// Default: 0 +#define RTE_GPIO12_PIN2_IRQ_PRIORITY 0 + +// GPIO12_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN3. +// Default: 0 +#define RTE_GPIO12_PIN3_IRQ_PRIORITY 0 + +// GPIO12_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN4. +// Default: 0 +#define RTE_GPIO12_PIN4_IRQ_PRIORITY 0 + +// GPIO12_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN5. +// Default: 0 +#define RTE_GPIO12_PIN5_IRQ_PRIORITY 0 + +// GPIO12_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN6. +// Default: 0 +#define RTE_GPIO12_PIN6_IRQ_PRIORITY 0 + +// GPIO12_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN7. +// Default: 0 +#define RTE_GPIO12_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO12 + +// GPIO13 +// Configuration settings for Driver_GPIO13 in component ::Drivers:GPIO +#define RTE_GPIO13 1 + +#if RTE_GPIO13 + +// GPIO13 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO13. +// Default: 1 +#define RTE_GPIO13_DB_CLK_DIV 1 + +// GPIO13_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN0. +// Default: 0 +#define RTE_GPIO13_PIN0_IRQ_PRIORITY 0 + +// GPIO13 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO13. +// Default: DISABLED +#define RTE_GPIO13_BIT_MANIPULATION 0 + +// GPIO13_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN1. +// Default: 0 +#define RTE_GPIO13_PIN1_IRQ_PRIORITY 0 + +// GPIO13_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN2. +// Default: 0 +#define RTE_GPIO13_PIN2_IRQ_PRIORITY 0 + +// GPIO13_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN3. +// Default: 0 +#define RTE_GPIO13_PIN3_IRQ_PRIORITY 0 + +// GPIO13_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN4. +// Default: 0 +#define RTE_GPIO13_PIN4_IRQ_PRIORITY 0 + +// GPIO13_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN5. +// Default: 0 +#define RTE_GPIO13_PIN5_IRQ_PRIORITY 0 + +// GPIO13_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN6. +// Default: 0 +#define RTE_GPIO13_PIN6_IRQ_PRIORITY 0 + +// GPIO13_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN7. +// Default: 0 +#define RTE_GPIO13_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO13 + +// GPIO14 +// Configuration settings for Driver_GPIO14 in component ::Drivers:GPIO +#define RTE_GPIO14 1 + +#if RTE_GPIO14 + +// GPIO14 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO14. +// Default: 1 +#define RTE_GPIO14_DB_CLK_DIV 1 + +// GPIO14_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN0. +// Default: 0 +#define RTE_GPIO14_PIN0_IRQ_PRIORITY 0 + +// GPIO14 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO14. +// Default: DISABLED +#define RTE_GPIO14_BIT_MANIPULATION 0 + +// GPIO14_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN1. +// Default: 0 +#define RTE_GPIO14_PIN1_IRQ_PRIORITY 0 + +// GPIO14_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN2. +// Default: 0 +#define RTE_GPIO14_PIN2_IRQ_PRIORITY 0 + +// GPIO14_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN3. +// Default: 0 +#define RTE_GPIO14_PIN3_IRQ_PRIORITY 0 + +// GPIO14_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN4. +// Default: 0 +#define RTE_GPIO14_PIN4_IRQ_PRIORITY 0 + +// GPIO14_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN5. +// Default: 0 +#define RTE_GPIO14_PIN5_IRQ_PRIORITY 0 + +// GPIO14_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN6. +// Default: 0 +#define RTE_GPIO14_PIN6_IRQ_PRIORITY 0 + +// GPIO14_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN7. +// Default: 0 +#define RTE_GPIO14_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO14 + +// GPIO16 +// Configuration settings for Driver_GPIO16 in component ::Drivers:GPIO +#define RTE_GPIO16 1 + +#if RTE_GPIO16 + +// GPIO16 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO16. +// Default: DISABLED +#define RTE_GPIO16_BIT_MANIPULATION 0 + +// GPIO16 IRQ Priority +// Defines Interrupt priority for GPIO16 +// Default: 0 +#define RTE_GPIO16_IRQ_PRIORITY 0 +#endif +// GPIO16 + +// GPIO17 +// Configuration settings for Driver_GPIO17 in component ::Drivers:GPIO +#define RTE_GPIO17 1 +#if RTE_GPIO17 + +// GPIO17 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO17. +// Default: DISABLED +#define RTE_GPIO17_BIT_MANIPULATION 0 + +// GPIO17 IRQ Priority +// Defines Interrupt priority for GPIO17 +// Default: 0 +#define RTE_GPIO17_IRQ_PRIORITY 0 +#endif +// GPIO17 + +// LPGPIO +// Configuration settings for Driver_LPGPIO in component ::Drivers:GPIO +#define RTE_LPGPIO 1 + +#if RTE_LPGPIO + +// LPGPIO Fast mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Fast mode +// Default: DISABLE +#define RTE_LPGPIO_FAST_MODE_ENABLE 0 + +// LPGPIO_PIN0 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN0. +// Default: 0 +#define RTE_LPGPIO_PIN0_IRQ_PRIORITY 0 + +// LPGPIO_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN1 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN1. +// Default: 0 +#define RTE_LPGPIO_PIN1_IRQ_PRIORITY 0 + +// LPGPIO_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN2 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN2. +// Default: 0 +#define RTE_LPGPIO_PIN2_IRQ_PRIORITY 0 + +// LPGPIO_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN3 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN3. +// Default: 0 +#define RTE_LPGPIO_PIN3_IRQ_PRIORITY 0 + +// LPGPIO_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN4 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN4. +// Default: 0 +#define RTE_LPGPIO_PIN4_IRQ_PRIORITY 0 + +// LPGPIO_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN5 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN5. +// Default: 0 +#define RTE_LPGPIO_PIN5_IRQ_PRIORITY 0 + +// LPGPIO_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN6 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN6. +// Default: 0 +#define RTE_LPGPIO_PIN6_IRQ_PRIORITY 0 + +// LPGPIO_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN7 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN7. +// Default: 0 +#define RTE_LPGPIO_PIN7_IRQ_PRIORITY 0 + +// LPGPIO_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN7_DMA_GLITCH_FILTER_ENABLE 0 + +#endif +// LPGPIO + +// GPIO (general purpose input and output) + +// PDM(Pulse Density Modulation) +// PDM (Pulse density modulation) [Driver_PDM] +// Configuration settings for Driver_PDM in component ::Drivers:PDM +#define RTE_PDM 1 +#if RTE_PDM + +// PDM DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for PDM +// Default: ENABLE +#define RTE_PDM_DMA_ENABLE 0 + +// PDM DMA IRQ priority <0-255> +// Defines PDM DMA Interrupt priority +// Default: 0 +#define RTE_PDM_DMA_IRQ_PRIORITY 0 + +// PDM IRQ priority <0-255> +// Defines Interrupt priority for PDM. +// Default: 0 +#define RTE_PDM_IRQ_PRIORITY 0 + +// PDM Fifo watermark <0-7> +// Defines number of PCM samples in the internal FIFO +// Default: 5 +#define RTE_PDM_FIFO_WATERMARK 5 + +#endif +// PDM (Pulse density modulation) [Driver_PDM] + +// PDM (Pulse density modulation) + +#if defined(RTSS_HE) +// LPPDM(Low Power Pulse Density Modulation) +// LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] +// Configuration settings for Driver_LPPDM in component ::Drivers:LPPDM +#define RTE_LPPDM 1 + +#if RTE_LPPDM + +// LPPDM IRQ priority <0-255> +// Defines Interrupt priority for LPPDM. +// Default: 0 +#define RTE_LPPDM_IRQ_PRIORITY 0 + +// LPPDM Fifo watermark <0-7> +// Defines number of PCM samples in the internal FIFO +// Default: 5 +#define RTE_LPPDM_FIFO_WATERMARK 5 + +// LPPDM DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPPDM +// Default: ENABLE +#define RTE_LPPDM_DMA_ENABLE 0 +#if RTE_LPPDM_DMA_ENABLE + +// LPPDM DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPPDM. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPPDM_SELECT_DMA0 0 + +// PDM DMA IRQ priority <0-255> +// Defines PDM DMA Interrupt priority +// Default: 0 +#define RTE_LPPDM_DMA_IRQ_PRIORITY 0 +#endif +#endif +// LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] +#endif // defined(RTSS_HE) +// LPPDM (Low Power Pulse density modulation) + +// CANFD (Controller Area Network - Fast Mode) +// CANFD0 (Controller Area Network - Fast Mode Interface) [Driver_CANFD0] +// Configuration settings for Driver_CANFD0 in component ::Drivers:CANFD +#define RTE_CANFD0 1 + +#if RTE_CANFD0 + +// CANFD0 IRQ priority <0-255> +// Defines Interrupt priority for CANFD0. +// Default: 0 +#define RTE_CANFD0_IRQ_PRIORITY 0 + +// CANFD0 Clock Source +// <0=> 38.4 MHz Clock +// <1=> 160 MHz Clock +// Defines Clock Source for CANFD0. +// Default: 160 MHz +#define RTE_CANFD0_CLK_SOURCE 1 + +// CANFD0 Clock Speed (Hz) <160000-80000000> +// Defines Clock Speed for CANFD0. +// Maximum Clock speed is 80MHz +// Recommended speeds with 160MHz clock source: 20MHz, 40MHz, 80MHz +// Default: 20MHz +#define RTE_CANFD0_CLK_SPEED 20000000 + +// CANFD0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for CANFD0 +// Default: DISABLE +#define RTE_CANFD0_BLOCKING_MODE_ENABLE 0 + +#endif +// CANFD0 (Controller Area Network - Fast Mode Interface) [Driver_CANFD0] +// CANFD (Controller Area Network - Fast Mode) + +// SDC (Secure Digital Controller) +// SDC (Secure Digital Controller 0) [Driver_SDC0] +// Configuration settings for Driver_SDC0 in component ::Drivers:SDC +#define RTE_SDC 1 + +#if RTE_SDC + +// SDC BUS WIDTH SELECT +// <0=> BUS_WIDTH_1BIT +// <1=> BUS_WIDTH_4BIT +// Defines SDC0 size of bus width +// Default: BUS_WIDTH_4BIT +#define RTE_SDC_BUS_WIDTH 1 + +// SDC CLOCK SELECT +// <0=> SDC_12_5MHz +// <1=> SDC_25MHz +// <2=> SDC_50MHz +// Defines SDC0 Clock select +// Default: 25MHz +#define RTE_SDC_CLOCK_SELECT 1 + +// SDC DMA SELECT +// <0=> SDMA +// <1=> ADMA2 +// Defines SDC0 DMA select +// Default: ADMA2 +#define RTE_SDC_DMA_SELECT 1 + +// SDC IRQ MODE SELECT +// <0=> Polling Mode +// <1=> IRQ Mode +// Defines SDC IRQ MODE select +// Default: IRQ MODE +#define RTE_SDC_IRQ_MODE_SELECT 1 + +// SDC IRQ priority <0-255> +// Defines SDC Interrupt priority +// Default: 0 +#define RTE_SDC_IRQ_PRI 0 + +// SDC WAKEUP IRQ priority <0-255> +// Defines SDC Wakeup Interrupt priority +// Default: 0 +#define RTE_SDC_WAKEUP_IRQ_PRI 0 + +#endif +// SDC0 (Secure Digital Controller 0) [Driver_SDC0] +// SDC (Secure Digital Controller) + +// ETH_MAC (Ethernet MAC) +// ETH_MAC (Ethernet MAC) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:ETH_MAC +#define RTE_ETH_MAC 1 + +#if RTE_ETH_MAC + +// ETH MAC IRQ priority <0-255> +// Defines ETH MAC Interrupt priority +// Default: 0 +#define RTE_ETH_MAC_IRQ_PRIORITY 0 + +#endif +// ETH (Ethernet MAC) [Driver_ETH_MAC0] +// ETH (Ethernet MAC) + +// Power Management (PM) +// Handle Spurious Wakeup +// <0=> Disable +// <1=> Enable +// define Handle Spurious Wakeup +// default: Enable +#define PM_HANDLE_SPURIOUS_WAKEUP 1 +// Power Management (PM) + +#endif /* __RTE_DEVICE_H */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.2.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.2.0 new file mode 100644 index 00000000..e05adf05 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/RTE_Device.h.base@2.2.0 @@ -0,0 +1,10936 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + +// MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] +// Configuration settings for Driver_MRAM in component ::Drivers:MRAM +#define RTE_MRAM 1 +// MRAM (NVM (Non-Volatile Memory)) [Driver_MRAM] + +// CPI (Camera) [Driver_CPI] +// Configuration settings for Driver_CPI in component ::Drivers:CPI +#define RTE_CPI 1 +#if RTE_CPI + +// CPI interrupt priority <0-255> +// Defines CPI interrupt priority. +// Default: 0 +#define RTE_CPI_IRQ_PRI 0 + +// CPI CSI halt enable/disable +// <0=> disable +// <1=> enable +// Defines CPI CSI halt enable/disable. +// Default: 0 +#define RTE_CPI_CSI_HALT 0 + +// Select CPI AXI port +// <0=> disable +// <1=> enable +// Defines CPI AXI port +// Default: AXI port enable +#define RTE_CPI_AXI_PORT 0 + +// Select CPI ISP port +// <0=> disable +// <1=> enable +// Defines CPI ISP port +// Default: ISP port disable +#define RTE_CPI_ISP_PORT 1 + +// CPI Row roundup +// <0=> disable +// <1=> enable +// Defines CPI row roundup to 64 bit. +// Default: 0 +#define RTE_CPI_ROW_ROUNDUP 0 + +// CPI FIFO read watermark +// Defines FIFO read watermark. +// Default: 0x8 +#define RTE_CPI_FIFO_READ_WATERMARK 0x8 + +// CPI FIFO write watermark +// Defines CPI FIFO write watermark. +// Default: 0x18 +#define RTE_CPI_FIFO_WRITE_WATERMARK 0x18 + +// CPI horizontal back porch +// Defines CPI horizontal back porch. +// Default: 0x0 +#define RTE_CPI_HBP 0 + +// CPI horizontal front porch +// Defines CPI horizontal front porch. +// Default: 0x0 +#define RTE_CPI_HFP 0 + +// CPI horizontal cropping +// <0=> disable +// <1=> enable +// Defines CPI horizontal cropping +// Default: 0x1 +#define RTE_CPI_HFP_EN 0 + +// CPI vertical back porch +// Defines CPI vertical back porch. +// Default: 0x0 +#define RTE_CPI_VBP 0 + +// CPI vertical front porch +// Defines CPI vertical front porch. +// Default: 0x0 +#define RTE_CPI_VFP 0 + +// CPI vertical cropping +// <0=> disable +// <1=> enable +// Defines CPI vertical cropping +// Default: 0x1 +#define RTE_CPI_VFP_EN 0 + +// CPI number of active framebuffers +// Defines CPI number of active framebuffers +// Default: 2 +#define RTE_CPI_NUM_ACTIVE_FRAMEBUFFERS 2 + +// Enable CPI streaming +// <0=> Disable +// <1=> Enable +// Default: 1 +#define RTE_CPI_STREAMING_ENABLE 1 + +// MT9M114 [Driver_MT9M114] +// Enable/Disable MT9M114 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 camera sensor +// default: disable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE 0 + +#if (RTE_MT9M114_CAMERA_SENSOR_CPI_ENABLE) + +// Select camera MT9M114 pixel clock polarity +// <0=> not invert camera pixclk +// <1=> invert camera pixclk +// Defines camera MT9M114 pixel clock polarity +// Default: not invert camera pixclk +#define RTE_MT9M114_CAMERA_SENSOR_CPI_PIXEL_CLK_POL 0 + +// Select camera MT9M114 HSYNC polarity +// <0=> not invert HSYNC input +// <1=> invert HSYNC input +// Defines camera MT9M114 HSYNC polarity +// Default: not invert HSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_CPI_HSYNC_POL 0 + +// Select camera MT9M114 VSYNC polarity +// <0=> not invert VSYNC input +// <1=> invert VSYNC input +// Defines camera MT9M114 VSYNC polarity +// Default: not invert VSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_POL 0 + +// Select camera MT9M114 VSYNC wait +// <0=> vsync wait disable +// <1=> vsync wait enable +// Defines camera MT9M114 VSYNC wait +// Default: vsync wait disable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_WAIT 0 + +// Select camera MT9M114 VSYNC mode +// <0=> sync enable +// <1=> data enable +// Defines camera MT9M114 VSYNC mode +// Default: sync enable +#define RTE_MT9M114_CAMERA_SENSOR_CPI_VSYNC_MODE 0 + +// Select video data mode +// <0=> 1 bit +// <1=> 2 bit +// <2=> 4 bit +// <3=> 8 bit +// <4=> 16 bit +// Defines video data mode +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MODE 3 + +// Select Data Endianness +// <0=> LSB First +// <1=> MSB First +// Select MSB/LSB +// Default: LSB +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_ENDIANNESS 0 + +// Select CODE10ON8 +// <0=> Disable +// <1=> Enable +// Defines transfer 10-bit coding over 8-bit data bus. +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_CODE10ON8 0 + +// Select camera MT9M114 data mask +// <0=> 16 bit +// <1=> 10 bit +// <2=> 12 bit +// <3=> 14 bit +// Defines camera MT9M114 data mask +// Default: 10 bit +#define RTE_MT9M114_CAMERA_SENSOR_CPI_DATA_MASK 1 + +// select MT9M114 frame height +// defines select MT9M114 frame height. +// default: 480 +#define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_HEIGHT 480 + +// select MT9M114 frame width +// defines select MT9M114 frame width. +// default: 640 +#define RTE_MT9M114_CAMERA_SENSOR_CPI_FRAME_WIDTH 640 + +#endif +// MT9M114 [Driver_MT9M114] + +#endif +// CPI (Camera) [Driver_CPI] + +// LPCPI (Camera) [Driver_LPCPI] +// Configuration settings for Driver_LPCPI in component ::Drivers:LPCPI +#define RTE_LPCPI 0 +#if RTE_LPCPI + +// LPCPI interrupt priority <0-255> +// Defines LPCPI interrupt priority. +// Default: 0 +#define RTE_LPCPI_IRQ_PRI 0 + +// Select LPCPI AXI port +// <0=> disable +// <1=> enable +// Defines LPCPI AXI port +// Default: AXI port enable +#define RTE_LPCPI_AXI_PORT 1 + +// Select LPCPI ISP port +// <0=> disable +// <1=> enable +// Defines LPCPI ISP port +// Default: ISP port disable +#define RTE_LPCPI_ISP_PORT 0 + +// LPCPI Row roundup +// <0=> disable +// <1=> enable +// Defines LPCPI row roundup to 64 bit. +// Default: 0 +#define RTE_LPCPI_ROW_ROUNDUP 0 + +// LPCPI FIFO read watermark +// Defines LPCPI FIFO read watermark. +// Default: 0x8 +#define RTE_LPCPI_FIFO_READ_WATERMARK 0x8 + +// LPCPI FIFO write watermark +// Defines LPCPI FIFO write watermark. +// Default: 0x18 +#define RTE_LPCPI_FIFO_WRITE_WATERMARK 0x18 + +// LPCPI horizontal back porch +// Defines LPCPI horizontal back porch. +// Default: 0x0 +#define RTE_LPCPI_HBP 0 + +// LPCPI horizontal front porch +// Defines LPCPI horizontal front porch. +// Default: 0x0 +#define RTE_LPCPI_HFP 0 + +// LPCPI horizontal cropping +// <0=> disable +// <1=> enable +// Defines LPCPI horizontal cropping +// Default: 0x1 +#define RTE_LPCPI_HFP_EN 0 + +// LPCPI vertical back porch +// Defines LPCPI vertical back porch. +// Default: 0x0 +#define RTE_LPCPI_VBP 0 + +// LPCPI vertical front porch +// Defines LPCPI vertical front porch. +// Default: 0x0 +#define RTE_LPCPI_VFP 0 + +// LPCPI vertical cropping +// <0=> disable +// <1=> enable +// Defines LPCPI vertical cropping +// Default: 0x1 +#define RTE_LPCPI_VFP_EN 0 + +// MT9M114 [Driver_MT9M114] +// Enable/Disable MT9M114 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 camera sensor +// default: disable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE 1 + +#if (RTE_MT9M114_CAMERA_SENSOR_LPCPI_ENABLE) + +// Select camera MT9M114 pixel clock polarity +// <0=> not invert camera pixclk +// <1=> invert camera pixclk +// Defines camera MT9M114 pixel clock polarity +// Default: not invert camera pixclk +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_PIXEL_CLK_POL 0 + +// Select camera MT9M114 HSYNC polarity +// <0=> not invert HSYNC input +// <1=> invert HSYNC input +// Defines camera MT9M114 HSYNC polarity +// Default: not invert HSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_HSYNC_POL 0 + +// Select camera MT9M114 VSYNC polarity +// <0=> not invert VSYNC input +// <1=> invert VSYNC input +// Defines camera MT9M114 VSYNC polarity +// Default: not invert VSYNC input +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_POL 0 + +// Select camera MT9M114 VSYNC wait +// <0=> vsync wait disable +// <1=> vsync wait enable +// Defines camera MT9M114 VSYNC wait +// Default: vsync wait disable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_WAIT 0 + +// Select camera MT9M114 VSYNC mode +// <0=> sync enable +// <1=> data enable +// Defines camera MT9M114 VSYNC mode +// Default: sync enable +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_VSYNC_MODE 0 + +// Select video data mode +// <0=> 1 bit +// <1=> 2 bit +// <2=> 4 bit +// <3=> 8 bit +// Defines video data mode +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_MODE 3 + +// Select Data Endianness +// <0=> LSB First +// <1=> MSB First +// Select MSB/LSB +// Default: LSB +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_DATA_ENDIANNESS 0 + +// Select CODE10ON8 +// <0=> Disable +// <1=> Enable +// Defines transfer 10-bit coding over 8-bit data bus. +// Default: 8 bit +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_CODE10ON8 0 + +// select MT9M114 frame height +// defines select MT9M114 frame height. +// default: 480 +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_HEIGHT 480 + +// select MT9M114 frame width +// defines select MT9M114 frame width. +// default: 640 +#define RTE_MT9M114_CAMERA_SENSOR_LPCPI_FRAME_WIDTH 640 + +#endif +// MT9M114 [Driver_MT9M114] + +#endif +// LPCPI (Camera) [Driver_LPCPI] + +// ISP (ISP) [Driver_ISP] +// Configuration settings for Driver_ISP in component ::Drivers:ISP +#define RTE_ISP 1 +#if RTE_ISP + +// ISP IRQ priority <0-255> +// Defines Interrupt priority for ISP. +// Default: 0 +#define RTE_ISP_IRQ_PRIORITY 0 + +// ISP Enable AE Module +// <0=> disable +// <1=> enable +// defines if AE Module is enabled or not +// default: false +#define RTE_ISP_AE_MODULE 1 + +// ISP Enable BLS Module +// <0=> disable +// <1=> enable +// defines if Black Level Subtraction Module is enabled or not +// default: false +#define RTE_ISP_BLS_MODULE 1 + +// ISP Enable DMSC Module +// <0=> disable +// <1=> enable +// defines if Demosaic Module is enabled or not +// default: false +#define RTE_ISP_DMSC_MODULE 1 + +// ISP Enable FLT Module +// <0=> disable +// <1=> enable +// defines if Noise/Sharpening-Filter Module is enabled or not +// default: false +#define RTE_ISP_FLT_MODULE 1 + +// ISP Enable CCM Module +// <0=> disable +// <1=> enable +// defines if Color Correction Matrix Module is enabled or not +// default: false +#define RTE_ISP_CCM_MODULE 1 + +// ISP Enable CSM Module +// <0=> disable +// <1=> enable +// defines if Color Space Conversion Module is enabled or not +// default: false +#define RTE_ISP_CSM_MODULE 1 + +// ISP Enable WB Module +// <0=> disable +// <1=> enable +// defines if White Balancing Module is enabled or not +// default: false +#define RTE_ISP_WB_MODULE 1 + +// ISP Enable EXPM Module +// <0=> disable +// <1=> enable +// defines if Auto-Exposure Statistics Module is enabled or not +// default: false +#define RTE_ISP_EXPM_MODULE 1 + +// ISP Enable Gamma-out Module +// <0=> disable +// <1=> enable +// defines if Gamma-out Module is enabled or not +// default: false +#define RTE_ISP_GAMMAOUT_MODULE 1 + +// ISP Enable WBM Module +// <0=> disable +// <1=> enable +// defines if White-Balancing Statistics Module is enabled or not +// default: false +#define RTE_ISP_WBM_MODULE 1 + +// ISP Enable Binning Module +// <0=> disable +// <1=> enable +// defines if Binning Module is enabled or not +// default: false +#define RTE_ISP_BINNING_MODULE 1 + +// ISP Binning Enable +// <0=> disable +// <1=> enable +// Enable binning processing in ISP +// default: false +#define RTE_ISP_BINNING_ENABLE 0 + +// ISP Binning Horizontal Step <0-255> +// Horizontal binning step size +// default: 0 +#define RTE_ISP_BINNING_HSTEP 0 + +// ISP Binning Vertical Step <0-255> +// Vertical binning step size +// default: 0 +#define RTE_ISP_BINNING_VSTEP 0 + +// ISP Enable Scaling Module +// <0=> disable +// <1=> enable +// defines if scaling Module is enabled or not +// default: true +#define RTE_ISP_SCALAR_MODULE 1 + +// ISP log level +// <0=> NONE +// <1 => Logs all fatal errors. +// <2=> Logs all warnings. +// <3=> Logs all informational messages. +// <4=> Logs all debug messages. +// <5=> Log level verbose +// Defines ISP logging level +#define RTE_ISP_LOG_LEVEL 5 + +// ISP Buffer Count <2-8> +// Number of video buffers for ISP +#define RTE_ISP_BUFFER_COUNT 1 + +// ISP Output Format +// <20=> RAW8 (8-bit raw) +// <21=> RAW10 (10-bit raw) +// <22=> RAW12 (12-bit raw) +// <23=> NV12 (YUV420 semi-planar) +// <25=> NV16 (YUV422 semi-planar) +// <30=> YUV422P (YUV422 planar) +// <31=> YUV420P (YUV420 planar) +// <32=> YUYV (YUV422 packed) +// <37=> YUV400 (Grayscale) +// <38=> RGB888 (RGB interleaved) +// <39=> RGB888P (RGB planar) +// <40=> RAW420SP (RAW420 semi-planar) +// <41=> RAW422SP (RAW422 semi-planar) +// Defines ISP output pixel format for memory dump +// Default: RGB888 +#define RTE_ISP_OUTPUT_FORMAT 32 + +// ISP Scaler Output Width +// Width in pixels of the ISP scaler output (after scaling from sensor dimensions). +#define RTE_ISP_OUTPUT_WIDTH 480 + +// ISP Scaler Output Height +// Height in pixels of the ISP scaler output (after scaling from sensor dimensions). +#define RTE_ISP_OUTPUT_HEIGHT 480 + +// ISP Sensor Input Width +// Width in pixels of the sensor input to the ISP pipeline. +// Default: MT9M114 sensor resolution (1280). Change for different sensors. +#define RTE_ISP_SENSOR_INPUT_WIDTH RTE_MT9M114_CAMERA_SENSOR_FRAME_WIDTH + + +// ISP Sensor Input Height +// Height in pixels of the sensor input to the ISP pipeline. +// Default: MT9M114 sensor resolution (720). Change for different sensors. +#define RTE_ISP_SENSOR_INPUT_HEIGHT RTE_MT9M114_CAMERA_SENSOR_FRAME_HEIGHT + +// ISP Crop Top offset <0-4095> +// Top offset in pixels for the cropped output window +#define RTE_ISP_CROP_TOP 0 + +// ISP Crop Left offset <0-4095> +// Left offset in pixels for the cropped output window +#define RTE_ISP_CROP_LEFT 0 + +// ISP Crop Width <1-4095> +// Width in pixels of the cropped output window. +// Default: full sensor input (no crop). Override with smaller value to crop. +#define RTE_ISP_CROP_WIDTH RTE_ISP_SENSOR_INPUT_WIDTH + +// ISP Crop Height <1-4095> +// Height in pixels of the cropped output window. +// Default: full sensor input (no crop). Override with smaller value to crop. +#define RTE_ISP_CROP_HEIGHT RTE_ISP_SENSOR_INPUT_HEIGHT + +#endif +// ISP (ISP) [Driver_ISP] + +// JPEG (JPEG) [Driver_JPEG] +// Configuration settings for Driver_JPEG in component ::Drivers:JPEG +#define RTE_JPEG 1 +#if RTE_JPEG + +// JPEG IRQ priority <0-255> +// Defines Interrupt priority for JPEG. +// Default: 0 +#define RTE_JPEG_IRQ_PRIORITY 0 + +// JPEG Encoding Mode +// <0=> 4:2:0(4lum+2chrblocks/MCU) +// Defines encoding mode for JPEG. +// Default: 0 +#define RTE_JPEG_MODE 0 + +// JPEG Encoding Mode +// <0=> JPEGENC_420_MODE +// Defines encoding mode for JPEG. +// Default: 0 +#define RTE_JPEG_CODING_MODE 0 + +// JPEG AXI Burst Length +// AXI burst length for JPEG. +// Default: 64 +#define RTE_JPEG_AXI_BURST_LENGTH 64 + +// JPEG AXI write outstanding number +// AXI write outstanding number for JPEG. +// Default: 64 +#define RTE_AXI_WRITE_OUTSTANDING_NUM 64 + +// JPEG AXI read outstanding number +// AXI read outstanding number for JPEG. +// Default: 64 +#define RTE_AXI_READ_OUTSTANDING_NUM 64 + +#endif +// JPEG (JPEG) [Driver_JPEG] + +// MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] +// Configuration settings for Driver_MIPI_CSI2 in component ::Drivers:MIPI_CSI2 +#define RTE_MIPI_CSI2 1 +#if RTE_MIPI_CSI2 + +// Select CSI2 DPHY backend +// <0=> CSI2 RX DPHY +// <1=> DSI TX DPHY used as RX +// Selects which DPHY hardware is used by Driver_MIPI_CSI2. +// Default: CSI2 RX DPHY +#define RTE_MIPI_CSI2_DPHY_BACKEND 0 + +// CSI pixel clock select +// <0=> Select AXI clock source +// <1=> Select PLL clock source +// Defines CSI pixel clock select +// Default: Select AXI clock source +#define RTE_CSI2_PIX_CLK_SEL 0 + +// select IPI mode +// <0=> camera mode +// <1=> controller mode +// defines select IPI mode +// default: camera mode +#define RTE_MIPI_CSI2_IPI_MODE 0 + +// select memory flush +// <0=> manual +// <1=> auto +// defines select memory flush +// default: auto +#define RTE_MIPI_CSI2_MEMFLUSH 1 + +// select sync event mode +// <0=> not trigger by frame start +// <1=> trigger by frame start +// defines select sync event mode +// default : not trigger by frame start +#define RTE_MIPI_CSI2_SYNC_ET_MODE 0 + +// select sync event select +// <0=> auto +// <1=> programmed +// defines select sync event select +// default : programmed +#define RTE_MIPI_CSI2_SYNC_ET_SEL 1 + +// embedded packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use embedded packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_EMBEDDED 0 + +// blanking packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use blanking packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_BLANKING 0 + +// null packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use null packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_NULL 0 + +// line start packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use line start packets for IPI synchronization events +// default: disable +#define RTE_MIPI_CSI2_EN_LINE_START 0 + +// video packets for IPI synchronization events +// <0=> disable +// <1=> enable +// define if want to use video packets for IPI synchronization events +// default: enable +#define RTE_MIPI_CSI2_EN_VIDEO 1 + +// datatype to overwrite +// select CSI2 Data type to overwrite +// <24=> YUV420_8 +// <25=> YUV420_10 +// <26=> YUV420_8_LEGACY +// <28=> YUV420_8_SHIFT +// <29=> YUV420_10_SHIFT +// <30=> YUV422_8 +// <31=> YUV422_10 +// <32=> RGB444 +// <33=> RGB555 +// <34=> RGB565 +// <35=> RGB666 +// <36=> RGB888 +// <40=> RAW6 +// <41=> RAW7 +// <42=> RAW8 +// <43=> RAW10 +// <44=> RAW12 +// <45=> RAW14 +// <46=> RAW16 +// <48=> USER_DEFINED_1 +// <49=> USER_DEFINED_2 +// <50=> USER_DEFINED_3 +// <51=> USER_DEFINED_4 +// <52=> USER_DEFINED_5 +// <53=> USER_DEFINED_6 +// <54=> USER_DEFINED_7 +// <55=> USER_DEFINED_8 +// defines select CSI2 Data type to be overwrite +// default: RAW10 +#define RTE_MIPI_CSI2_EN_DT 43 + +// datatype to overwrite with programmed datatype +// define if want to use programmed datatype ignoring datatype of the header +// default: 0 +#define RTE_MIPI_CSI2_EN_DT_OVERWRITE 0 + +// Horizontal Synchronism Active Time range <0-2047> +// Defines possible range for selecting horizontal sync active time +// Default: 0 +#define RTE_MIPI_CSI2_IPI_HSA_TIME 5 + +// Horizontal Synchronism back porch Time range <0-2047> +// Defines possible range for selecting horizontal sync back porch time +// Default: 0 +#define RTE_MIPI_CSI2_IPI_HBP_TIME 10 + +// Horizontal sync delay Time range <0-2047> +// Defines possible range for selecting horizontal sync delay time +// Default: 560 +#define RTE_MIPI_CSI2_IPI_HSD_TIME 280 + +// Horizontal Active Time range <0-2047> +// Defines possible range for selecting horizontal active time +// Default: 560 +#define RTE_MIPI_CSI2_IPI_HACTIVE_TIME 560 + +// Vertical sync active period range <0-511> +// Defines possible range for selecting vertical sync active period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VSA_LINE 4 + +// Vertical back porch period range <0-511> +// Defines possible range for selecting vertical back porch period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VBP_LINE 4 + +// Vertical front porch period range <0-511> +// Defines possible range for selecting vertical front porch period +// Default: 0 +#define RTE_MIPI_CSI2_IPI_VFP_LINE 4 + +// Vertical active period range <0-8191> +// Defines possible range for selecting vertical active period +// Default: 560 +#define RTE_MIPI_CSI2_IPI_VACTIVE_LINE 560 + +// CSI2 interrupt priority <0-255> +// Defines CSI2 interrupt priority. +// Default: 0 +#define RTE_MIPI_CSI2_IRQ_PRI 0 + +// ARX3A0 [Driver_ARX3A0] +// Enable/Disable ARX3A0 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable ARX3A0 camera sensor +// default: enable +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_ARX3A0_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera ARX3A0 frame per second +// <5=> 5 FPS +// <40=> 40 FPS +// <60=> 60 FPS +// <90=> 90 FPS +// Defines camera ARX3A0 frame per second +// Default: 90 FPS +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_CFG_FPS 90 + +// Select camera ARX3A0 frequency +// Defines camera ARX3A0 frequency +// Default: 400000000 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_FREQ 400000000 + +// select ARX3A0 CSI2 Data type +// defines select CSI2 Data type +// default: 43(RAW10) +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_DATA_TYPE 43 + +// select ARX3A0 number of lanes in DPHY +// defines select ARX3A0 number of lanes in DPHY. +// default: 2 two lane +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_N_LANES 2 + +// select ARX3A0 virtual channel ID +// defines select ARX3A0 virtual channel ID. +// default: 0 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_VC_ID 0 + +// select ARX3A0 override CPI color mode +// defines select ARX3A0 override CPI color mode. +// default: 1 (Ensable) +#define RTE_ARX3A0_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select ARX3A0 CPI color mode +// defines select ARX3A0 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_ARX3A0_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select ARX3A0 frame height +// defines select ARX3A0 frame height. +// default: 560 +#define RTE_ARX3A0_CAMERA_SENSOR_FRAME_HEIGHT 560 + +// select ARX3A0 frame width +// defines select ARX3A0 frame width. +// default: 560 +#define RTE_ARX3A0_CAMERA_SENSOR_FRAME_WIDTH 560 + +// Select camera sensor ARX3A0 CSI clock source division [Divisor] <2-511> +// Defines camera sensor ARX3A0 CSI clock source division +// Default: 20 +#define RTE_ARX3A0_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 + +// RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor ARX3A0 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_ARX3A0_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// ARX3A0 [Driver_ARX3A0] + +// AR0144 [Driver_AR0144] +// Enable/Disable AR0144 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0144 camera sensor +// default: enable +#define RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0144_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0144 frequency +// Defines camera AR0144 frequency +// Default: 225000000 +#define RTE_AR0144_CAMERA_SENSOR_CSI_FREQ 225000000 + +// select AR0144 CSI2 Data type +// defines select CSI2 Data type +// default: 44(RAW12) +#define RTE_AR0144_CAMERA_SENSOR_CSI_DATA_TYPE 44 + +// select AR0144 number of lanes in DPHY +// defines select AR0144 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0144_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0144 virtual channel ID +// defines select AR0144 virtual channel ID. +// default: 0 +#define RTE_AR0144_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0144 override CPI color mode +// defines select AR0144 override CPI color mode. +// default: 1 (Ensable) +#define RTE_AR0144_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select AR0144 CPI color mode +// defines select AR0144 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_AR0144_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select AR0144 frame height +// defines select AR0144 frame height. +// default: 560 +#define RTE_AR0144_CAMERA_SENSOR_FRAME_HEIGHT 800 + +// select AR0144 frame width +// defines select AR0144 frame width. +// default: 560 +#define RTE_AR0144_CAMERA_SENSOR_FRAME_WIDTH 1280 + +// Select camera sensor AR0144 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0144 CSI clock source division +// Default: 20 +#define RTE_AR0144_CAMERA_SENSOR_CSI_CLK_SCR_DIV 20 + +// RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0144 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0144_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0114 [Driver_AR0114] + +// AR0145 [Driver_AR0145] +// Enable/Disable AR0145 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0145 camera sensor +// default: enable +#define RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0145_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0145 frequency +// Defines camera AR0145 frequency +// Default: 400000000 +#define RTE_AR0145_CAMERA_SENSOR_CSI_FREQ 400000000 + +// select AR0145 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2A(RAW8) +#define RTE_AR0145_CAMERA_SENSOR_CSI_DATA_TYPE 0x2A + +// select AR0145 number of lanes in DPHY +// defines select AR0145 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0145_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0145 virtual channel ID +// defines select AR0145 virtual channel ID. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0145 override CPI color mode +// defines select AR0145 override CPI color mode. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 + +// select AR0145 CPI color mode +// defines select AR0145 CPI color mode. +// default: 0 +#define RTE_AR0145_CAMERA_SENSOR_CPI_COLOR_MODE 0 + +// select AR0145 Image configuration +// Defines camera sensor AR0145 Image configuration +// <0=> 1280x800_Full_1M +// <1=> 640x400_YSum2_XBin2 +// <2=> 640x400_YSkip2_XSkip2 +// <3=> 320x200_YSkip2_XSkip2 +// Default: 0 +#define RTE_AR0145_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// Select camera sensor AR0145 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0145 CSI clock source division +// Default: 16 +#define RTE_AR0145_CAMERA_SENSOR_CSI_CLK_SCR_DIV 16 + +// RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0145 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0145_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0145 [Driver_AR0145] + +// AR0246 [Driver_AR0246] +// Enable/Disable AR0246 camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable AR0246 camera sensor +// default: enable +#define RTE_AR0246_CAMERA_SENSOR_CSI_ENABLE 1 + +#if (RTE_AR0246_CAMERA_SENSOR_CSI_ENABLE) + +// Select camera AR0246 frequency +// Defines camera AR0246 frequency +// Default: 442000000 +#define RTE_AR0246_CAMERA_SENSOR_CSI_FREQ 442000000 + +// select AR0246 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2C(RAW12) +#define RTE_AR0246_CAMERA_SENSOR_CSI_DATA_TYPE 0x2C + +// select AR0246 number of lanes in DPHY +// defines select AR0246 number of lanes in DPHY. +// default: 2 two lane +#define RTE_AR0246_CAMERA_SENSOR_CSI_N_LANES 2 + +// select AR0246 virtual channel ID +// defines select AR0246 virtual channel ID. +// default: 0 +#define RTE_AR0246_CAMERA_SENSOR_CSI_VC_ID 0 + +// select AR0246 override CPI color mode +// defines select AR0246 override CPI color mode. +// default: 1 (Enable) +#define RTE_AR0246_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select AR0246 CPI color mode +// defines select AR0246 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_AR0246_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select AR0246 frame height +// defines select AR0246 frame height. +// default: 472 +#define RTE_AR0246_CAMERA_SENSOR_FRAME_HEIGHT 472 + +// select AR0246 frame width +// defines select AR0246 frame width. +// default: 684 +#define RTE_AR0246_CAMERA_SENSOR_FRAME_WIDTH 684 + +// Select camera sensor AR0246 CSI clock source division [Divisor] <2-511> +// Defines camera sensor AR0246 CSI clock source division +// Default: 15 +#define RTE_AR0246_CAMERA_SENSOR_CSI_CLK_SCR_DIV 15 + +// RTE_AR0246_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor AR0246 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_AR0246_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// AR0246 [Driver_AR0246] + +// MT9M114_MIPI [Driver_MT9M114_MIPI] +// Enable/Disable MT9M114 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable MT9M114 MIPI camera sensor +// default: enable +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE 1 + +#if (RTE_MT9M114_CAMERA_SENSOR_MIPI_ENABLE) + +// Select camera MT9M114 MIPI frequency +// Defines camera MT9M114 MIPI frequency +// Default: 296000000 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_FREQ 320000000 + +// select MT9M114 Image configuration +// Defines camera sensor MT9M114 Image configuration +// <0=> 1288x728_RAW10 +// <1=> 1280x720_RAW8 +// <2=> 1280x720_RGB565 +// <3=> 640x480_RGB565 +// <4=> 320x240_RGB565 +// <5=> 320x320_RGB565 +// Default: 1 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_IMAGE_CONFIG 1 + +// select MT9M114 MIPI number of lanes in DPHY +// defines select MT9M114 MIPI number of lanes in DPHY. +// default: 1 one lane +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_N_LANES 1 + +// select MT9M114 MIPI virtual channel ID +// defines select MT9M114 MIPI virtual channel ID. +// default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_VC_ID 0 + +// select MT9M114 MIPI override CPI color mode +// defines select MT9M114 MIPI override CPI color mode. +// default: 0 (Disable) +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_OVERRIDE_CPI_COLOR_MODE 0 + +// select MT9M114 MIPI CPI color mode +// defines select MT9M114 MIPI CPI color mode. +// default: 0 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CPI_COLOR_MODE 0 + +// Select camera sensor MT9M114 MIPI CSI clock source division [Divisor] <2-511> +// Defines camera sensor MT9M114 MIPI CSI clock source division +// Default: 20 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 + +// RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE +// Defines camera sensor MT9M114 MIPI i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_MT9M114_CAMERA_SENSOR_MIPI_I2C_INSTANCE 1 + +// MT9M114 sensor frame width for ISP / CSI2 pipeline +// Width in pixels of the MT9M114 MIPI sensor frame +#define RTE_MT9M114_CAMERA_SENSOR_FRAME_WIDTH 1280 + +// MT9M114 sensor frame height for ISP / CSI2 pipeline +// Height in pixels of the MT9M114 MIPI sensor frame +#define RTE_MT9M114_CAMERA_SENSOR_FRAME_HEIGHT 720 + +#endif +// MT9M114_MIPI [Driver_MT9M114_MIPI] + +// HM0360_MIPI [Driver_HM0360_MIPI] +// Enable/Disable HM0360 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable HM0360 MIPI camera sensor +// default: enable +#define RTE_HM0360_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_HM0360_CAMERA_SENSOR_ENABLE) + +// Select camera HM0360 frequency +// Defines camera HM0360 frequency +// Default: 176000000 +#define RTE_HM0360_CAMERA_SENSOR_CSI_FREQ 176000000 + +// Select camera HM0360 frame per second +// <30=> 30 FPS +// <60=> 60 FPS +// Defines camera HM0360 frame per second +// Default: 60 FPS +#define RTE_HM0360_CAMERA_SENSOR_CSI_CFG_FPS 60 + +// Select camera HM0360 context select +// <0=> CONTEXT_A +// <1=> CONTEXT_B +// Defines camera HM0360 context select +// Default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL 0 + +// select HM0360 CSI2 Data type +// defines select CSI2 Data type +// default: 42(RAW8) +#define RTE_HM0360_CAMERA_SENSOR_CSI_DATA_TYPE 42 + +// select HM0360 number of lanes in DPHY +// defines select HM0360 number of lanes in DPHY. +// default: 1 one lane +#define RTE_HM0360_CAMERA_SENSOR_CSI_N_LANES 1 + +// select HM0360 virtual channel ID +// defines select HM0360 virtual channel ID. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CSI_VC_ID 0 + +// select HM0360 override CPI color mode +// defines select HM0360 override CPI color mode. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 0 + +// select HM0360 CPI color mode +// defines select HM0360 CPI color mode. +// default: 0 +#define RTE_HM0360_CAMERA_SENSOR_CPI_COLOR_MODE 0 + +#if (RTE_HM0360_CAMERA_SENSOR_CSI_CXT_SEL == 0) +// select HM0360 frame height +// defines select HM0360 frame height. +// default: 480 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 480 + +// select HM0360 frame width +// defines select HM0360 frame width. +// default: 640 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 640 +#else +// select HM0360 frame height +// defines select HM0360 frame height. +// default: 240 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_HEIGHT 240 + +// select HM0360 frame width +// defines select HM0360 frame width. +// default: 320 +#define RTE_HM0360_CAMERA_SENSOR_FRAME_WIDTH 320 +#endif + +// RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE +// Defines camera sensor HM0360 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// <4=> I2C OVER I3C +// Default: 1 +#define RTE_HM0360_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// HM0360_MIPI [Driver_HM0360_MIPI] + +// OV5647_MIPI [Driver_OV5647_MIPI] +// Enable/Disable OV5647 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable OV5647 MIPI camera sensor +// default: enable +#define RTE_OV5647_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_OV5647_CAMERA_SENSOR_ENABLE) + +// Select camera OV5647 frequency +// Defines camera OV5647 frequency +// Default: 158000000 +#define RTE_OV5647_CAMERA_SENSOR_CSI_FREQ 158000000 + +// select OV5647 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2B (RAW10) +#define RTE_OV5647_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B + +// select OV5647 number of lanes in DPHY +// defines select OV5647 number of lanes in DPHY. +// default: 2 one lane +#define RTE_OV5647_CAMERA_SENSOR_CSI_N_LANES 2 + +// select OV5647 virtual channel ID +// defines select OV5647 virtual channel ID. +// default: 0 +#define RTE_OV5647_CAMERA_SENSOR_CSI_VC_ID 0 + +// select OV5647 override CPI color mode +// defines select OV5647 override CPI color mode. +// default: 1 +#define RTE_OV5647_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select OV5647 CPI color mode +// defines select OV5647 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_OV5647_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// select OV5647 frame height +// defines select OV5647 frame height. +// default: 480 +#define RTE_OV5647_CAMERA_SENSOR_FRAME_HEIGHT 480 + +// select OV5647 frame width +// defines select OV5647 frame width. +// default: 640 +#define RTE_OV5647_CAMERA_SENSOR_FRAME_WIDTH 640 + +// Select camera sensor OV5647 i2c instance +// Defines camera sensor OV5647 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_OV5647_CAMERA_SENSOR_I2C_INSTANCE 1 + +#endif +// OV5647_MIPI [Driver_OV5647_MIPI] + +// OV5675_MIPI [Driver_OV5675_MIPI] +// Enable/Disable OV5675 MIPI camera sensor +// <0=> disable +// <1=> enable +// define if to enable or disable OV5675 MIPI camera sensor +// default: enable +#define RTE_OV5675_CAMERA_SENSOR_ENABLE 1 + +#if (RTE_OV5675_CAMERA_SENSOR_ENABLE) + +// Select camera OV5675 frequency +// Defines camera OV5675 frequency +// Default: 450000000 +#define RTE_OV5675_CAMERA_SENSOR_CSI_FREQ 450000000 + +// select OV5675 CSI2 Data type +// defines select CSI2 Data type +// default: 0x2B (RAW10) +#define RTE_OV5675_CAMERA_SENSOR_CSI_DATA_TYPE 0x2B + +// select OV5675 number of lanes in DPHY +// defines select OV5675 number of lanes in DPHY. +// default: 2 lane +#define RTE_OV5675_CAMERA_SENSOR_CSI_N_LANES 2 + +// select OV5675 virtual channel ID +// defines select OV5675 virtual channel ID. +// default: 0 +#define RTE_OV5675_CAMERA_SENSOR_CSI_VC_ID 0 + +// select OV5675 override CPI color mode +// defines select OV5675 override CPI color mode. +// default: 1 +#define RTE_OV5675_CAMERA_SENSOR_OVERRIDE_CPI_COLOR_MODE 1 + +// select OV5675 CPI color mode +// defines select OV5675 CPI color mode. +// default: 2 (IPI-16 RAW 8) +#define RTE_OV5675_CAMERA_SENSOR_CPI_COLOR_MODE 2 + +// Select OV5675 image configuration +// <0=> 1296x972_RAW10 +// <1=> 1920x1080_RAW10 +// <2=> 1280x720_RAW10 +// <3=> 640x480_RAW10 +// Default: 0 +#define RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG 0 + +// OV5675 frame height (derived from IMAGE_CONFIG) +// defines OV5675 frame height. +// default: 972 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 1080 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 720 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 480 +#else +#define RTE_OV5675_CAMERA_SENSOR_FRAME_HEIGHT 972 +#endif + +// OV5675 frame width (derived from IMAGE_CONFIG) +// defines OV5675 frame width. +// default: 1296 +#if (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 1) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1920 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 2) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1280 +#elif (RTE_OV5675_CAMERA_SENSOR_IMAGE_CONFIG == 3) +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 640 +#else +#define RTE_OV5675_CAMERA_SENSOR_FRAME_WIDTH 1296 +#endif + +// Select camera sensor OV5675 i2c instance +// Defines camera sensor OV5675 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_OV5675_CAMERA_SENSOR_I2C_INSTANCE 1 + +// Select camera sensor OV5675 CSI clock source division [Divisor] <2-511> +// Defines camera sensor OV5675 CSI clock source division +// Default: 20 +#define RTE_OV5675_CAMERA_SENSOR_MIPI_CSI_CLK_SCR_DIV 20 + +#endif +// OV5675_MIPI [Driver_OV5675_MIPI] + +#endif +// MIPI_CSI2 (mipi csi2) [Driver_MIPI_CSI2] + +// MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] +// Configuration settings for Driver_MIPI_DSI in component ::Drivers:MIPI_DSI +#ifndef RTE_MIPI_DSI +#define RTE_MIPI_DSI 1 +#endif // RTE_MIPI_DSI + +#if RTE_MIPI_DSI + +// DPHY PLL input division factor +// Defines DPHY PLL input division factor +// Default: 3 +#define RTE_MIPI_DSI_PLL_INPUT_DIV_FACTOR_N 3 + +// DSI TX escape clock division value. +// Defines DSI TX escape clock division value. +// Default: 2 +#define RTE_MIPI_DSI_TX_ESC_CLK_DIVISION 2 + +// DPI Video Mode +// <0=> NON_BURST SYNC_PULSES +// <1=> NON_BURST SYNC_EVENTS +// <2=> BURST MODE +// Defines DPI Video Mode +// Default:BURST MODE +#define RTE_MIPI_DSI_VID_MODE_TYPE 2 + +// DSI Video number of Chunks +// Defines Number of chunks used to transfer single video packet . +// Default: 0 +#define RTE_MIPI_DSI_VID_NUM_CHUNKS 0 + +// DSI Size of NULL packet +// Defines Size of the NULL packet. +// Default: 0 +#define RTE_MIPI_DSI_VID_NULL_SIZE 0 + +// DSI IRQ priority <0-255> +// Defines Interrupt priority. +// Default: 0 +#define RTE_MIPI_DSI_IRQ_PRI 0 + +// MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] +// DSI ILI9806E LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines DSI ILI9806E LCD PANEL +// Default: ENABLE +#define RTE_MIPI_DSI_ILI9806E_PANEL 1 + +#if RTE_MIPI_DSI_ILI9806E_PANEL + +// DSI ILI9806E panel variant +// <0=> E43RB_FW405 +// <1=> E43GB_MW405 +// <2=> E50RA_MW550 +// Defines ILI9806E panel variant +// Default: E43RB_FW405 +#define RTE_ILI9806E_PANEL_VARIANT 1 + +#if (RTE_ILI9806E_PANEL_VARIANT == 0) +#define RTE_ILI9806E_PANEL_E43RB_FW405_EN 1 +#elif (RTE_ILI9806E_PANEL_VARIANT == 1) +#define RTE_ILI9806E_PANEL_E43GB_MW405_EN 1 +#elif (RTE_ILI9806E_PANEL_VARIANT == 2) +#define RTE_ILI9806E_PANEL_E50RA_MW550_EN 1 +#endif + +// ILI9806 LCD panel maximum bitrate in mbps +// Defines ILI9806 LCD panel maximum bitrate in mbps. +// Default: 500 +#define RTE_ILI9806E_PANEL_MAX_BITRATE_MBPS 500 + +// DSI color mode +// <1=> 16bit +// <4=> 18bit +// <5=> 24bit +// Defines Color mode for display panel +// Default: 24bit +#define RTE_ILI9806E_PANEL_DSI_COLOR_MODE 5 + +// Number of data lanes +// <1=> ONE +// <2=> TWO +// Defines Number of data lanes +// Default: TWO +#define RTE_ILI9806E_PANEL_DSI_N_LANES 0x2 + +// Virtual channel ID +// Defines Virtual Channel ID +// Default: 0 +#define RTE_ILI9806E_PANEL_DSI_VC_ID 0 + +// MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] +#if (RTE_ILI9806E_PANEL_E43RB_FW405_EN || RTE_ILI9806E_PANEL_E43GB_MW405_EN) + +// Panel hsync time in pixels +// Defines ILI9806 LCD panel hsync time in pixels. +// Default: 4 +#define RTE_PANEL_HSYNC_TIME 4 + +// Panel FW405/MW405 hbp time in pixels +// Defines ILI9806 LCD panel hbp time in pixels. +// Default: 5 +#define RTE_PANEL_HBP_TIME 5 + +// Panel FW405/MW405 hfp time in pixels +// Defines ILI9806 LCD panel hfp time in pixels. +// Default: 5 +#define RTE_PANEL_HFP_TIME 5 + +// Panel FW405/MW405 hactive pixels +// Defines ILI9806 LCD panel hactive pixels. +// Default: 480 +#define RTE_PANEL_HACTIVE_TIME 480 + +// Panel FW405/MW405 vsync time in lines +// Defines ILI9806 LCD panel vsync time in lines. +// Default: 2 +#define RTE_PANEL_VSYNC_LINE 2 + +// Panel FW405/MW405 vbp time in lines +// Defines ILI9806 LCD panel vbp time in lines. +// Default: 10 +#define RTE_PANEL_VBP_LINE 10 + +// Panel FW405/MW405 vfp time in lines +// Defines ILI9806 LCD panel vfp time in lines. +// Default: 10 +#define RTE_PANEL_VFP_LINE 10 + +// Panel FW405/MW405 vactive lines +// Defines ILI9806 LCD panel vactive lines. +// Default: 800 +#define RTE_PANEL_VACTIVE_LINE 800 +// MIPI_DSI (ILI9806E_PANEL_E43RB_FW405 | ILI9806E_PANEL_E43GB_MW405) [Driver_ILI9806E_PANEL] + +// MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] +#elif RTE_ILI9806E_PANEL_E50RA_MW550_EN + +// Panel MW550 hsync time in pixels +// Defines ILI9806 LCD panel hsync time in pixels. +// Default: 4 +#define RTE_PANEL_HSYNC_TIME 4 + +// Panel MW550 hbp time in pixels +// Defines ILI9806 LCD panel hbp time in pixels. +// Default: 30 +#define RTE_PANEL_HBP_TIME 30 + +// Panel MW550 hfp time in pixels +// Defines ILI9806 LCD panel hfp time in pixels. +// Default: 18 +#define RTE_PANEL_HFP_TIME 18 + +// Panel MW550 hactive pixels +// Defines ILI9806 LCD panel hactive pixels. +// Default: 480 +#define RTE_PANEL_HACTIVE_TIME 480 + +// Panel MW550 vsync time in lines +// Defines ILI9806 LCD panel vsync time in lines. +// Default: 4 +#define RTE_PANEL_VSYNC_LINE 4 + +// Panel MW550 vbp time in lines +// Defines ILI9806 LCD panel vbp time in lines. +// Default: 30 +#define RTE_PANEL_VBP_LINE 30 + +// Panel MW550 vfp time in lines +// Defines ILI9806 LCD panel vfp time in lines. +// Default: 20 +#define RTE_PANEL_VFP_LINE 20 + +// Panel MW550 vactive lines +// Defines ILI9806 LCD panel vactive lines. +// Default: 854 +#define RTE_PANEL_VACTIVE_LINE 854 +#endif +// MIPI_DSI (ILI9806E_PANEL_E50RA_MW550) [Driver_ILI9806E_PANEL] + +// MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] +// DSI ILI9488 LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines DSI ILI9488 LCD PANEL +// Default: ENABLE +#define RTE_MIPI_DSI_ILI9488_PANEL 1 + +#if RTE_MIPI_DSI_ILI9488_PANEL + +// ILI9806 LCD panel maximum bitrate in mbps +// Defines ILI9806 LCD panel maximum bitrate in mbps. +// Default: 500 +#define RTE_ILI9488_PANEL_MAX_BITRATE_MBPS 500 + +// DSI color mode +// <1=> 16bit +// <4=> 18bit +// Defines Color mode for display panel +// Default: 16bit +#define RTE_ILI9488_PANEL_DSI_COLOR_MODE 1 + +// Virtual channel ID +// Defines Virtual Channel ID +// Default: 0 +#define RTE_ILI9488_PANEL_DSI_VC_ID 0 + +// Panel hsync time in pixels +// Defines ILI9488 LCD panel hsync time in pixels. +// Default: 10 +#define RTE_ILI9488_PANEL_HSYNC_TIME 10 + +// Panel ILI9488 hbp time in pixels +// Defines ILI9488 LCD panel hbp time in pixels. +// Default: 10 +#define RTE_ILI9488_PANEL_HBP_TIME 10 + +// Panel ILI9488 hfp time in pixels +// Defines ILI9488 LCD panel hfp time in pixels. +// Default: 40 +#define RTE_ILI9488_PANEL_HFP_TIME 40 + +// Panel ILI9488 hactive pixels +// Defines ILI9488 LCD panel hactive pixels. +// Default: 320 +#define RTE_ILI9488_PANEL_HACTIVE_TIME 320 + +// Panel ILI9488 vsync time in lines +// Defines ILI9488 LCD panel vsync time in lines. +// Default: 2 +#define RTE_ILI9488_PANEL_VSYNC_LINE 2 + +// Panel ILI9488 vbp time in lines +// Defines ILI9488 LCD panel vbp time in lines. +// Default: 16 +#define RTE_ILI9488_PANEL_VBP_LINE 16 + +// Panel ILI9488 vfp time in lines +// Defines ILI9488 LCD panel vfp time in lines. +// Default: 10 +#define RTE_ILI9488_PANEL_VFP_LINE 10 + +// Panel ILI9488 vactive lines +// Defines ILI9488 LCD panel vactive lines. +// Default: 480 +#define RTE_ILI9488_PANEL_VACTIVE_LINE 480 + +#endif +// MIPI_DSI (ILI9488_PANEL) [Driver_ILI9488_PANEL] + +#endif +// MIPI_DSI (ILI9806E_PANEL) [Driver_ILI9806E_PANEL] + +#endif +// MIPI_DSI (mipi dsi) [Driver_MIPI_DSI] + +// TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] +// Configuration settings for Driver_Touch_Screen in component ::Drivers:touch screen +#define RTE_TOUCH_SCREEN 1 + +#if RTE_TOUCH_SCREEN + +// GT911 Touch screen +// <0=> DISABLE +// <1=> ENABLE +// Defines GT911 Touch screen +// Default: ENABLE +#define RTE_GT911 1 + +#if RTE_GT911 + +// select active touch points +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// defines select active touch points +// default: 5 +#define RTE_ACTIVE_TOUCH_POINTS 5 + +// RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL +// Defines GT911 Touchscreen i2c slave address selection +// <0x14=> I2C_SLAVE_ADDRESS_HEX_14 +// <0x5D=> I2C_SLAVE_ADDRESS_HEX_5D +// Default: 0x14 +#define RTE_GT911_TOUCH_I2C_SLAVE_ADDRESS_SEL 0x14 +#endif + +#endif +// TOUCH_SCREEN (touch screen) [Driver_Touch_Screen] + +// CDC200 (cdc200) [Driver_CDC200] +// Configuration settings for Driver_CDC200 in component ::Drivers:CDC200 +#define RTE_CDC200 1 + +#if RTE_CDC200 + +// CDC200 IRQ priority <0-255> +// Defines Interrupt priority. +// Default: 0 +#define RTE_CDC200_IRQ_PRI 0 + +// CDC200 clock select +// <0=> Select AXI clock source +// <1=> Select PLL clock source +// Defines CDC200 clock select +// Default: Select AXI clock source +#define RTE_CDC200_CLK_SEL 0 + +// CDC200 background color red <0-255> +// Defines CDC200 background color red. +// Default: 0 +#define RTE_CDC200_BGC_RED 0 + +// CDC200 background color green <0-255> +// Defines CDC200 background color green. +// Default: 0 +#define RTE_CDC200_BGC_GREEN 0 + +// CDC200 background color blue <0-255> +// Defines CDC200 background color blue. +// Default: 0 +#define RTE_CDC200_BGC_BLUE 0 + +// CDC200 pixel format +// <0=> ARGB8888 +// <1=> RGB888 +// <2=> RGB565 +//      <3=> RGBA8888 +//      <6=> ARGB1555 +//      <7=> ARGB4444 +// Defines CDC200 pixel format +// Default: RGB888 +#define RTE_CDC200_PIXEL_FORMAT 1 + +// CDC200 Constant alpha <0-255> +// Defines CDC200 constant alpha range from 0 (fully transparent) to 255 or 1.0 (fully opaque). +// Default: 255 +#define RTE_CDC200_CONSTANT_ALPHA 255 + +// CDC200 blending factor +// <0=> CONST_ALPHA +// <1=> PIXEL_ALPHA_X_CONST_ALPHA +// Defines CDC200 blending factor selection. +// Default: PIXEL_ALPHA_X_CONST_ALPHA +#define RTE_CDC200_BLEND_FACTOR 1 + +// CDC200 DPI interface FPS +// Defines CDC200 DPI interface Framrate per second. +// Default: 60 +#define RTE_CDC200_DPI_FPS 60 + +// Parallel ILI6122 LCD PANEL +// <0=> DISABLE +// <1=> ENABLE +// Defines Parallel ILI6122 LCD PANEL +// Default: ENABLE +#ifndef RTE_ILI6122_PANEL +#define RTE_ILI6122_PANEL 0 +#endif // RTE_ILI6122_PANEL + +#if RTE_ILI6122_PANEL + +// CDC HSYNC pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC HSYNC pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_HSYNC_ACTIVE_LOW 0 + +// CDC VSYNC pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC VSYNC pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_VSYNC_ACTIVE_LOW 0 + +// CDC Pixel Clock Output pin active state +// <0=> FEED THROUGH +// <1=> INVERTED +// Defines CDC Pixel Clock pin active state +// Default: FEED THROUGH +#define RTE_ILI6122_PANEL_CDC_PIXCLK_FEED_THROUGH 0 + +// CDC BLANKING pin active state +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines CDC BLANKINg pin active state +// Default: ACTIVE LOW +#define RTE_ILI6122_PANEL_CDC_BLANK_ACTIVE_LOW 0 + +// Panel hsync time in pixels +// Defines ILI6122 LCD panel hsync time in pixels. +// Default: 1 +#define RTE_PANEL_HSYNC_TIME 1 + +// Panel hbp time in pixels +// Defines ILI6122 LCD panel hbp time in pixels. +// Default: 46 +#define RTE_PANEL_HBP_TIME 46 + +// Panel hfp time in pixels +// Defines ILI6122 LCD panel hfp time in pixels. +// Default: 210 +#define RTE_PANEL_HFP_TIME 210 + +// Panel hactive pixels +// Defines ILI6122 LCD panel hactive pixels. +// Default: 800 +#define RTE_PANEL_HACTIVE_TIME 800 + +// Panel vsync time in lines +// Defines ILI6122 LCD panel vsync time in lines. +// Default: 1 +#define RTE_PANEL_VSYNC_LINE 1 + +// Panel vbp time in lines +// Defines ILI6122 LCD panel vbp time in lines. +// Default: 23 +#define RTE_PANEL_VBP_LINE 23 + +// Panel vfp time in lines +// Defines ILI6122 LCD panel vfp time in lines. +// Default: 22 +#define RTE_PANEL_VFP_LINE 22 + +// Panel vactive lines +// Defines ILI6122 LCD panel vactive lines. +// Default: 480 +#define RTE_PANEL_VACTIVE_LINE 480 +#endif + +#endif +// CDC200 (cdc200) [Driver_CDC200] + +// I3C (Improved Inter Integrated Circuit) +// I3C (Improved Inter-Integrated Circuit) [Driver_I3C] +// Configuration settings for Driver_I3C in component ::Drivers:I3C +#define RTE_I3C 1 + +#if RTE_I3C + +// I3C IRQ priority <0-255> +// Defines I3C Interrupt priority +// Default: 0 +#define RTE_I3C_IRQ_PRI 0 + +// I2C (Inter Integrated Circuit) [Driver_I2CI3C] +// Configuration settings for Driver_I2CI3C in component ::Drivers:I2CI3C +#define RTE_I2CI3C 1 +// I2C (Inter Integrated Circuit) [Driver_I2CI3C] + +// I3C DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I3C +// Default: DISABLE +#define RTE_I3C_DMA_ENABLE 0 + +// I3C DMA Selection +// <0=> DMA2(M55-HE) +// <1=> DMA0 +// Defines Select DMA0 for I3C. By default DMA0 will be considered +// Default: DMA0 +#define RTE_I3C_SELECT_DMA0 1 + +// I3C DMA IRQ priority <0-255> +// Defines I3C DMA Interrupt priority +// Default: 0 +#define RTE_I3C_DMA_IRQ_PRI 0 + +// I3C blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I3C +// Default: DISABLE +#define RTE_I3C_BLOCKING_MODE_ENABLE 0 + +// I3C Slave I2C/I3C Adaptive mode Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines whether I3C Slave starts with I2C mode or not. +// It is for for enabling some features for I2C/I3C mode +// Default: DISABLE +#define RTE_I3C_SLAVE_ADAPTIVE_MODE_ENABLE 0 + +#endif +// I3C (Improved Inter-Integrated Circuit) [Driver_I3C] + +// LPI3C (Low Power Improved Inter-Integrated Circuit) [Driver_LPI3C] +// Configuration settings for Driver_LPI3C in component ::Drivers:LPI3C +#if defined(RTSS_HE) +#define RTE_LPI3C 1 + +#if RTE_LPI3C + +// LPI3C IRQ priority <0-255> +// Defines LPI3C Interrupt priority +// Default: 0 +#define RTE_LPI3C_IRQ_PRI 0 + +// LPI3C DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPI3C +// Default: DISABLE +#define RTE_LPI3C_DMA_ENABLE 0 + +#if RTE_LPI3C_DMA_ENABLE + +// LPI3C DMA IRQ priority <0-255> +// Defines LPI3C DMA Interrupt priority +// Default: 0 +#define RTE_LPI3C_DMA_IRQ_PRI 0 +#endif +// LPI3C blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPI3C +// Default: DISABLE +#define RTE_LPI3C_BLOCKING_MODE_ENABLE 0 + +// LPI3C Slave I2C/I3C Adaptive mode Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines whether LPI3C Slave starts with I2C mode or not. +// It is for for enabling some features for I2C/I3C mode +// Default: DISABLE +#define RTE_LPI3C_SLAVE_ADAPTIVE_MODE_ENABLE 0 + +#endif +#endif +// LPI3C (Low Power Improved Inter-Integrated Circuit) [Driver_LPI3C] +// + +// IMU (Initial Measurement Unit) [Driver_IMU] +// Configuration settings for Driver_IMU in component ::Drivers:IMU +#define RTE_IMU 1 + +#if RTE_IMU + +// ICM42670 (Initial Measurement Unit) [Driver_ICM42670] +// Configuration settings for Driver_ICM42670 in component ::Drivers:IMU +#define RTE_ICM42670 1 + +#if RTE_ICM42670 + +// ICM42670 IMU enable In-band_interrupt +// <0=> DISABLE +// <1=> ENABLE +// Defines whether In-band-interrupt to be enabled +// If disabled, then Normal-GPIO interrupt will be enabled +// Default: DISABLE +#define RTE_ICM42670_IBI_ENABLE 0 + +#endif +// ICM42670 (Initial Measurement Unit) [Driver_ICM42670] + +// BMI323 (Initial Measurement Unit) [Driver_BMI323] +// Configuration settings for Driver_BMI323 in component ::Drivers:IMU +#define RTE_BMI323 1 + +// BMI323 (Initial Measurement Unit) [Driver_BMI323] +#endif +// IMU (Initial Measurement Unit) [Driver_IMU] + +// SPI (Serial Peripheral Interface) +// SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] +// Configuration settings for Driver_SPI0 in component ::Drivers:SPI +#define RTE_SPI0 1 + +#ifdef RTE_SPI0 + +// SPI0 IRQ priority <0-255> +// Defines Interrupt priority for SPI0. +// Default: 0 +#define RTE_SPI0_IRQ_PRIORITY 0 + +// SPI0 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI0. +// Default: 0 +#define RTE_SPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI0 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI0. +// Default: 0 +#define RTE_SPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI0 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI0. +// Default: 0 +#define RTE_SPI0_TX_FIFO_THRESHOLD 0 + +// SPI0 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI0. +// Default: 0 +#define RTE_SPI0_RX_FIFO_THRESHOLD 0 + +// SPI0 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// Defines slave selection for SPI0. +// Default: 0 +#define RTE_SPI0_CHIP_SELECTION_PIN 0 + +// SPI0 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI0. +// Default: 0 +#define RTE_SPI0_RX_SAMPLE_DELAY 0 + +// SPI0 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI0. +// Default: 1 +#define RTE_SPI0_SSTE_ENABLE 1 + +// SPI0 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI0_USE_MASTER_SS_SW 0 + +#if RTE_SPI0_USE_MASTER_SS_SW + +// SPI0 SW SS Port <0-15> +// Defines SPI0 port of SS pin in software controlled mode. +// Default: 0 +#define RTE_SPI0_SW_SPI_PORT 0 + +// SPI0 SW SS Pin <0-7> +// Defines SPI0 SS pin number in software controlled mode. +// Default: 0 +#define RTE_SPI0_SW_SPI_PIN 0 + +// SPI0 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI0. +// Default: 0 +#define RTE_SPI0_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI0_USE_MASTER_SS_SW + +// SPI0 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI0 MicroWire frame format. +// Default: 0 +#define RTE_SPI0_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI0_MICROWIRE_FRF_ENABLE + +// SPI0 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI0 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI0_MW_TRANSFER_MODE 0 + +// SPI0 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI0 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI0_MW_HANDSAHKE_ENABLE 0 + +// SPI0 MW Control Frame Size +// Defines MW Control Frame Size for SPI0. +// Default: 0 +#define RTE_SPI0_MW_CFS 16 +#endif // RTE_SPI0_MICROWIRE_FRF_ENABLE + +// SPI0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI0 +// Default: DISABLE +#define RTE_SPI0_DMA_ENABLE 0 + +// SPI0 DMA IRQ priority <0-255> +// Defines SPI0 DMA Interrupt priority +// Default: 0 +#define RTE_SPI0_DMA_IRQ_PRI 0 + +// SPI0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI0 +// Default: DISABLE +#define RTE_SPI0_BLOCKING_MODE_ENABLE 0 +#endif +// SPI0 (Serial Peripheral Interface 0) [Driver_SPI0] + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::Drivers:SPI +#define RTE_SPI1 1 + +#ifdef RTE_SPI1 + +// SPI1 IRQ priority <0-255> +// Defines Interrupt priority for SPI1. +// Default: 0 +#define RTE_SPI1_IRQ_PRIORITY 0 + +// SPI1 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI1. +// Default: 0 +#define RTE_SPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI1 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI1. +// Default: 0 +#define RTE_SPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI1 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI1. +// Default: 0 +#define RTE_SPI1_TX_FIFO_THRESHOLD 0 + +// SPI1 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI1. +// Default: 0 +#define RTE_SPI1_RX_FIFO_THRESHOLD 0 + +// SPI1 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// Defines slave selection for SPI1. +// Default: 0 +#define RTE_SPI1_CHIP_SELECTION_PIN 0 + +// SPI1 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI1. +// Default: 0 +#define RTE_SPI1_RX_SAMPLE_DELAY 0 + +// SPI1 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI1. +// Default: 1 +#define RTE_SPI1_SSTE_ENABLE 1 + +// SPI1 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI1_USE_MASTER_SS_SW 0 + +#if RTE_SPI1_USE_MASTER_SS_SW + +// SPI1 SW SS Port <0-15> +// Defines SPI1 port of SS pin in software controlled mode. +// Default: 0 +#define RTE_SPI1_SW_SPI_PORT 0 + +// SPI1 SW SS pin number <0-7> +// Defines SPI1 SS pin number in software controlled mode. +// Default: 0 +#define RTE_SPI1_SW_SPI_PIN 0 + +// SPI1 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI1. +// Default: 0 +#define RTE_SPI1_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI1_USE_MASTER_SS_SW + +// SPI1 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI1 MicroWire frame format. +// Default: 0 +#define RTE_SPI1_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI1_MICROWIRE_FRF_ENABLE + +// SPI1 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI1 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI1_MW_TRANSFER_MODE 0 + +// SPI1 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI1 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI1_MW_HANDSAHKE_ENABLE 0 + +// SPI1 MW Control Frame Size +// Defines MW Control Frame Size for SPI1. +// Default: 0 +#define RTE_SPI1_MW_CFS 16 +#endif // RTE_SPI1_MICROWIRE_FRF_ENABLE + +// SPI1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI1 +// Default: DISABLE +#define RTE_SPI1_DMA_ENABLE 0 + +// SPI1 DMA IRQ priority <0-255> +// Defines SPI1 DMA Interrupt priority +// Default: 0 +#define RTE_SPI1_DMA_IRQ_PRI 0 + +// SPI1 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI1 +// Default: DISABLE +#define RTE_SPI1_BLOCKING_MODE_ENABLE 0 +#endif +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::Drivers:SPI +#define RTE_SPI2 1 + +#ifdef RTE_SPI2 + +// SPI2 IRQ priority <0-255> +// Defines Interrupt priority for SPI2. +// Default: 0 +#define RTE_SPI2_IRQ_PRIORITY 0 + +// SPI2 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI2. +// Default: 0 +#define RTE_SPI2_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI2 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI2. +// Default: 0 +#define RTE_SPI2_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI2 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI2. +// Default: 0 +#define RTE_SPI2_TX_FIFO_THRESHOLD 0 + +// SPI2 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI2. +// Default: 0 +#define RTE_SPI2_RX_FIFO_THRESHOLD 0 + +// SPI2 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// Defines slave selection for SPI2. +// Default: 0 +#define RTE_SPI2_CHIP_SELECTION_PIN 0 + +// SPI2 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI2. +// Default: 0 +#define RTE_SPI2_RX_SAMPLE_DELAY 0 + +// SPI2 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI2. +// Default: 1 +#define RTE_SPI2_SSTE_ENABLE 1 + +// SPI2 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI2_USE_MASTER_SS_SW 0 + +#if RTE_SPI2_USE_MASTER_SS_SW + +// SPI2 SW SS Port <0-15> +// Defines SPI2 port of SS pin in software controlled mode +// Default: 0 +#define RTE_SPI2_SW_SPI_PORT 0 + +// SPI2 SW SS pin number <0-7> +// Defines SPI2 SS pin number in software controlled mode +// Default: 0 +#define RTE_SPI2_SW_SPI_PIN 0 + +// SPI2 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI2. +// Default: 0 +#define RTE_SPI2_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI2_USE_MASTER_SS_SW + +// SPI2 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI2 MicroWire frame format. +// Default: 0 +#define RTE_SPI2_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI2_MICROWIRE_FRF_ENABLE + +// SPI2 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI2 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI2_MW_TRANSFER_MODE 0 + +// SPI2 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI2 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI2_MW_HANDSAHKE_ENABLE 0 + +// SPI2 MW Control Frame Size +// Defines MW Control Frame Size for SPI2. +// Default: 0 +#define RTE_SPI2_MW_CFS 0 +#endif // RTE_SPI2_MICROWIRE_FRF_ENABLE + +// SPI2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI2 +// Default: DISABLE +#define RTE_SPI2_DMA_ENABLE 0 + +// SPI2 DMA IRQ priority <0-255> +// Defines SPI2 DMA Interrupt priority +// Default: 0 +#define RTE_SPI2_DMA_IRQ_PRI 0 + +// SPI2 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI2 +// Default: DISABLE +#define RTE_SPI2_BLOCKING_MODE_ENABLE 0 +#endif +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::Drivers:SPI +#define RTE_SPI3 1 + +#ifdef RTE_SPI3 + +// SPI3 IRQ priority <0-255> +// Defines Interrupt priority for SPI3. +// Default: 0 +#define RTE_SPI3_IRQ_PRIORITY 0 + +// SPI3 TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for SPI3. +// Default: 0 +#define RTE_SPI3_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// SPI3 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for SPI3. +// Default: 0 +#define RTE_SPI3_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// SPI3 TX FIFO threshold <0-15> +// Defines TX FIFO threshold for SPI3. +// Default: 0 +#define RTE_SPI3_TX_FIFO_THRESHOLD 0 + +// SPI3 RX FIFO threshold <0-15> +// Defines RX FIFO threshold for SPI3. +// Default: 0 +#define RTE_SPI3_RX_FIFO_THRESHOLD 0 + +// SPI3 slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// Defines slave selection for SPI3. +// Default: 0 +#define RTE_SPI3_CHIP_SELECTION_PIN 1 + +// SPI3 RX SAMPLE DELAY <0-4> +// Defines RX SAMPLE DELAY for SPI3. +// Default: 0 +#define RTE_SPI3_RX_SAMPLE_DELAY 0 + +// SPI3 Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for SPI3. +// Default: 1 +#define RTE_SPI3_SSTE_ENABLE 1 + +// SPI3 Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_SPI3_USE_MASTER_SS_SW 0 + +#if RTE_SPI3_USE_MASTER_SS_SW + +// SPI3 SW SS Port <0-15> +// Defines SPI3 port of SS pin in software controlled mode +// Default: 0 +#define RTE_SPI3_SW_SPI_PORT 0 + +// SPI3 SW SS pin number <0-7> +// Defines SPI3 SS pin number in software controlled mode +// Default: 0 +#define RTE_SPI3_SW_SPI_PIN 0 + +// SPI3 SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for SPI3. +// Default: 0 +#define RTE_SPI3_SW_SPI_SS_POLARITY 0 +#endif // RTE_SPI3_USE_MASTER_SS_SW + +// SPI3 Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SPI3 MicroWire frame format. +// Default: 0 +#define RTE_SPI3_MICROWIRE_FRF_ENABLE 0 + +#if RTE_SPI3_MICROWIRE_FRF_ENABLE + +// SPI3 MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines SPI3 MicroWire transfer mode. +// Default: 0 +#define RTE_SPI3_MW_TRANSFER_MODE 0 + +// SPI3 MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SPI3 MicroWire handshake enable. +// Default: 0 +#define RTE_SPI3_MW_HANDSAHKE_ENABLE 0 + +// SPI3 MW Control Frame Size +// Defines MW Control Frame Size for SPI3. +// Default: 0 +#define RTE_SPI3_MW_CFS 0 +#endif // RTE_SPI3_MICROWIRE_FRF_ENABLE + +// SPI3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for SPI3 +// Default: DISABLE +#define RTE_SPI3_DMA_ENABLE 0 + +// SPI3 DMA IRQ priority <0-255> +// Defines SPI3 DMA Interrupt priority +// Default: 0 +#define RTE_SPI3_DMA_IRQ_PRI 0 + +// SPI3 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for SPI3 +// Default: DISABLE +#define RTE_SPI3_BLOCKING_MODE_ENABLE 0 +#endif +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] + +// LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] +// Configuration settings for Driver_LPSPI in component ::Drivers:SPI +#if defined(RTSS_HE) + +#define RTE_LPSPI 1 + +#ifdef RTE_LPSPI + +// LPSPI mode configuration +// <0=> SLAVE +// <1=> MASTER +// Configure LPSPI mode. +// Default: 1 +#define RTE_LPSPI_CONFIG_MASTER_SLAVE 1 + +// LPSPI IRQ priority <0-255> +// Defines Interrupt priority for LPSPI. +// Default: 0 +#define RTE_LPSPI_IRQ_PRIORITY 0 + +// LPSPI TX FIFO Start level <0-15> +// Defines TX FIFO transfer start level for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// LPSPI load dummy data +// <0=> DISABLE +// <1=> ENABLE +// load dummy data to start transfer for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// LPSPI TX FIFO threshold <0-15> +// Defines TX FIFO threshold for LPSPI. +// Default: 0 +#define RTE_LPSPI_TX_FIFO_THRESHOLD 0 + +// LPSPI RX FIFO threshold <0-15> +// Defines RX FIFO threshold for LPSPI. +// Default: 0 +#define RTE_LPSPI_RX_FIFO_THRESHOLD 0 + +// LPSPI slave selection +// <0=> SS_0 +// <1=> SS_1 +// <2=> SS_2 +// <3=> SS_3 +// <4=> SS_4 +// <5=> SS_5 +// Defines slave selection for LPSPI. +// Default: 0 +#define RTE_LPSPI_CHIP_SELECTION_PIN 0 + +// LPSPI Slave Select Toggle Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines SS state after each data frame for LPSPI. +// Default: 1 +#define RTE_LPSPI_SSTE_ENABLE 1 + +// LPSPI Master SS SW +// <0=> DISABLE +// <1=> ENABLE +// Defines use of SW control slave select. +// Default: 0 +#define RTE_LPSPI_USE_MASTER_SS_SW 0 + +#if RTE_LPSPI_USE_MASTER_SS_SW + +// LPSPI SW SS Port <0-15> +// Defines LPSPI port of SS pin in software controlled mode +// Default: 0 +#define RTE_LPSPI_SW_SPI_PORT 0 + +// LPSPI SW SS pin number <0-7> +// Defines LPSPI SS pin number in software controlled mode +// Default: 0 +#define RTE_LPSPI_SW_SPI_PIN 0 + +// LPSPI SW SS Polarity +// <0=> ACTIVE LOW +// <1=> ACTIVE HIGH +// Defines SW controlled slave select polarity for LPSPI. +// Default: 0 +#define RTE_LPSPI_SW_SPI_SS_POLARITY 0 +#endif // RTE_LPSPI_USE_MASTER_SS_SW + +// LPSPI Enable MicroWire FRF +// <0=> DISABLE +// <1=> ENABLE +// Defines use of LPSPI MicroWire frame format. +// Default: 0 +#define RTE_LPSPI_MICROWIRE_FRF_ENABLE 0 + +#if RTE_LPSPI_MICROWIRE_FRF_ENABLE + +// LPSPI MW Transfer Mode +// <0=> NON-SEQUENTIAL MODE +// <1=> SEQUENTIAL MODE +// Defines LPSPI MicroWire transfer mode. +// Default: 0 +#define RTE_LPSPI_MW_TRANSFER_MODE 0 + +// LPSPI MW Handshake Enable +// <0=> DISABLE +// <1=> ENABLE +// Defines LPSPI MicroWire handshake enable. +// Default: 0 +#define RTE_LPSPI_MW_HANDSAHKE_ENABLE 0 + +// LPSPI MW Control Frame Size +// Defines MW Control Frame Size for LPSPI. +// Default: 0 +#define RTE_LPSPI_MW_CFS 8 +#endif // RTE_LPSPI_MICROWIRE_FRF_ENABLE + +// LPSPI DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPSPI +// Default: DISABLE +#define RTE_LPSPI_DMA_ENABLE 0 +#if RTE_LPSPI_DMA_ENABLE + +// LPSPI DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPSPI. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPSPI_SELECT_DMA0 0 +#if RTE_LPSPI_SELECT_DMA0 + +// LPSPI DMA0 Group Selection +// <1=> DMA0_GROUP_1 +// <2=> DMA0_GROUP_2 +// Defines DMA0 Group for LPSPI. By default DMA0 Group 1 will be considered +// Default: DMA0_GROUP_1 +#define RTE_LPSPI_SELECT_DMA0_GROUP 1 +#endif // RTE_LPSPI_SELECT_DMA0 +#endif // RTE_LPSPI_DMA_ENABLE + +// LPSPI DMA IRQ priority <0-255> +// Defines LPSPI DMA Interrupt priority +// Default: 0 +#define RTE_LPSPI_DMA_IRQ_PRI 0 + +// LPSPI blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPSPI +// Default: DISABLE +#define RTE_LPSPI_BLOCKING_MODE_ENABLE 0 +#endif // RTE_LPSPI +#endif // RTSS_HE + +// LPSPI (Low Power Serial Peripheral Interface) [Driver_LPSPI] +// SPI (Serial Peripheral Interface) + +// OSPI (Octal Serial Peripheral Interface) +// OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] +// Configuration settings for Driver_OSPI in component ::Drivers:OSPI +#define RTE_OSPI0 1 +#if RTE_OSPI0 +// OSPI0 IRQ priority <0-255> +// Defines OSPI0 Interrupt priority +// Default: 0 +#define RTE_OSPI0_IRQ_PRIORITY 0 + +// OSPI0 Frame format +// <0=> Standard SPI FRF +// <1=> Dual SPI FRF +// <2=> Quad SPI FRF +// <3=> Octal SPI FRF +// <4=> Dual Octal SPI FRF +// Defines OSPI0 Frame format +// Default: Octal SPI FRF +#define RTE_OSPI0_SPI_FRAME_FORMAT 3 + +// OSPI0 Bus speed +// Defines the OSPI0 Bus speed +// Default: 100000000 +#define RTE_OSPI0_BUS_SPEED 100000000 + +// OSPI0 Wait Cycles +// Defines the OSPI0 Wait Cycles for connected device +// Default: 6 +#define RTE_OSPI0_WAIT_CYCLES 6 + +// OSPI0 DFS +// Defines OSPI0 Data Frame Size +// Default: 32 +#define RTE_OSPI0_DFS 32 + +// OSPI0 TX FIFO Start level <0-255> +// Defines TX FIFO transfer start level for OSPI0 +// Default: 0 +#define RTE_OSPI0_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// OSPI0 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// Load dummy data to start transfer for OSPI0 +// Default: DISABLE +#define RTE_OSPI0_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// OSPI0 TX FIFO threshold <0-255> +// Defines TX FIFO threshold for OSPI0 +// Default: 64 +#define RTE_OSPI0_TX_FIFO_THRESHOLD 64 + +// OSPI0 RX FIFO threshold <0-255> +// Defines RX FIFO threshold for OSPI0 +// Default: 0 +#define RTE_OSPI0_RX_FIFO_THRESHOLD 0 + +// OSPI0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Enable DMA for OSPI0 +// Default: DISABLE +#define RTE_OSPI0_DMA_ENABLE 0 +#if RTE_OSPI0_DMA_ENABLE + +// OSPI0 TX DMA Data level +// Defines TX DMA Data level for OSPI0 +// Default: 64 +#define RTE_OSPI0_TX_DMA_DATA_LEVEL 64 + +// OSPI0 RX DMA Data level +// Defines RX DMA Data level for OSPI0 +// Default: 15 +#define RTE_OSPI0_RX_DMA_DATA_LEVEL 15 + +// OSPI0 DMA IRQ priority <0-255> +// Defines OSPI0 DMA Interrupt priority +// Default: 0 +#define RTE_OSPI0_DMA_IRQ_PRIORITY 0 +#endif + +// OSPI0 slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for OSPI0 +// Default: 0 +#define RTE_OSPI0_CHIP_SELECTION_PIN 0 + +// OSPI0 RX SAMPLE DELAY +// Defines RX SAMPLE DELAY for OSPI0 +// Default: 0 +#define RTE_OSPI0_RX_SAMPLE_DELAY 0 + +// OSPI0 DDR DRIVE EDGE +// Defines DDR DRIVE EDGE for OSPI0 +// Default: 0 +#define RTE_OSPI0_DDR_DRIVE_EDGE 1 + +// OSPI0 RXDS Delay <0-23> +// Defines the delay applied to the RXDS signal of OSPI0 +// Default: 0 +#define RTE_OSPI0_RXDS_DELAY 11 + +// OSPI0 Signal Delay <0-23> +// Defines the delay applied to signals of OSPI0 +// Default: 0 +#define RTE_OSPI0_SIGNAL_DELAY 22 +#endif +// OSPI0 (Octal Serial Peripheral Interface 0) [Driver_OSPI] + +// OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] +// Configuration settings for Driver_OSPI in component ::Drivers:OSPI +#define RTE_OSPI1 1 +#if RTE_OSPI1 +// OSPI1 IRQ priority <0-255> +// Defines OSPI1 Interrupt priority +// Default: 0 +#define RTE_OSPI1_IRQ_PRIORITY 0 + +// OSPI1 Frame format +// <0=> Standard SPI FRF +// <1=> Dual SPI FRF +// <2=> Quad SPI FRF +// <3=> Octal SPI FRF +// <4=> Dual Octal SPI FRF +// Defines OSPI0 Frame format +// Default: Octal SPI FRF +#define RTE_OSPI1_SPI_FRAME_FORMAT 3 + +// OSPI1 Bus speed +// Defines the OSPI1 Bus speed +// Default: 100000000 +#define RTE_OSPI1_BUS_SPEED 100000000 + +// OSPI1 Wait Cycles +// Defines the OSPI1 Wait Cycles for connected device +// Default: 16 +#define RTE_OSPI1_WAIT_CYCLES 3 + +// OSPI1 DFS +// Defines OSPI1 Data Frame Size +// Default: 32 +#define RTE_OSPI1_DFS 32 + +// OSPI1 TX FIFO Start level <0-255> +// Defines TX FIFO transfer start level for OSPI1 +// Default: 0 +#define RTE_OSPI1_TX_FIFO_LEVEL_TO_START_TRANSFER 0 + +// OSPI1 load dummy data +// <0=> DISABLE +// <1=> ENABLE +// Load dummy data to start transfer for OSPI1 +// Default: DISABLE +#define RTE_OSPI1_TX_LOAD_DUMMY_TO_START_LEVEL 0 + +// OSPI1 TX FIFO threshold <0-255> +// Defines TX FIFO threshold for OSPI1 +// Default: 64 +#define RTE_OSPI1_TX_FIFO_THRESHOLD 64 + +// OSPI1 RX FIFO threshold <0-255> +// Defines RX FIFO threshold for OSPI1 +// Default: 0 +#define RTE_OSPI1_RX_FIFO_THRESHOLD 0 + +// OSPI1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Enable DMA for OSPI1 +// Default: DISABLE +#define RTE_OSPI1_DMA_ENABLE 0 +#if RTE_OSPI1_DMA_ENABLE + +// OSPI1 TX DMA Data level +// Defines TX DMA Data level for OSPI1 +// Default: 130 +#define RTE_OSPI1_TX_DMA_DATA_LEVEL 130 + +// OSPI1 RX DMA Data level +// Defines RX DMA Data level for OSPI1 +// Default: 15 +#define RTE_OSPI1_RX_DMA_DATA_LEVEL 15 + +// OSPI1 DMA IRQ priority <0-255> +// Defines OSPI1 DMA Interrupt priority +// Default: 0 +#define RTE_OSPI1_DMA_IRQ_PRIORITY 0 +#endif + +// OSPI1 slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for OSPI1. +// Default: 0 +#define RTE_OSPI1_CHIP_SELECTION_PIN 0 + +// OSPI1 RX SAMPLE DELAY +// Defines RX SAMPLE DELAY for OSPI1 +// Default: 0 +#define RTE_OSPI1_RX_SAMPLE_DELAY 0 + +// OSPI1 DDR DRIVE EDGE +// Defines DDR DRIVE EDGE for OSPI1 +// Default: 1 +#define RTE_OSPI1_DDR_DRIVE_EDGE 1 + +// OSPI1 RXDS Delay <0-23> +// Defines the delay applied to the RXDS signal of OSPI1 +// Default: 11 +#define RTE_OSPI1_RXDS_DELAY 11 + +// OSPI1 Signal Delay <0-23> +// Defines the delay applied to signals of OSPI1 +// Default: 0 +#define RTE_OSPI1_SIGNAL_DELAY 0 +#endif +// OSPI1 (Octal Serial Peripheral Interface 1) [Driver_OSPI] +// OSPI (Octal Serial Peripheral Interface) + +// FLASH +// FLASH (ISSI FLASH) [Driver_Flash] +// Configuration settings for Driver_Flash in component ::Drivers:Flash +#define RTE_ISSI_FLASH 1 +#if RTE_ISSI_FLASH + +// ISSI FLASH SIZE +// ISSI flash density in bytes +// Default: 0x4000000 +#define RTE_ISSI_FLASH_SIZE 0x4000000 + +// ISSI FLASH OSPI Instance +// Defines the OSPI controller instance the ISSI flash is connected to +// Default: 1 +#define RTE_ISSI_FLASH_OSPI_DRV_NUM 1 + +// ISSI FLASH OSPI Bus speed +// Defines the OSPI Bus speed +// Default: 100000000 +#define RTE_ISSI_FLASH_OSPI_BUS_SPEED 100000000 + +// ISSI FLASH Wait cycles +// Defines the number of wait (dummy) cycles needed for fast read operations +// Default: 16 +#define RTE_ISSI_FLASH_WAIT_CYCLES 16 +#endif +// FLASH (ISSI FLASH) [Driver_Flash] + +// FLASH (MX66UW1G FLASH) [Driver_MX66UW1G_FLASH] +// Configuration settings for Driver_MX66UW1G_FLASH in component ::Drivers:Flash +#define RTE_MX66UW1G_FLASH 1 +#if RTE_MX66UW1G_FLASH + +// MX66UW1G FLASH SIZE +// MX66UW1G flash density in bytes +// Default: 0x4000000 +#define RTE_MX66UW1G_FLASH_SIZE 0x4000000 + +// MX66UW1G FLASH OSPI Instance +// Defines the OSPI controller instance the MX66UW1G flash is connected to +// Default: 1 +#define RTE_MX66UW1G_FLASH_OSPI_DRV_NUM 1 + +// MX66UW1G FLASH OSPI Bus speed +// Defines the OSPI Bus speed +// Default: 100000000 +#define RTE_MX66UW1G_FLASH_OSPI_BUS_SPEED 100000000 + +// MX66UW1G FLASH Wait cycles +// Defines the number of wait (dummy) cycles needed for fast read operations +// Default: 10 +#define RTE_MX66UW1G_FLASH_WAIT_CYCLES 10 +#endif +// FLASH (MX66UW1G FLASH) [Driver_MX66UW1G_FLASH] +// FLASH + +// APS512XXN PSRAM +// APS512XXN PSRAM [Driver_APS512XXN_PSRAM] +// Configuration settings for Driver_APS512XXN_PSRAM in component ::Drivers:APS512XXN_PSRAM +#define RTE_APS512XXN_PSRAM 1 +#if RTE_APS512XXN_PSRAM + +// APS512XXN PSRAM Wait cycles +// Defines the number of wait cycles needed for fast read write operations. +// Default: 4 +#define RTE_APS512XXN_PSRAM_WAIT_CYCLES 4 + +// APS512XXN PSRAM Enable Dual Octal Mode +// <0=> Disable +// <1=> Enable +// Defines APS512XXN PSRAM SPI Mode. +// Default: 0 +#define RTE_APS512XXN_PSRAM_DUAL_OCTAL_MODE_ENABLE 1 + +// APS512XXN PSRAM OSPI slave selection +// <0=> SS_0 +// <1=> SS_1 +// Defines the slave select line for APS512XXN PSRAM. +// Default: 0 +#define RTE_APS512XXN_PSRAM_OSPI_SS_LINE 0 +#endif +// APS512XXN PSRAM [Driver_APS512XXN_PSRAM] +// APS512XXN PSRAM + +// S80K HYPERRAM +// S80K HYPERRAM [Driver_S80K_HYPERRAM] +// Configuration settings for Driver_S80K_HYPERRAM in component ::Drivers:S80K_HYPERRAM +#define RTE_S80K_HYPERRAM 1 +#if RTE_S80K_HYPERRAM + +// S80K HYPERRAM Wait cycles +// Defines the number of wait cycles needed for fast read write operations. +// Default: 3 +#define RTE_S80K_HYPERRAM_WAIT_CYCLES 3 + +// S80K HYPERRAM SPI MODE +// <0=> Octal mode +// <1=> Dual Octal mode +// Defines S80K HYPERRAM SPI Mode. +// Default: 0 +#define RTE_S80K_HYPERRAM_SPI_MODE 1 +#endif +// S80K HYPERRAM [Driver_S80K_HYPERRAM] +// S80K HYPERRAM + +// I2S (Integrated Interchip Sound) +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] +// Configuration settings for Driver_SAI0 in component ::Drivers:SAI +#define RTE_I2S0 1 + +#if RTE_I2S0 + +// I2S0 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S0 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S0_WSS_CLOCK_CYCLES 2 + +// I2S0 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S0 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S0_SCLKG_CLOCK_CYCLES 0 + +// I2S0 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S0 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S0_RX_TRIG_LVL 7 + +// I2S0 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S0 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S0_TX_TRIG_LVL 8 + +// I2S0 IRQ priority <0-255> +// Defines I2S0 Interrupt priority +// Default: 0 +#define RTE_I2S0_IRQ_PRI 0 + +// I2S0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S0 +// Default: ENABLE +#define RTE_I2S0_DMA_ENABLE 0 + +// I2S0 DMA IRQ priority <0-255> +// Defines I2S0 DMA Interrupt priority +// Default: 0 +#define RTE_I2S0_DMA_IRQ_PRI 0 + +// I2S0 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S0 +// Default: DISABLE +#define RTE_I2S0_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S0 (Integrated Interchip Sound 0) [Driver_SAI0] + +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] +// Configuration settings for Driver_SAI1 in component ::Drivers:SAI +#define RTE_I2S1 1 + +#if RTE_I2S1 + +// I2S1 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S1 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S1_WSS_CLOCK_CYCLES 2 + +// I2S1 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S1 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S1_SCLKG_CLOCK_CYCLES 0 + +// I2S1 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S1 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S1_RX_TRIG_LVL 7 + +// I2S1 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S1 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S1_TX_TRIG_LVL 8 + +// I2S1 IRQ priority <0-255> +// Defines I2S1 Interrupt priority +// Default: 1 +#define RTE_I2S1_IRQ_PRI 1 + +// I2S1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S1 +// Default: ENABLE +#define RTE_I2S1_DMA_ENABLE 0 + +// I2S1 DMA IRQ priority <0-255> +// Defines I2S1 DMA Interrupt priority +// Default: 0 +#define RTE_I2S1_DMA_IRQ_PRI 0 + +// I2S1 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S1 +// Default: DISABLE +#define RTE_I2S1_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S1 (Integrated Interchip Sound 1) [Driver_SAI1] + +// I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] +// Configuration settings for Driver_SAI2 in component ::Drivers:SAI +#define RTE_I2S2 1 + +#if RTE_I2S2 + +// I2S2 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S2 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S2_WSS_CLOCK_CYCLES 2 + +// I2S2 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S2 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S2_SCLKG_CLOCK_CYCLES 0 + +// I2S2 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S2 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S2_RX_TRIG_LVL 7 + +// I2S2 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S2 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S2_TX_TRIG_LVL 8 + +// I2S2 IRQ priority <0-255> +// Defines I2S2 Interrupt priority +// Default: 0 +#define RTE_I2S2_IRQ_PRI 10 + +// I2S2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S2 +// Default: ENABLE +#define RTE_I2S2_DMA_ENABLE 0 + +// I2S2 DMA IRQ priority <0-255> +// Defines I2S2 DMA Interrupt priority +// Default: 0 +#define RTE_I2S2_DMA_IRQ_PRI 0 + +// I2S2 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S2 +// Default: DISABLE +#define RTE_I2S2_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S2 (Integrated Interchip Sound 2) [Driver_SAI2] + +// I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] +// Configuration settings for Driver_SAI3 in component ::Drivers:SAI +#define RTE_I2S3 1 + +#if RTE_I2S3 + +// I2S3 WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines I2S3 size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_I2S3_WSS_CLOCK_CYCLES 2 + +// I2S3 SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines I2S3 SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_I2S3_SCLKG_CLOCK_CYCLES 0 + +// I2S3 RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S3 receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_I2S3_RX_TRIG_LVL 7 + +// I2S3 TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines I2S3 transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_I2S3_TX_TRIG_LVL 8 + +// I2S3 IRQ priority <0-255> +// Defines I2S3 Interrupt priority +// Default: 0 +#define RTE_I2S3_IRQ_PRI 0 + +// I2S3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2S3 +// Default: ENABLE +#define RTE_I2S3_DMA_ENABLE 0 + +// I2S3 DMA IRQ priority <0-255> +// Defines I2S3 DMA Interrupt priority +// Default: 0 +#define RTE_I2S3_DMA_IRQ_PRI 0 + +// I2S3 Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for I2S3 +// Default: DISABLE +#define RTE_I2S3_BLOCKING_MODE_ENABLE 0 + +#endif +// I2S3 (Integrated Interchip Sound 3) [Driver_SAI3] + +// LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] +// Configuration settings for Driver_SAILP in component ::Drivers:SAI +#if defined(RTSS_HE) + +#define RTE_LPI2S 1 + +#if RTE_LPI2S + +// LPI2S WORD SELECT SIZE +// <0=> WSS_CLOCK_CYCLES_16 +// <1=> WSS_CLOCK_CYCLES_24 +// <2=> WSS_CLOCK_CYCLES_32 +// Defines LPI2S size of word +// Default: WSS_CLOCK_CYCLES_32 +#define RTE_LPI2S_WSS_CLOCK_CYCLES 2 + +// LPI2S SCLK GATING +// <0=> NO_CLOCK_GATING +// <1=> SCLKG_CLOCK_CYCLES_12 +// <2=> SCLKG_CLOCK_CYCLES_16 +// <3=> SCLKG_CLOCK_CYCLES_20 +// <4=> SCLKG_CLOCK_CYCLES_24 +// Defines LPI2S SCLK Gating +// Default: NO_CLOCK_GATING +#define RTE_LPI2S_SCLKG_CLOCK_CYCLES 0 + +// LPI2S RX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines LPI2S receive fifo trigger level +// Default: TRIGGER_LEVEL_8 +#define RTE_LPI2S_RX_TRIG_LVL 7 + +// LPI2S TX FIFO TRIGGER LEVEL +// <0=> TRIGGER_LEVEL_1 +// <1=> TRIGGER_LEVEL_2 +// <2=> TRIGGER_LEVEL_3 +// <3=> TRIGGER_LEVEL_4 +// <4=> TRIGGER_LEVEL_5 +// <5=> TRIGGER_LEVEL_6 +// <6=> TRIGGER_LEVEL_7 +// <7=> TRIGGER_LEVEL_8 +// <8=> TRIGGER_LEVEL_9 +// <9=> TRIGGER_LEVEL_10 +// <10=> TRIGGER_LEVEL_11 +// <11=> TRIGGER_LEVEL_12 +// <12=> TRIGGER_LEVEL_13 +// <13=> TRIGGER_LEVEL_14 +// <14=> TRIGGER_LEVEL_15 +// <15=> TRIGGER_LEVEL_16 +// Defines LPI2S transfer fifo trigger level +// Default: TRIGGER_LEVEL_9 +#define RTE_LPI2S_TX_TRIG_LVL 8 + +// LPI2S IRQ priority <0-255> +// Defines LPI2S Interrupt priority +// Default: 1 +#define RTE_LPI2S_IRQ_PRI 1 + +// LPI2S DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPI2S +// Default: ENABLE +#define RTE_LPI2S_DMA_ENABLE 0 +#if RTE_LPI2S_DMA_ENABLE + +// LPI2S DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPI2S. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPI2S_SELECT_DMA0 0 +#endif + +// LPI2S DMA IRQ priority <0-255> +// Defines LPI2S DMA Interrupt priority +// Default: 0 +#define RTE_LPI2S_DMA_IRQ_PRI 0 + +// LPI2S Blocking Mode +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPI2S +// Default: DISABLE +#define RTE_LPI2S_BLOCKING_MODE_ENABLE 0 + +#endif // RTE_LPI2S +#endif // defined(RTSS_HE) + +// LPI2S (Low Power Integrated Interchip Sound) [Driver_SAILP] +// I2S (Integrated Interchip Sound) + +// WM8904 Codec [Driver_WM8904] +// Configuration settings for Driver_WM8904 in component ::Drivers:WM8904 +#define RTE_WM8904_CODEC 1 + +#if RTE_WM8904_CODEC + +// Select WM8904 i2c instance +// Defines WM8904 i2c instance +// <0=> I2C0 +// <1=> I2C1 +// <2=> I2C2 +// <3=> I2C3 +// I2C OVER I3C +// Default: 1 +#define RTE_WM8904_CODEC_I2C_INSTANCE 1 +#endif + +// WM8904 Codec [Driver_WM8904] + +// UART (Universal asynchronous receiver transmitter) +// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] +// Configuration settings for Driver_USART0 in component ::Drivers:USART +#define RTE_UART0 1 + +#if RTE_UART0 + +// UART0 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART0 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART0_RX_TRIG_LVL 0 + +// UART0 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART0 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART0_TX_TRIG_LVL 0 + +// UART0 IRQ priority <0-255> +// Defines Interrupt priority for UART0. +// Default: 0 +#define RTE_UART0_IRQ_PRI 0 + +// UART0 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART0 clock source. +// Default: CLK_100MHz +#define RTE_UART0_CLK_SOURCE 1 + +// UART0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART0 +// Default: DISABLE +#define RTE_UART0_DMA_ENABLE 0 + +// UART0 DMA IRQ priority <0-255> +// Defines UART0 DMA Interrupt priority +// Default: 0 +#define RTE_UART0_DMA_IRQ_PRI 0 + +// UART0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART0 +// Default: DISABLE +#define RTE_UART0_BLOCKING_MODE_ENABLE 0 + +#endif // UART0 + +// UART0 (Universal asynchronous receiver transmitter) [Driver_USART0] + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::Drivers:USART +#define RTE_UART1 1 + +#if RTE_UART1 + +// UART1 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART1 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART1_RX_TRIG_LVL 0 + +// UART1 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART1 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART1_TX_TRIG_LVL 0 + +// UART1 IRQ priority <0-255> +// Defines Interrupt priority for UART1. +// Default: 0 +#define RTE_UART1_IRQ_PRI 0 + +// UART1 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART1 clock source. +// Default: CLK_100MHz +#define RTE_UART1_CLK_SOURCE 1 + +// UART1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART1 +// Default: DISABLE +#define RTE_UART1_DMA_ENABLE 0 + +// UART1 DMA IRQ priority <0-255> +// Defines UART1 DMA Interrupt priority +// Default: 0 +#define RTE_UART1_DMA_IRQ_PRI 0 + +// UART1 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART1 +// Default: DISABLE +#define RTE_UART1_BLOCKING_MODE_ENABLE 0 + +#endif // UART1 + +// UART1 (Universal asynchronous receiver transmitter) [Driver_USART1] + +// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::Drivers:USART +#define RTE_UART2 1 + +#if RTE_UART2 + +// UART2 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART2 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART2_RX_TRIG_LVL 0 + +// UART2 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART2 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART2_TX_TRIG_LVL 0 + +// UART2 IRQ priority <0-255> +// Defines Interrupt priority for UART2. +// Default: 0 +#define RTE_UART2_IRQ_PRI 0 + +// UART2 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART2 clock source. +// Default: CLK_100MHz +#define RTE_UART2_CLK_SOURCE 1 + +// UART2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART2 +// Default: DISABLE +#define RTE_UART2_DMA_ENABLE 0 + +// UART2 DMA IRQ priority <0-255> +// Defines UART2 DMA Interrupt priority +// Default: 0 +#define RTE_UART2_DMA_IRQ_PRI 0 + +// UART2 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART2 +// Default: DISABLE +#define RTE_UART2_BLOCKING_MODE_ENABLE 0 + +#endif // UART2 + +// UART2 (Universal asynchronous receiver transmitter) [Driver_USART2] + +// UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::Drivers:USART +#define RTE_UART3 1 + +#if RTE_UART3 + +// UART3 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART3 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART3_RX_TRIG_LVL 0 + +// UART3 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART3 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART3_TX_TRIG_LVL 0 + +// UART3 IRQ priority <0-255> +// Defines Interrupt priority for UART3. +// Default: 0 +#define RTE_UART3_IRQ_PRI 0 + +// UART3 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART3 clock source. +// Default: CLK_100MHz +#define RTE_UART3_CLK_SOURCE 1 + +// UART3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART3 +// Default: DISABLE +#define RTE_UART3_DMA_ENABLE 0 + +// UART3 DMA IRQ priority <0-255> +// Defines UART3 DMA Interrupt priority +// Default: 0 +#define RTE_UART3_DMA_IRQ_PRI 0 + +// UART3 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART3 +// Default: DISABLE +#define RTE_UART3_BLOCKING_MODE_ENABLE 0 + +#endif // UART3 + +// UART3 (Universal asynchronous receiver transmitter) [Driver_USART3] + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] +// Configuration settings for Driver_USART4 in component ::Drivers:USART +#define RTE_UART4 1 + +#if RTE_UART4 + +// UART4 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART4 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART4_RX_TRIG_LVL 0 + +// UART4 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART4 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART4_TX_TRIG_LVL 0 + +// UART4 IRQ priority <0-255> +// Defines Interrupt priority for UART4. +// Default: 0 +#define RTE_UART4_IRQ_PRI 0 + +// UART4 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART4 clock source. +// Default: CLK_100MHz +#define RTE_UART4_CLK_SOURCE 1 + +#define RTE_UART4_RS485_ENABLE 0 +#if RTE_UART4_RS485_ENABLE +#define RTE_UART4_RS485_TRANSFER_MODE 2 +#define RTE_UART4_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART4_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART4_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART4_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART4 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART4 +// Default: DISABLE +#define RTE_UART4_DMA_ENABLE 0 + +// UART4 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART4. By default DMA0 will be considered. +// Default: DMA0 +#define RTE_UART4_SELECT_DMA0 1 + +// UART4 DMA IRQ priority <0-255> +// Defines UART4 DMA Interrupt priority +// Default: 0 +#define RTE_UART4_DMA_IRQ_PRI 0 + +// UART4 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART4 +// Default: DISABLE +#define RTE_UART4_BLOCKING_MODE_ENABLE 0 + +#endif // UART4 + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] +// Configuration settings for Driver_USART5 in component ::Drivers:USART +#define RTE_UART5 1 + +#if RTE_UART5 + +// UART5 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART5 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART5_RX_TRIG_LVL 0 + +// UART5 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART5 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART5_TX_TRIG_LVL 0 + +// UART5 IRQ priority <0-255> +// Defines Interrupt priority for UART5. +// Default: 0 +#define RTE_UART5_IRQ_PRI 0 + +// UART5 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART5 clock source. +// Default: CLK_100MHz +#define RTE_UART5_CLK_SOURCE 1 + +#define RTE_UART5_RS485_ENABLE 0 +#if RTE_UART5_RS485_ENABLE +#define RTE_UART5_RS485_TRANSFER_MODE 2 +#define RTE_UART5_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART5_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART5_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART5_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART5 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART5 +// Default: DISABLE +#define RTE_UART5_DMA_ENABLE 0 + +// UART5 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART5. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART5_SELECT_DMA0 1 + +// UART5 DMA IRQ priority <0-255> +// Defines UART5 DMA Interrupt priority +// Default: 0 +#define RTE_UART5_DMA_IRQ_PRI 0 + +// UART5 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART5 +// Default: DISABLE +#define RTE_UART5_BLOCKING_MODE_ENABLE 0 + +#endif // UART5 + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] + +// UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] +// Configuration settings for Driver_USART6 in component ::Drivers:USART +#define RTE_UART6 1 + +#if RTE_UART6 + +// UART6 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART6 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART6_RX_TRIG_LVL 0 + +// UART6 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART6 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART6_TX_TRIG_LVL 0 + +// UART6 IRQ priority <0-255> +// Defines Interrupt priority for UART6. +// Default: 0 +#define RTE_UART6_IRQ_PRI 0 + +// UART6 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART6 clock source. +// Default: CLK_100MHz +#define RTE_UART6_CLK_SOURCE 1 + +#define RTE_UART6_RS485_ENABLE 0 +#if RTE_UART6_RS485_ENABLE +#define RTE_UART6_RS485_TRANSFER_MODE 2 +#define RTE_UART6_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART6_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART6_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART6_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART6 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART6 +// Default: DISABLE +#define RTE_UART6_DMA_ENABLE 0 + +// UART6 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART6. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART6_SELECT_DMA0 1 + +// UART6 DMA IRQ priority <0-255> +// Defines UART6 DMA Interrupt priority +// Default: 0 +#define RTE_UART6_DMA_IRQ_PRI 0 + +// UART6 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART6 +// Default: DISABLE +#define RTE_UART6_BLOCKING_MODE_ENABLE 0 + +#endif // UART6 + +// UART6 (Universal asynchronous receiver transmitter) [Driver_USART6] + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] +// Configuration settings for Driver_USART7 in component ::Drivers:USART +#define RTE_UART7 1 + +#if RTE_UART7 + +// UART7 RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines UART7 receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_UART7_RX_TRIG_LVL 0 + +// UART7 TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines UART7 transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_UART7_TX_TRIG_LVL 0 + +// UART7 IRQ priority <0-255> +// Defines Interrupt priority for UART7. +// Default: 0 +#define RTE_UART7_IRQ_PRI 0 + +// UART7 CLK SOURCE +// <0=> CLK_38.4MHz +// <1=> CLK_100MHz +// Defines UART7 clock source. +// Default: CLK_100MHz +#define RTE_UART7_CLK_SOURCE 1 + +#define RTE_UART7_RS485_ENABLE 0 +#if RTE_UART7_RS485_ENABLE +#define RTE_UART7_RS485_TRANSFER_MODE 2 +#define RTE_UART7_RS485_DE_ASSERTION_TIME_8BIT (0x01) +#define RTE_UART7_RS485_DE_DEASSERTION_TIME_8BIT (0x01) +#define RTE_UART7_RS485_DE_TO_RE_TURN_AROUND_TIME_16BIT (0x01) +#define RTE_UART7_RS485_RE_TO_DE_TURN_AROUND_TIME_16BIT (0x03) +#endif + +// UART7 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for UART7 +// Default: DISABLE +#define RTE_UART7_DMA_ENABLE 0 + +// UART7 DMA Selection +// <0=> DMA1(M55-HP) +// <1=> DMA0 +// Defines Select DMA0 for UART7. By default DMA0 will be considered +// Default: DMA0 +#define RTE_UART7_SELECT_DMA0 1 + +// UART7 DMA IRQ priority <0-255> +// Defines UART7 DMA Interrupt priority +// Default: 0 +#define RTE_UART7_DMA_IRQ_PRI 0 + +// UART7 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for UART7 +// Default: DISABLE +#define RTE_UART7_BLOCKING_MODE_ENABLE 0 + +#endif // UART7 + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] + +// LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] +// Configuration settings for Driver_USARTLP in component ::Drivers:USART +#if defined(RTSS_HE) +#define RTE_LPUART 1 +#endif + +#if RTE_LPUART + +// LPUART RX FIFO TRIGGER LEVEL +// <0=> UART_RX_ONE_CHAR_IN_FIFO +// <1=> UART_RX_FIFO_QUARTER_FULL +// <2=> UART_RX_FIFO_HALF_FULL +// <3=> UART_RX_FIFO_TWO_LESS_FULL +// Defines LPUART receive fifo trigger level. +// Default: UART_RX_ONE_CHAR_IN_FIFO +#define RTE_LPUART_RX_TRIG_LVL 0 + +// LPUART TX FIFO TRIGGER LEVEL +// <0=> UART_TX_FIFO_EMPTY +// <1=> UART_TX_FIFO_CHAR_2 +// <2=> UART_TX_FIFO_QUARTER_FULL +// <3=> UART_TX_FIFO_HALF_FULL +// Defines LPUART transmit fifo trigger level. +// Default: UART_TX_FIFO_EMPTY +#define RTE_LPUART_TX_TRIG_LVL 0 + +// LPUART IRQ priority <0-255> +// Defines Interrupt priority for LPUART. +// Default: 0 +#define RTE_LPUART_IRQ_PRI 0 + +// LPUART DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPUART +// Default: DISABLE +#define RTE_LPUART_DMA_ENABLE 0 + +// LPUART DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPUART. By default DMA0 will be considered +// Default: DMA0 +#define RTE_LPUART_SELECT_DMA0 1 + +// LPUART DMA IRQ priority <0-255> +// Defines LPUART DMA Interrupt priority +// Default: 0 +#define RTE_LPUART_DMA_IRQ_PRI 0 + +// LPUART blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for LPUART +// Default: DISABLE +#define RTE_LPUART_BLOCKING_MODE_ENABLE 0 + +#endif // RTE_LPUART + +// LPUART (Low-Power Universal asynchronous receiver transmitter) [Driver_USARTLP] +// UART (Universal asynchronous receiver transmitter) + +// LPTIMER (Low power timer) +// LPTIMER (Low power timer) [Driver_LPTIMER] +// Configuration settings for Driver_LPTIMER in component ::Drivers:LPTIMER +#define RTE_LPTIMER 1 + +#if RTE_LPTIMER + +// LPTIMER CHANNEL 0 +// Configuration settings for Driver_LPTIMER channel 0 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL0 1 + +// CHANNEL0 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 0. +// Default: 0 +#define RTE_LPTIMER_CHANNEL0_IRQ_PRIORITY (0) + +// CHANNEL0 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel0. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL0_FREE_RUN_MODE (0) + +// CHANNEL0 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// Defines clock source for channel0. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL0_CLK_SRC (0) +// LPTIMER CHANNEL 0 + +// LPTIMER CHANNEL 1 +// Configuration settings for Driver_LPTIMER channel 1 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL1 1 + +// CHANNEL1 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 1. +// Default: 0 +#define RTE_LPTIMER_CHANNEL1_IRQ_PRIORITY (0) + +// CHANNEL1 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel1. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL1_FREE_RUN_MODE (0) + +// CHANNEL1 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// <3=> CLK_CASCADE +// Defines clock source for channel1. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL1_CLK_SRC (0) +// LPTIMER CHANNEL 1 + +// LPTIMER CHANNEL 2 +// Configuration settings for Driver_LPTIMER channel 2 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL2 1 + +// CHANNEL2 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 2. +// Default: 0 +#define RTE_LPTIMER_CHANNEL2_IRQ_PRIORITY (0) + +// CHANNEL2 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel2. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL2_FREE_RUN_MODE (0) + +// CHANNEL2 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// Defines clock source for channel2. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL2_CLK_SRC (0) +// LPTIMER CHANNEL 2 + +// LPTIMER CHANNEL 3 +// Configuration settings for Driver_LPTIMER channel 3 in component ::Drivers:LPTIMER +#define RTE_LPTIMER_CHANNEL3 1 + +// CHANNEL3 IRQ priority <0-255> +// Defines Interrupt priority for LPTIMER channel 3. +// Default: 0 +#define RTE_LPTIMER_CHANNEL3_IRQ_PRIORITY (0) + +// CHANNEL3 FREE RUN feature +// <0=> DISABLED +// <1=> ENABLED +// Defines whether free run feature is not enabled/disabled for channel3. +// Default: DISABLED +#define RTE_LPTIMER_CHANNEL3_FREE_RUN_MODE (0) + +// CHANNEL3 clock source +// <0=> CLK_32768Hz +// <1=> CLK_128KHz +// <2=> EXT_CLK +// <3=> CLK_CASCADE +// Defines clock source for channel3. +// Default: CLK_32768Hz +#define RTE_LPTIMER_CHANNEL3_CLK_SRC (0) +// LPTIMER CHANNEL 3 +#endif /* RTE_LPTIMER */ +// LPTIMER (Low power timer) [Driver_LPTIMER] +// LPTIMER (Low power timer) + +// RTC (Real time clock) +// RTC0 (Real time clock) [Driver_RTC0] +// Configuration settings for Driver_RTC0 in component ::Drivers:RTC +#define RTE_RTC0 1 + +#if RTE_RTC0 + +// RTC0 IRQ priority <0-255> +// Defines Interrupt priority for RTC0. +// Default: 0 +#define RTE_RTC0_IRQ_PRI 0 +#endif +// RTC0 (Real time clock) [Driver_RTC0] +// RTC (Real time clock) + +// WDT (Watchdog Timer) +// WDT0 (Watchdog Timer) [Driver_WDT0] +// Configuration settings for Driver_WDT0 in component ::Drivers:WDT +#define RTE_WDT0 1 +// WDT0 (Watchdog Timer) [Driver_WDT0] +// WDT (Watchdog Timer) + +// UTIMER (Universal Timer) +// UTIMER (Universal Timer) [Driver_UTIMER] +// Configuration settings for Driver_UTIMER in component ::Drivers:UTIMER +#define RTE_UTIMER 1 + +#if RTE_UTIMER + +// UTIMER CHANNEL 0 +// Configuration settings for UTIMER channel 0 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL0 1 + +// CHANNEL0 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_FIXED_BUFFER 0 + +// CHANNEL0 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DMA_CLEAR_ENABLE 0 + +// CHANNEL0 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 0. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL0_FAULT_TYPE 0 + +// CHANNEL0 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 0. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL0_BUF_TROUGH_N_CREST 0 + +// CHANNEL0 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DRIVER_A 1 + +// CHANNEL0 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL0_DRIVER_B 0 + +// CHANNEL0 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_A_START_STATE 0 + +// CHANNEL0 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_A_STOP_STATE 0 + +// CHANNEL0 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL0 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_B_START_STATE 0 + +// CHANNEL0 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 0. +// Default: LOW +#define RTE_UTIMER_CHANNEL0_DRV_B_STOP_STATE 0 + +// CHANNEL0 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL0 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 0. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL0_EVENT_AT_CREST 1 + +// CHANNEL0 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_EVENT_AT_TROUGH 0 + +// CHANNEL0 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 0. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE 0 + +// CHANNEL0 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 0. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL0_BUFFER_OPERATION 0 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 0 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_A 2 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 0 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL0_BUFFERING_TYPE_B 0 + +// CHANNEL0 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL0 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL0_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_ENABLE 0 + +// CHANNEL0 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 0. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL0_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 0 + +// UTIMER CHANNEL 1 +// Configuration settings for UTIMER channel 1 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL1 1 + +// CHANNEL1 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_FIXED_BUFFER 0 + +// CHANNEL1 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DMA_CLEAR_ENABLE 0 + +// CHANNEL1 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 1. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL1_FAULT_TYPE 0 + +// CHANNEL1 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL1_BUF_TROUGH_N_CREST 0 + +// CHANNEL1 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DRIVER_A 0 + +// CHANNEL1 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 1. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL1_DRIVER_B 0 + +// CHANNEL1 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_A_START_STATE 0 + +// CHANNEL1 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_A_STOP_STATE 0 + +// CHANNEL1 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL1 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_B_START_STATE 0 + +// CHANNEL1 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 1. +// Default: LOW +#define RTE_UTIMER_CHANNEL1_DRV_B_STOP_STATE 0 + +// CHANNEL1 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL1 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 1. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL1_EVENT_AT_CREST 1 + +// CHANNEL1 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_EVENT_AT_TROUGH 0 + +// CHANNEL1 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 1. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE 1 + +// CHANNEL1 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 1. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL1_BUFFER_OPERATION 1 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 1 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_A 0 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 1 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL1_BUFFERING_TYPE_B 0 + +// CHANNEL1 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL1 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 1 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL1 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 1 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL1 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 1 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL1_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL1 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_ENABLE 0 + +// CHANNEL1 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 1. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL1_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 1 + +// UTIMER CHANNEL 2 +// Configuration settings for UTIMER channel 2 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL2 1 + +// CHANNEL2 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_FIXED_BUFFER 0 + +// CHANNEL2 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DMA_CLEAR_ENABLE 0 + +// CHANNEL2 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 2. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL2_FAULT_TYPE 0 + +// CHANNEL2 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 2. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL2_BUF_TROUGH_N_CREST 0 + +// CHANNEL2 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DRIVER_A 0 + +// CHANNEL2 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 2. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL2_DRIVER_B 0 + +// CHANNEL2 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_A_START_STATE 0 + +// CHANNEL2 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_A_STOP_STATE 0 + +// CHANNEL2 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL2 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_B_START_STATE 0 + +// CHANNEL2 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 2. +// Default: LOW +#define RTE_UTIMER_CHANNEL2_DRV_B_STOP_STATE 0 + +// CHANNEL2 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL2 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 2. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL2_EVENT_AT_CREST 1 + +// CHANNEL2 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_EVENT_AT_TROUGH 0 + +// CHANNEL2 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 2. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE 1 + +// CHANNEL2 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 2. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL2_BUFFER_OPERATION 1 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 2 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_A 2 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 2 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL2_BUFFERING_TYPE_B 0 + +// CHANNEL2 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel2 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL2 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 2 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL2 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 2 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL2 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 2 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL2_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL2 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_ENABLE 0 + +// CHANNEL2 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 2. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL2_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 2 + +// UTIMER CHANNEL 3 +// Configuration settings for UTIMER channel 3 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL3 1 + +// CHANNEL3 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_FIXED_BUFFER 0 + +// CHANNEL3 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 0. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DMA_CLEAR_ENABLE 0 + +// CHANNEL3 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 3. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL3_FAULT_TYPE 0 + +// CHANNEL3 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 3. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL3_BUF_TROUGH_N_CREST 0 + +// CHANNEL3 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DRIVER_A 0 + +// CHANNEL3 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 3. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL3_DRIVER_B 0 + +// CHANNEL3 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_A_START_STATE 0 + +// CHANNEL3 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_A_STOP_STATE 0 + +// CHANNEL3 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL3 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL3 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_B_START_STATE 0 + +// CHANNEL3 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 3. +// Default: LOW +#define RTE_UTIMER_CHANNEL3_DRV_B_STOP_STATE 0 + +// CHANNEL3 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL3 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL3 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 3. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL3_EVENT_AT_CREST 1 + +// CHANNEL3 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_EVENT_AT_TROUGH 0 + +// CHANNEL3 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 3. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE 0 + +// CHANNEL3 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 3. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL3_BUFFER_OPERATION 0 + +// CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 3 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_A 0 + +// CHANNEL3 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 3 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL3_BUFFERING_TYPE_B 0 + +// CHANNEL3 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL3 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 3 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL3 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 3 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL3 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 3 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL3_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL3 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_ENABLE 0 + +// CHANNEL3 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 3. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL3_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 3 + +// UTIMER CHANNEL 4 +// Configuration settings for UTIMER channel 4 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL4 1 + +// CHANNEL4 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_FIXED_BUFFER 0 + +// CHANNEL4 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DMA_CLEAR_ENABLE 0 + +// CHANNEL4 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 4. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL4_FAULT_TYPE 0 + +// CHANNEL4 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL4_BUF_TROUGH_N_CREST 0 + +// CHANNEL4 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DRIVER_A 1 + +// CHANNEL4 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL4_DRIVER_B 0 + +// CHANNEL4 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_A_START_STATE 0 + +// CHANNEL4 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_A_STOP_STATE 0 + +// CHANNEL4 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL4 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL4 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_B_START_STATE 0 + +// CHANNEL4 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 4. +// Default: LOW +#define RTE_UTIMER_CHANNEL4_DRV_B_STOP_STATE 0 + +// CHANNEL4 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL4 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL4 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 4. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL4_EVENT_AT_CREST 1 + +// CHANNEL4 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_EVENT_AT_TROUGH 1 + +// CHANNEL4 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 4. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE 1 + +// CHANNEL4 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 4. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL4_BUFFER_OPERATION 1 + +// CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 4 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_A 2 + +// CHANNEL4 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 4 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL4_BUFFERING_TYPE_B 2 + +// CHANNEL4 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL4 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 4 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL4 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 4 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL4 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 4 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL4_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL4 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_ENABLE 0 + +// CHANNEL4 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 4. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL4_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 4 + +// UTIMER CHANNEL 5 +// Configuration settings for UTIMER channel 5 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL5 1 + +// CHANNEL5 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_FIXED_BUFFER 0 + +// CHANNEL5 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 4. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DMA_CLEAR_ENABLE 0 + +// CHANNEL5 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 5. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL5_FAULT_TYPE 0 + +// CHANNEL5 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 5. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL5_BUF_TROUGH_N_CREST 0 + +// CHANNEL5 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DRIVER_A 1 + +// CHANNEL5 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 5. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL5_DRIVER_B 0 + +// CHANNEL5 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_A_START_STATE 0 + +// CHANNEL5 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_A_STOP_STATE 0 + +// CHANNEL5 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_MATCH_COUNT 3 + +// CHANNEL5 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_A_OP_AT_CYCLE_END 3 + +// CHANNEL5 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_B_START_STATE 0 + +// CHANNEL5 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 5. +// Default: LOW +#define RTE_UTIMER_CHANNEL5_DRV_B_STOP_STATE 0 + +// CHANNEL5 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL5 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL5 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 5. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL5_EVENT_AT_CREST 1 + +// CHANNEL5 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_EVENT_AT_TROUGH 0 + +// CHANNEL5 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 5. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE 1 + +// CHANNEL5 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 5. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL5_BUFFER_OPERATION 1 + +// CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 5 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_A 2 + +// CHANNEL5 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 5 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL5_BUFFERING_TYPE_B 0 + +// CHANNEL5 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL5 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 5 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL5 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 5 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL5 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 5 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL5_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL5 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_ENABLE 0 + +// CHANNEL5 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 5. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL5_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 5 + +// UTIMER CHANNEL 6 +// Configuration settings for UTIMER channel 6 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL6 1 + +// CHANNEL6 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_FIXED_BUFFER 0 + +// CHANNEL6 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DMA_CLEAR_ENABLE 0 + +// CHANNEL6 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 6. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL6_FAULT_TYPE 0 + +// CHANNEL6 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 6. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL6_BUF_TROUGH_N_CREST 0 + +// CHANNEL6 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DRIVER_A 1 + +// CHANNEL6 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 6. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL6_DRIVER_B 0 + +// CHANNEL6 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_A_START_STATE 0 + +// CHANNEL6 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_A_STOP_STATE 0 + +// CHANNEL6 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_MATCH_COUNT 3 + +// CHANNEL6 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_A_OP_AT_CYCLE_END 3 + +// CHANNEL6 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_B_START_STATE 0 + +// CHANNEL6 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 6. +// Default: LOW +#define RTE_UTIMER_CHANNEL6_DRV_B_STOP_STATE 0 + +// CHANNEL6 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL6 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL6 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 6. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL6_EVENT_AT_CREST 1 + +// CHANNEL6 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_EVENT_AT_TROUGH 0 + +// CHANNEL6 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 6. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE 0 + +// CHANNEL6 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 6. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL6_BUFFER_OPERATION 0 + +// CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 6 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_A 0 + +// CHANNEL6 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 6 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL6_BUFFERING_TYPE_B 0 + +// CHANNEL6 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL6 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 6 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL6 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 6 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL6 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 6 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL6_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL6 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_ENABLE 0 + +// CHANNEL6 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 6. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL6_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 6 + +// UTIMER CHANNEL 7 +// Configuration settings for UTIMER channel 7 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL7 1 + +// CHANNEL7 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_FIXED_BUFFER 0 + +// CHANNEL7 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DMA_CLEAR_ENABLE 0 + +// CHANNEL7 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 7. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL7_FAULT_TYPE 0 + +// CHANNEL7 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 7. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL7_BUF_TROUGH_N_CREST 0 + +// CHANNEL7 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DRIVER_A 0 + +// CHANNEL7 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 7. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL7_DRIVER_B 0 + +// CHANNEL7 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_A_START_STATE 0 + +// CHANNEL7 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_A_STOP_STATE 0 + +// CHANNEL7 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL7 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL7 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_B_START_STATE 0 + +// CHANNEL7 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 7. +// Default: LOW +#define RTE_UTIMER_CHANNEL7_DRV_B_STOP_STATE 0 + +// CHANNEL7 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL7 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL7 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 7. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL7_EVENT_AT_CREST 1 + +// CHANNEL7 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_EVENT_AT_TROUGH 0 + +// CHANNEL7 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 7. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE 1 + +// CHANNEL7 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 7. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL7_BUFFER_OPERATION 1 + +// CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 7 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_A 2 + +// CHANNEL7 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 7 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL7_BUFFERING_TYPE_B 0 + +// CHANNEL7 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL7 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 7 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL7 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 7 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL7 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 7 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL7_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL7 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_ENABLE 0 + +// CHANNEL7 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 7. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL7_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 7 + +// UTIMER CHANNEL 8 +// Configuration settings for UTIMER channel 8 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL8 1 + +// CHANNEL8 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_FIXED_BUFFER 0 + +// CHANNEL8 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DMA_CLEAR_ENABLE 0 + +// CHANNEL8 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 8. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL8_FAULT_TYPE 0 + +// CHANNEL8 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 8. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL8_BUF_TROUGH_N_CREST 0 + +// CHANNEL8 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DRIVER_A 1 + +// CHANNEL8 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 8. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL8_DRIVER_B 0 + +// CHANNEL8 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_A_START_STATE 0 + +// CHANNEL8 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_A_STOP_STATE 0 + +// CHANNEL8 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_MATCH_COUNT 1 + +// CHANNEL8 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_A_OP_AT_CYCLE_END 2 + +// CHANNEL8 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_B_START_STATE 0 + +// CHANNEL8 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 8. +// Default: LOW +#define RTE_UTIMER_CHANNEL8_DRV_B_STOP_STATE 0 + +// CHANNEL8 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL8 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL8 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 8. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL8_EVENT_AT_CREST 1 + +// CHANNEL8 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_EVENT_AT_TROUGH 0 + +// CHANNEL8 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 8. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE 0 + +// CHANNEL8 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 8. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL8_BUFFER_OPERATION 0 + +// CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 8 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_A 2 + +// CHANNEL8 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 8 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL8_BUFFERING_TYPE_B 0 + +// CHANNEL8 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL8 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 8 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL8 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 8 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL8 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 8 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL8_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL8 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_ENABLE 0 + +// CHANNEL8 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 8. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL8_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 8 + +// UTIMER CHANNEL 9 +// Configuration settings for UTIMER channel 9 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL9 1 + +// CHANNEL9 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_FIXED_BUFFER 0 + +// CHANNEL9 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DMA_CLEAR_ENABLE 0 + +// CHANNEL9 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 9. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL9_FAULT_TYPE 0 + +// CHANNEL9 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 9. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL9_BUF_TROUGH_N_CREST 0 + +// CHANNEL9 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DRIVER_A 0 + +// CHANNEL9 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 9. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL9_DRIVER_B 1 + +// CHANNEL9 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_A_START_STATE 0 + +// CHANNEL9 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_A_STOP_STATE 0 + +// CHANNEL9 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL9 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL9 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_B_START_STATE 0 + +// CHANNEL9 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 9. +// Default: LOW +#define RTE_UTIMER_CHANNEL9_DRV_B_STOP_STATE 0 + +// CHANNEL9 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_MATCH_COUNT 1 + +// CHANNEL9 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_DRV_B_OP_AT_CYCLE_END 2 + +// CHANNEL9 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 9. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL9_EVENT_AT_CREST 1 + +// CHANNEL9 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_EVENT_AT_TROUGH 0 + +// CHANNEL9 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 9. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE 0 + +// CHANNEL9 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 9. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL9_BUFFER_OPERATION 0 + +// CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 9 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_A 0 + +// CHANNEL9 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 9 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL9_BUFFERING_TYPE_B 0 + +// CHANNEL9 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL9 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 9 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL9 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 9 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL9 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 9 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL9_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL9 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_ENABLE 0 + +// CHANNEL9 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 9. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL9_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 9 + +// UTIMER CHANNEL 10 +// Configuration settings for UTIMER channel 10 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL10 1 + +// CHANNEL10 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_FIXED_BUFFER 0 + +// CHANNEL10 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DMA_CLEAR_ENABLE 0 + +// CHANNEL10 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 10. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL10_FAULT_TYPE 0 + +// CHANNEL10 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 10. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL10_BUF_TROUGH_N_CREST 0 + +// CHANNEL10 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DRIVER_A 1 + +// CHANNEL10 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 10. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL10_DRIVER_B 0 + +// CHANNEL10 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_A_START_STATE 0 + +// CHANNEL10 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_A_STOP_STATE 0 + +// CHANNEL10 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_MATCH_COUNT 1 + +// CHANNEL10 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_A_OP_AT_CYCLE_END 2 + +// CHANNEL10 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_B_START_STATE 0 + +// CHANNEL10 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 10. +// Default: LOW +#define RTE_UTIMER_CHANNEL10_DRV_B_STOP_STATE 0 + +// CHANNEL10 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL10 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL10 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 10. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL10_EVENT_AT_CREST 1 + +// CHANNEL10 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_EVENT_AT_TROUGH 0 + +// CHANNEL10 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 10. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE 0 + +// CHANNEL10 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 10. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL10_BUFFER_OPERATION 0 + +// CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 10 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_A 2 + +// CHANNEL10 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 10 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL10_BUFFERING_TYPE_B 0 + +// CHANNEL10 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL10 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 10 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL10 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 10 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL10 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 10 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL10_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL10 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_ENABLE 0 + +// CHANNEL10 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 10. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL10_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 10 + +// UTIMER CHANNEL 11 +// Configuration settings for UTIMER channel 11 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL11 1 + +// CHANNEL11 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_FIXED_BUFFER 0 + +// CHANNEL11 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DMA_CLEAR_ENABLE 0 + +// CHANNEL11 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 11. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL11_FAULT_TYPE 0 + +// CHANNEL11 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 11. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL11_BUF_TROUGH_N_CREST 0 + +// CHANNEL11 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DRIVER_A 0 + +// CHANNEL11 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 11. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL11_DRIVER_B 0 + +// CHANNEL11 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_A_START_STATE 0 + +// CHANNEL11 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_A_STOP_STATE 0 + +// CHANNEL11 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL11 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL11 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_B_START_STATE 0 + +// CHANNEL11 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 11. +// Default: LOW +#define RTE_UTIMER_CHANNEL11_DRV_B_STOP_STATE 0 + +// CHANNEL11 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL11 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL11 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 11. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL11_EVENT_AT_CREST 1 + +// CHANNEL11 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_EVENT_AT_TROUGH 0 + +// CHANNEL11 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 11. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE 1 + +// CHANNEL11 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 11. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL11_BUFFER_OPERATION 1 + +// CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 11 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_A 2 + +// CHANNEL11 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 11 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL11_BUFFERING_TYPE_B 0 + +// CHANNEL11 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL11 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 11 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL11 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 11 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL11 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 11 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL11_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL11 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_ENABLE 0 +// UTIMER CHANNEL 11 + +// UTIMER CHANNEL 12 +// Configuration settings for UTIMER channel 12 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL12 1 + +// CHANNEL11 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 11. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL11_DUTY_CYCLE_VALUE 0 + +// CHANNEL12 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_FIXED_BUFFER 0 + +// CHANNEL12 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DMA_CLEAR_ENABLE 0 + +// CHANNEL12 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 12. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL12_FAULT_TYPE 0 + +// CHANNEL12 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 12. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL12_BUF_TROUGH_N_CREST 0 + +// CHANNEL12 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DRIVER_A 1 + +// CHANNEL12 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 12. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL12_DRIVER_B 0 + +// CHANNEL12 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_A_START_STATE 0 + +// CHANNEL12 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_A_STOP_STATE 0 + +// CHANNEL12 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL12 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL12 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_B_START_STATE 0 + +// CHANNEL12 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 12. +// Default: LOW +#define RTE_UTIMER_CHANNEL12_DRV_B_STOP_STATE 0 + +// CHANNEL12 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL12 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL12 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 12. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL12_EVENT_AT_CREST 1 + +// CHANNEL12 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_EVENT_AT_TROUGH 0 + +// CHANNEL12 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 12. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE 0 + +// CHANNEL12 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 12. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL12_BUFFER_OPERATION 0 + +// CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 12 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_A 0 + +// CHANNEL12 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 12 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL12_BUFFERING_TYPE_B 0 + +// CHANNEL12 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL12 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 12 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL12 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 12 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL12 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 12 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL12_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL12 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_ENABLE 0 + +// CHANNEL12 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 12. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL12_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 12 + +// UTIMER CHANNEL 13 +// Configuration settings for UTIMER channel 13 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL13 1 + +// CHANNEL13 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_FIXED_BUFFER 0 + +// CHANNEL13 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DMA_CLEAR_ENABLE 0 + +// CHANNEL13 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 13. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL13_FAULT_TYPE 0 + +// CHANNEL13 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 13. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL13_BUF_TROUGH_N_CREST 0 + +// CHANNEL13 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DRIVER_A 1 + +// CHANNEL13 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 13. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL13_DRIVER_B 0 + +// CHANNEL13 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_A_START_STATE 0 + +// CHANNEL13 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_A_STOP_STATE 0 + +// CHANNEL13 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL13 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL13 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_B_START_STATE 0 + +// CHANNEL13 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 13. +// Default: LOW +#define RTE_UTIMER_CHANNEL13_DRV_B_STOP_STATE 0 + +// CHANNEL13 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL13 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL13 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 13. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL13_EVENT_AT_CREST 1 + +// CHANNEL13 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_EVENT_AT_TROUGH 0 + +// CHANNEL13 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 13. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE 0 + +// CHANNEL13 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 13. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL13_BUFFER_OPERATION 0 + +// CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 13 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_A 0 + +// CHANNEL13 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 13 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL13_BUFFERING_TYPE_B 0 + +// CHANNEL13 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL13 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 13 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL13 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 13 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL13 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 13 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL13_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL13 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_ENABLE 0 + +// CHANNEL13 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 13. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL13_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 13 + +// UTIMER CHANNEL 14 +// Configuration settings for UTIMER channel 14 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL14 1 + +// CHANNEL14 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_FIXED_BUFFER 0 + +// CHANNEL14 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DMA_CLEAR_ENABLE 0 + +// CHANNEL14 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 14. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_UTIMER_CHANNEL14_FAULT_TYPE 0 + +// CHANNEL14 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 14. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL14_BUF_TROUGH_N_CREST 0 + +// CHANNEL14 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DRIVER_A 1 + +// CHANNEL14 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 14. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL14_DRIVER_B 0 + +// CHANNEL14 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_A_START_STATE 0 + +// CHANNEL14 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_A_STOP_STATE 0 + +// CHANNEL14 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL14 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL14 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_B_START_STATE 0 + +// CHANNEL14 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 14. +// Default: LOW +#define RTE_UTIMER_CHANNEL14_DRV_B_STOP_STATE 0 + +// CHANNEL14 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL14 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL14 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 14. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL14_EVENT_AT_CREST 1 + +// CHANNEL14 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_EVENT_AT_TROUGH 0 + +// CHANNEL14 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 14. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE 0 + +// CHANNEL14 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 14. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL14_BUFFER_OPERATION 0 + +// CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 14 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_A 0 + +// CHANNEL14 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 14 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL14_BUFFERING_TYPE_B 0 + +// CHANNEL14 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL14 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 14 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL14 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 14 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL14 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 14 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL14_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL14 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_ENABLE 0 + +// CHANNEL14 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 14. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL14_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 14 + +// UTIMER CHANNEL 15 +// Configuration settings for UTIMER channel 15 in component ::Drivers:UTIMER +#define RTE_UTIMER_CHANNEL15 1 + +// CHANNEL15 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_FIXED_BUFFER 0 + +// CHANNEL15 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DMA_CLEAR_ENABLE 0 + +// CHANNEL15 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for UT channel 15. +// Default: LOW_UNTIL_CYCLE_END +#define RTE_UTIMER_CHANNEL15_FAULT_TYPE 0 + +// CHANNEL15 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of UT channel 15. +// Default: BUF_AT_TROUGH +#define RTE_UTIMER_CHANNEL15_BUF_TROUGH_N_CREST 0 + +// CHANNEL15 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DRIVER_A 1 + +// CHANNEL15 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for UT channel 15. +// Default: DISABLED +#define RTE_UTIMER_CHANNEL15_DRIVER_B 0 + +// CHANNEL15 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_A_START_STATE 0 + +// CHANNEL15 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_A_STOP_STATE 0 + +// CHANNEL15 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL15 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL15 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_B_START_STATE 0 + +// CHANNEL15 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for UT channel 15. +// Default: LOW +#define RTE_UTIMER_CHANNEL15_DRV_B_STOP_STATE 0 + +// CHANNEL15 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL15 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL15 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for UT channel 15. +// Default: NO CHANGE +#define RTE_UTIMER_CHANNEL15_EVENT_AT_CREST 1 + +// CHANNEL15 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_EVENT_AT_TROUGH 0 + +// CHANNEL15 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for UT channel 15. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE 0 + +// CHANNEL15 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for UT channel 15. +// Default: ENABLE +#define RTE_UTIMER_CHANNEL15_BUFFER_OPERATION 0 + +// CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 15 capture mode. +// Default: DOUBLE BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_A 0 + +// CHANNEL15 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for UT channel 15 capture mode. +// Default: NO BUFFER +#define RTE_UTIMER_CHANNEL15_BUFFERING_TYPE_B 0 + +// CHANNEL15 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture A. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture B. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture C. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture D. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture E. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL15 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 15 capture F. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL15 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 15 overflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL15 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 15 underflow interrupt. +// Default: 0 +#define RTE_UTIMER_CHANNEL15_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL15 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_ENABLE 0 + +// CHANNEL15 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for UT channel 15. +// Default: DISABLE +#define RTE_UTIMER_CHANNEL15_DUTY_CYCLE_VALUE 0 +// UTIMER CHANNEL 15 +#endif /*RTE_UTIMER*/ +// UTIMER (Universal timer) [Driver_UTIMER] + +// LPUTIMER (Low-Power Universal Timer) [Driver_UTIMERLP] +// Configuration settings for Driver_UTIMERLP in component ::Drivers:UTIMER +#define RTE_LPUTIMER 1 + +#if RTE_LPUTIMER + +// LPUTIMER CHANNEL 0 +// Configuration settings for LPUTIMER channel 0 in component ::Drivers:UTIMERLP +#define RTE_LPUTIMER_CHANNEL0 1 + +// CHANNEL0 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for LP UT channel 0. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL0_FIXED_BUFFER 0 + +// CHANNEL0 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for LP UT channel 0. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL0_DMA_CLEAR_ENABLE 0 + +// CHANNEL0 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for LP UT channel 0. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_LPUTIMER_CHANNEL0_FAULT_TYPE 0 + +// CHANNEL0 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of LP UT channel 0. +// Default: BUF_AT_TROUGH +#define RTE_LPUTIMER_CHANNEL0_BUF_TROUGH_N_CREST 0 + +// CHANNEL0 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for LP UT channel 0. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL0_DRIVER_A 1 + +// CHANNEL0 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for LP UT channel 0. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL0_DRIVER_B 0 + +// CHANNEL0 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for LP UT channel 0. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL0_DRV_A_START_STATE 0 + +// CHANNEL0 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for LP UT channel 0. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL0_DRV_A_STOP_STATE 0 + +// CHANNEL0 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL0 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for LP UT channel 0. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL0_DRV_B_START_STATE 0 + +// CHANNEL0 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for LP UT channel 0. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL0_DRV_B_STOP_STATE 0 + +// CHANNEL0 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL0 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL0 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for LP UT channel 0. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL0_EVENT_AT_CREST 1 + +// CHANNEL0 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for LP UT channel 0. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL0_EVENT_AT_TROUGH 0 + +// CHANNEL0 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for LP UT channel 0. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL0_BUFFERING_TYPE 0 + +// CHANNEL0 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for LP UT channel 0. +// Default: ENABLE +#define RTE_LPUTIMER_CHANNEL0_BUFFER_OPERATION 0 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 0 capture mode. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL0_BUFFERING_TYPE_A 2 + +// CHANNEL0 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 0 capture mode. +// Default: NO BUFFER +#define RTE_LPUTIMER_CHANNEL0_BUFFERING_TYPE_B 0 + +// CHANNEL0 CAPTURE A IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture A. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_A_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE B IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture B. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_B_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE C IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture C. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_C_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE D IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture D. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_D_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE E IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture E. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_E_IRQ_PRIORITY 0 + +// CHANNEL0 CAPTURE F IRQ priority <0-255> +// Defines Interrupt priority for channel 0 capture F. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_CAPTURE_F_IRQ_PRIORITY 0 + +// CHANNEL0 OVERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 overflow interrupt. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_OVER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 UNDERFLOW IRQ priority <0-255> +// Defines Interrupt priority for channel 0 underflow interrupt. +// Default: 0 +#define RTE_LPUTIMER_CHANNEL0_UNDER_FLOW_IRQ_PRIORITY 0 + +// CHANNEL0 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for LP UT channel 0. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL0_DUTY_CYCLE_ENABLE 0 + +// CHANNEL0 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for LP UT channel 0. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL0_DUTY_CYCLE_VALUE 0 +// LPUTIMER CHANNEL 0 + +// LPUTIMER CHANNEL 1 +// Configuration settings for LPUTIMER channel 1 in component ::Drivers:UTIMERLP +#define RTE_LPUTIMER_CHANNEL1 1 + +// CHANNEL1 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for LP UT channel 1. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL1_FIXED_BUFFER 0 + +// CHANNEL1 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for LP UT channel 1. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL1_DMA_CLEAR_ENABLE 0 + +// CHANNEL1 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for LP UT channel 1. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_LPUTIMER_CHANNEL1_FAULT_TYPE 0 + +// CHANNEL1 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of LP UT channel 1. +// Default: BUF_AT_TROUGH +#define RTE_LPUTIMER_CHANNEL1_BUF_TROUGH_N_CREST 0 + +// CHANNEL1 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for LP UT channel 1. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL1_DRIVER_A 0 + +// CHANNEL1 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for LP UT channel 1. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL1_DRIVER_B 0 + +// CHANNEL1 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for LP UT channel 1. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL1_DRV_A_START_STATE 0 + +// CHANNEL1 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for LP UT channel 1. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL1_DRV_A_STOP_STATE 0 + +// CHANNEL1 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL1 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for LP UT channel 1. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL1_DRV_B_START_STATE 0 + +// CHANNEL1 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for LP UT channel 1. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL1_DRV_B_STOP_STATE 0 + +// CHANNEL1 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL1 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL1 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for LP UT channel 1. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL1_EVENT_AT_CREST 1 + +// CHANNEL1 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for LP UT channel 1. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL1_EVENT_AT_TROUGH 0 + +// CHANNEL1 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for LP UT channel 1. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL1_BUFFERING_TYPE 1 + +// CHANNEL1 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for LP UT channel 1. +// Default: ENABLE +#define RTE_LPUTIMER_CHANNEL1_BUFFER_OPERATION 1 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 1 capture mode. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL1_BUFFERING_TYPE_A 0 + +// CHANNEL1 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 1 capture mode. +// Default: NO BUFFER +#define RTE_LPUTIMER_CHANNEL1_BUFFERING_TYPE_B 0 + +// CHANNEL1 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for LP UT channel 1. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL1_DUTY_CYCLE_ENABLE 0 + +// CHANNEL1 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for LP UT channel 1. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL1_DUTY_CYCLE_VALUE 0 +// LPUTIMER CHANNEL 1 + +// LPUTIMER CHANNEL 2 +// Configuration settings for LPUTIMER channel 2 in component ::Drivers:UTIMERLP +#define RTE_LPUTIMER_CHANNEL2 1 + +// CHANNEL2 FIXED BUFFER +// <0=> DISABLED +// <1=> ENABLED +// Defines Fixed Buffer features for LP UT channel 2. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL2_FIXED_BUFFER 0 + +// CHANNEL2 DMA CLEAR ENABLE +// <0=> DISABLED +// <1=> ENABLED +// Defines DMA feature control for LP UT channel 2. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL2_DMA_CLEAR_ENABLE 0 + +// CHANNEL2 FAULT TYPE +// <0=> LOW_UNTIL_CYCLE_END +// <1=> LOW_UNTIL_COUNTER_STOP +// Defines fault type for LP UT channel 2. +// Default: LOW_UNTIL_COUNTER_STOP +#define RTE_LPUTIMER_CHANNEL2_FAULT_TYPE 0 + +// CHANNEL2 TRIANGLE COUNTER BUFFER EVENT +// <0=> BUF_AT_TROUGH +// <1=> BUF_AT_TROUGH_N_CREST +// Defines Buffer for triangle counter of LP UT channel 2. +// Default: BUF_AT_TROUGH +#define RTE_LPUTIMER_CHANNEL2_BUF_TROUGH_N_CREST 0 + +// CHANNEL2 DRIVER A +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver A state for LP UT channel 2. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL2_DRIVER_A 0 + +// CHANNEL2 DRIVER B +// <0=> DISABLED +// <1=> ENABLED +// Defines Driver B state for LP UT channel 2. +// Default: DISABLED +#define RTE_LPUTIMER_CHANNEL2_DRIVER_B 0 + +// CHANNEL2 DRIVER A START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A start state for LP UT channel 2. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL2_DRV_A_START_STATE 0 + +// CHANNEL2 DRIVER A STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver A stop state for LP UT channel 2. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL2_DRV_A_STOP_STATE 0 + +// CHANNEL2 DRIVER A AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at compare match for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_DRV_A_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER A AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver A state at cycle end for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_DRV_A_OP_AT_CYCLE_END 0 + +// CHANNEL2 DRIVER B START STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B start state for LP UT channel 2. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL2_DRV_B_START_STATE 0 + +// CHANNEL2 DRIVER B STOP STATE +// <0=> LOW +// <1=> HIGH +// Defines Driver B stop state for LP UT channel 2. +// Default: LOW +#define RTE_LPUTIMER_CHANNEL2_DRV_B_STOP_STATE 0 + +// CHANNEL2 DRIVER B AT COMP MATCH +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at compare match for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_DRV_B_OP_AT_MATCH_COUNT 0 + +// CHANNEL2 DRIVER B AT CYCLE END +// <0=> NO CHANGE +// <1=> LOW +// <2=> HIGH +// <3=> TOGGLE +// Defines Driver B state at cycle end for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_DRV_B_OP_AT_CYCLE_END 0 + +// CHANNEL2 BUFFER TRANSFER AT CREST +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at crest for LP UT channel 2. +// Default: NO CHANGE +#define RTE_LPUTIMER_CHANNEL2_EVENT_AT_CREST 1 + +// CHANNEL2 BUFFER TRANSFER AT TROUGH +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer transfer at trough for LP UT channel 2. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL2_EVENT_AT_TROUGH 0 + +// CHANNEL2 BUFFERING TYPE +// <0=> SINGLE BUFFER +// <1=> DOUBLE BUFFER +// Defines buffer type for LP UT channel 2. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL2_BUFFERING_TYPE 1 + +// CHANNEL2 BUFFER OPERATION +// <0=> DISABLE +// <1=> ENABLE +// Defines buffer operation for LP UT channel 2. +// Default: ENABLE +#define RTE_LPUTIMER_CHANNEL2_BUFFER_OPERATION 1 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER A +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 2 capture mode. +// Default: DOUBLE BUFFER +#define RTE_LPUTIMER_CHANNEL2_BUFFERING_TYPE_A 2 + +// CHANNEL2 CAPTURE BUFFER OPERATION FOR DRIVER B +// <0=> NO BUFFER +// <1=> SINGLE BUFFER +// <2=> DOUBLE BUFFER +// Defines buffer operation for LP UT channel 2 capture mode. +// Default: NO BUFFER +#define RTE_LPUTIMER_CHANNEL2_BUFFERING_TYPE_B 0 + +// CHANNEL2 DUTY CYCLE +// <0=> DISABLE +// <1=> ENABLE +// Defines duty cycle for LP UT channel 2. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL2_DUTY_CYCLE_ENABLE 0 + +// CHANNEL2 DUTY CYCLE VALUE +// <0=> COMP MATCH +// <1=> COMP MATCH +// <2=> 0 PERCENT +// <3=> 100 PERCENT +// Defines duty cycle value for LP UT channel 2. +// Default: DISABLE +#define RTE_LPUTIMER_CHANNEL2_DUTY_CYCLE_VALUE 0 +// LPUTIMER CHANNEL 2 +#endif /*RTE_LPUTIMER*/ + +// LPUTIMER (Low-Power Universal timer) [Driver_UTIMERLP] +// UTIMER (Universal Timer) + +// DAC (Digital to analog converter ) +// DAC0 (Digital to analog converter ) [Driver_DAC0] +// Configuration settings for Driver_DAC0 in component ::Drivers:DAC +#define RTE_DAC0 1 +#if RTE_DAC0 + +// DAC input through bypass mode +// <0=> DISABLE (DAC input data source through DAC_IN reg) +// <1=> ENABLE (DAC input data source through DAC_REG1 reg) +// Default: DISABLE +#define RTE_DAC0_INPUT_BYP_MUX_EN 0 + +// DAC converts two's complement to unsigned binary data +// DAC_out = (DAC_Input / 2^12) * Vref +// DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v +// 2^12 represents DAC supports 12 bit resolution. +// if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), +// DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). +// if dac_input > 2047 then, +// DAC_out = ((dac_input - 2047) / 2^12) *vref +// if dac_input < 2047 then, +// DAC_out = ((dac_input + 2047) / 2^12) *vref +// <0=> DISABLE(input will be positive) +// <1=> ENABLE (Input can be positive or negative) +// Default: DISABLE +#define RTE_DAC0_TWOSCOMP_EN 0 +#endif +// DAC0 (Digital to analog converter) [Driver_DAC0] + +// DAC1 (Digital to analog converter ) [Driver_DAC1] +// Configuration settings for Driver_DAC1 in component ::Drivers:DAC +#define RTE_DAC1 1 +#if RTE_DAC1 + +// DAC input through bypass mode +// <0=> DISABLE (DAC input data source through DAC_IN reg) +// <1=> ENABLE (DAC input data source through DAC_REG1 reg) +// Default: DISABLE +#define RTE_DAC1_INPUT_BYP_MUX_EN 0 + +// DAC converts two's complement to unsigned binary data +// DAC_out = (DAC_Input / 2^12) * Vref +// DAC input = 4000 ==> DAC_out = (4000 / 4096) * 1.8v ==> 1.757v +// 2^12 represents DAC supports 12 bit resolution. +// if DAC input = 0xFFFF FFFF FFFF FFFF (in decimal: -1), +// DAC_IN(0-11bits) ==> 0xFFF(dac_input = 4095). +// if dac_input > 2047 then, +// DAC_out = ((dac_input - 2047) / 2^12) *vref +// if dac_input < 2047 then, +// DAC_out = ((dac_input + 2047) / 2^12) *vref +// <0=> DISABLE(input will be positive) +// <1=> ENABLE (Input can be positive or negative) +// Default: DISABLE +#define RTE_DAC1_TWOSCOMP_EN 0 +#endif +// DAC1 (Digital to Analog converter) [Driver_DAC1] +// DAC(Digital to analog converter) + +// ADC (Analog to Digital Converter) +// ADC120 (Analog to Digital Converter 0) [Driver_ADC120] +// Configuration settings for Driver_ADC120 in component ::Drivers:ADC12 +#define RTE_ADC120 1 +#if RTE_ADC120 +#define RTE_ADC120_IRQ_PRIORITY 0 + +// ADC120 DONE0 IRQ PRIORITY <0-225> +// defines ADC120 done0 interrupt priority +// default: 0 +#define RTE_ADC120_DONE0_IRQ_PRIORITY 0 + +// ADC120 DONE1 IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_DONE1_IRQ_PRIORITY 0 + +// ADC120 CMPA IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_CMPA_IRQ_PRIORITY 0 + +// ADC120 CMPB IRQ PRIORITY <0-225> +// defines ADC120 interrupt priority +// default: 0 +#define RTE_ADC120_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC120_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC120_CLOCK_DIV (2) + +// Sample Width <2-32> +// Defines Width in divided clocks of the sample output signal +// Default: 16 +#define RTE_ADC120_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC120_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC120_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC120_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC120_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC120_DIFFERENTIAL_EN 0 + +// Enable PGA +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC120 PGA enable +// Default: DISABLE +#define RTE_ADC120_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC120_PGA_GAIN (0) +// RTE_ADC121_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC120_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC120_COMPARATOR_BIAS 2 + +#endif +// ADC120 (Analog to Digital Converter 0) [Driver_ADC120] + +// ADC121 (Analog to Digital Converter 1) [Driver_ADC121] +// Configuration settings for Driver_ADC121 in component ::Drivers:ADC +#define RTE_ADC121 1 +#if RTE_ADC121 + +// ADC121 DONE0 IRQ PRIORITY <0-225> +// defines ADC121 done0 interrupt priority +// default: 0 +#define RTE_ADC121_DONE0_IRQ_PRIORITY 0 + +// ADC121 DONE1 IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_DONE1_IRQ_PRIORITY 0 + +// ADC121 CMPA IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_CMPA_IRQ_PRIORITY 0 + +// ADC121 CMPB IRQ PRIORITY <0-225> +// defines ADC121 interrupt priority +// default: 0 +#define RTE_ADC121_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC121_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC121_CLOCK_DIV (2) + +// Sample Width <2-32> +// Defines Width in divided clocks of the sample output signal +// Default: 16 +#define RTE_ADC121_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC121_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC121_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC121_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC121_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC121_DIFFERENTIAL_EN 0 + +// Pga enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC121 using PGA gain +// Default: DISABLE +#define RTE_ADC121_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC121_PGA_GAIN (0) +// RTE_ADC121_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC121_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC121_COMPARATOR_BIAS 2 + +#endif +// ADC121 (Analog to Digital Converter 1) [Driver_ADC121] + +// ADC122 (Analog to Digital Converter 2) [Driver_ADC122] +// Configuration settings for Driver_ADC122 in component ::Drivers:ADC +#define RTE_ADC122 1 +#if RTE_ADC122 + +// ADC122 DONE0 IRQ PRIORITY <0-225> +// defines ADC122 done0 interrupt priority +// default: 0 +#define RTE_ADC122_DONE0_IRQ_PRIORITY 0 + +// ADC122 DONE1 IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_DONE1_IRQ_PRIORITY 0 + +// ADC122 CMPA IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_CMPA_IRQ_PRIORITY 0 + +// ADC122 CMPB IRQ PRIORITY <0-225> +// defines ADC122 interrupt priority +// default: 0 +#define RTE_ADC122_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-8> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC122_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC122_CLOCK_DIV (2) + +// Sample Width <2-32> +// defines Width in divided clocks of the sample output signal +// default: 16 +#define RTE_ADC122_SAMPLE_WIDTH (16) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC122_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC122_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC122_SHIFT_LEFT_OR_RIGHT (1) + +// RTE_ADC122_DIFFERENTIAL_EN +// Enable differential Mode: 1 ==> in1/2, in3/4, in5/6 will be differential other wise all +// single ended +#define RTE_ADC122_DIFFERENTIAL_EN 0 + +// Enable PGA ADC122 +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable ADC122 using PGA gain +// Default: DISABLE +#define RTE_ADC122_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC122_PGA_GAIN (0) +// RTE_ADC122_DIFFERENTIAL_EN + +// Comparator mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines set 1 to ENABLE the comparator otherwise comparator "DISABLE" +// Default: ENABLE +#define RTE_ADC122_COMPARATOR_EN 1 + +// Comparator bias enable +// <0=> 0.5MS/s +// <1=> 1MS/s +// <2=> 2.5MS/s +// <3=> 5MS/s +// Defines: "11":5MS/s; "10""2.5MS/s; "01":1MS/s;"00":0.5MS/s +// Default: ENABLE +#define RTE_ADC122_COMPARATOR_BIAS 2 + +#endif +// ADC122 (Analog to Digital Converter 2) [Driver_ADC122] + +// ADC24 (Analog to Digital Converter 0) [Driver_ADC24] +// Configuration settings for Driver_ADC24 in component ::Drivers:ADC +#define RTE_ADC24 1 +#if RTE_ADC24 + +// ADC24 DONE0 IRQ PRIORITY <0-225> +// defines ADC24 done0 interrupt priority +// default: 0 +#define RTE_ADC24_DONE0_IRQ_PRIORITY 0 + +// ADC24 DONE1 IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_DONE1_IRQ_PRIORITY 0 + +// ADC24 CMPA IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_CMPA_IRQ_PRIORITY 0 + +// ADC24 CMPB IRQ PRIORITY <0-225> +// defines ADC24 interrupt priority +// default: 0 +#define RTE_ADC24_CMPB_IRQ_PRIORITY 0 + +// Input channel number <0-4> +// Defines select input channel number. +// Default: 0 +#define RTE_ADC24_INPUT_NUM (0) + +// Clock Divider <2-16> +// Defines Clock divider applied to main clock +// Default: 2 +#define RTE_ADC24_CLOCK_DIV (2) + +// Number of average sample <0-256> +// Defines Number of sample to be taken and it must be power of 2 +// Default: 256 +#define RTE_ADC24_AVG_SAMPLE_NUM (256) + +// Number of bits to shift <0-8> +// Defines How much bit to shift before storing in sample register. +// Default: 8 +#define RTE_ADC24_SHIFT_N_BIT (8) + +// Left or Right shift +// <0=> LEFT SHIFT +// <1=> RIGHT SHIFT +// Defines shift averaged value before loading in sample register. +// Default: RIGHT SHIFT +#define RTE_ADC24_SHIFT_LEFT_OR_RIGHT (1) + +// Ouput rate select +// <0=> 1 KS/s +// <1=> 2 KS/s +// <2=> 4 KS/s +// <3=> 8 KS/s +// <4=> 16 KS/s +// Defines Select adc24 output rate +// Default: 0 +#define RTE_ADC24_OUTPUT_RATE (0) + +// PGA enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable PGA to set PGA gain +// Default: DISABLE +#define RTE_ADC24_PGA_EN (0) + +// PGA gain value +// <0=> 0 dB +// <1=> 6 dB +// <2=> 12 dB +// <3=> 18 dB +// <4=> 24 dB +// <5=> 30 dB +// <6=> 36 dB +// <7=> 42 dB +// Defines Select PGA gain value +// Default: 0 +#define RTE_ADC24_PGA_GAIN (0) + +// Bias Control +// <0=> 5 uA +// <1=> 6.25 uA +// <3=> 7.5 uA +// <7=> 8.75 uA +// Defines Bias control +// Default: 3 +#define RTE_ADC24_BIAS (3) + +#endif +// ADC24 (Analog to Digital Converter 0) [Driver_ADC24] +// ADC (Analog to Digital Converter) + +// CRC (Cyclic Redundancy Check) +// CRC0 (Cyclic Redundancy Check) [Driver_CRC0] +// Configuration settings for Driver_CRC0 in component ::Drivers:CRC +#define RTE_CRC0 1 +#if RTE_CRC0 + +// CRC0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for CRC0 +// Default: 0 +#define RTE_CRC0_DMA_ENABLE 0 +#if RTE_CRC0_DMA_ENABLE + +// CRC0 DMA Selection +// <0=> DMA0 +// <1=> DMA1 +// <2=> DMA2 +// Defines Select DMA for CRC0. By default DMA0 will be considered +// Default: 0 +#define RTE_CRC0_SELECT_DMA 0 +#endif + +// CRC0 DMA IRQ priority <0-255> +// Defines CRC0 DMA Interrupt priority +// Default: 0 +#define RTE_CRC0_DMA_IRQ_PRI 0 +#endif +// CRC0 (Cyclic Redundancy Check) [Driver_CRC0] + +// CRC1 (Cyclic Redundancy Check) [Driver_CRC1] +// Configuration settings for Driver_CRC1 in component ::Drivers:CRC +#define RTE_CRC1 1 +#if RTE_CRC1 + +// CRC1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for CRC1 +// Default: 0 +#define RTE_CRC1_DMA_ENABLE 0 +#if RTE_CRC1_DMA_ENABLE + +// CRC1 DMA Selection +// <0=> DMA0 +// <1=> DMA1 +// <2=> DMA2 +// Defines Select DMA for CRC1. By default DMA0 will be considered +// Default: 0 +#define RTE_CRC1_SELECT_DMA 0 +#endif + +// CRC1 DMA IRQ priority <0-255> +// Defines CRC1 DMA Interrupt priority +// Default: 0 +#define RTE_CRC1_DMA_IRQ_PRI 0 +#endif +// CRC1 (Cyclic Redundancy Check) [Driver_CRC1] +// + +// HWSEM (Hardware Semaphore) +// HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] +// Configuration settings for Driver_HWSEM0 in component ::Drivers:HWSEM +#define RTE_HWSEM0 1 +#if RTE_HWSEM0 + +// HWSEM0 IRQ priority <0-255> +// Defines HWSEM0 Interrupt priority +// Default: 0 +#define RTE_HWSEM0_IRQPRIORITY 0 +#endif + +// HWSEM0 (Hardware Semaphore) [Driver_HWSEM0] + +// HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] +// Configuration settings for Driver_HWSEM1 in component ::Drivers:HWSEM +#define RTE_HWSEM1 0 +#if RTE_HWSEM1 + +// HWSEM1 IRQ priority <0-255> +// Defines HWSEM1 Interrupt priority +// Default: 0 +#define RTE_HWSEM1_IRQPRIORITY 0 +#endif + +// HWSEM1 (Hardware Semaphore) [Driver_HWSEM1] + +// HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] +// Configuration settings for Driver_HWSEM2 in component ::Drivers:HWSEM +#define RTE_HWSEM2 0 +#if RTE_HWSEM2 + +// HWSEM2 IRQ priority <0-255> +// Defines HWSEM2 Interrupt priority +// Default: 0 +#define RTE_HWSEM2_IRQPRIORITY 0 +#endif + +// HWSEM2 (Hardware Semaphore) [Driver_HWSEM2] + +// HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] +// Configuration settings for Driver_HWSEM3 in component ::Drivers:HWSEM +#define RTE_HWSEM3 0 +#if RTE_HWSEM3 + +// HWSEM3 IRQ priority <0-255> +// Defines HWSEM3 Interrupt priority +// Default: 0 +#define RTE_HWSEM3_IRQPRIORITY 0 +#endif + +// HWSEM3 (Hardware Semaphore) [Driver_HWSEM3] + +// HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] +// Configuration settings for Driver_HWSEM4 in component ::Drivers:HWSEM +#define RTE_HWSEM4 0 +#if RTE_HWSEM4 + +// HWSEM4 IRQ priority <0-255> +// Defines HWSEM4 Interrupt priority +// Default: 0 +#define RTE_HWSEM4_IRQPRIORITY 0 +#endif + +// HWSEM4 (Hardware Semaphore) [Driver_HWSEM4] + +// HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] +// Configuration settings for Driver_HWSEM5 in component ::Drivers:HWSEM +#define RTE_HWSEM5 0 +#if RTE_HWSEM5 + +// HWSEM5 IRQ priority <0-255> +// Defines HWSEM5 Interrupt priority +// Default: 0 +#define RTE_HWSEM5_IRQPRIORITY 0 +#endif + +// HWSEM5 (Hardware Semaphore) [Driver_HWSEM5] + +// HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] +// Configuration settings for Driver_HWSEM6 in component ::Drivers:HWSEM +#define RTE_HWSEM6 0 +#if RTE_HWSEM6 + +// HWSEM6 IRQ priority <0-255> +// Defines HWSEM6 Interrupt priority +// Default: 0 +#define RTE_HWSEM6_IRQPRIORITY 0 +#endif + +// HWSEM6 (Hardware Semaphore) [Driver_HWSEM6] + +// HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] +// Configuration settings for Driver_HWSEM7 in component ::Drivers:HWSEM +#define RTE_HWSEM7 0 +#if RTE_HWSEM7 + +// HWSEM7 IRQ priority <0-255> +// Defines HWSEM7 Interrupt priority +// Default: 0 +#define RTE_HWSEM7_IRQPRIORITY 0 +#endif + +// HWSEM7 (Hardware Semaphore) [Driver_HWSEM7] + +// HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] +// Configuration settings for Driver_HWSEM8 in component ::Drivers:HWSEM +#define RTE_HWSEM8 0 +#if RTE_HWSEM8 + +// HWSEM8 IRQ priority <0-255> +// Defines HWSEM8 Interrupt priority +// Default: 0 +#define RTE_HWSEM8_IRQPRIORITY 0 +#endif + +// HWSEM8 (Hardware Semaphore) [Driver_HWSEM8] + +// HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] +// Configuration settings for Driver_HWSEM9 in component ::Drivers:HWSEM +#define RTE_HWSEM9 0 +#if RTE_HWSEM9 + +// HWSEM9 IRQ priority <0-255> +// Defines HWSEM9 Interrupt priority +// Default: 0 +#define RTE_HWSEM9_IRQPRIORITY 0 +#endif + +// HWSEM9 (Hardware Semaphore) [Driver_HWSEM9] + +// HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] +// Configuration settings for Driver_HWSEM10 in component ::Drivers:HWSEM +#define RTE_HWSEM10 0 +#if RTE_HWSEM10 + +// HWSEM10 IRQ priority <0-255> +// Defines HWSEM10 Interrupt priority +// Default: 0 +#define RTE_HWSEM10_IRQPRIORITY 0 +#endif + +// HWSEM10 (Hardware Semaphore) [Driver_HWSEM10] + +// HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] +// Configuration settings for Driver_HWSEM11 in component ::Drivers:HWSEM +#define RTE_HWSEM11 0 +#if RTE_HWSEM11 + +// HWSEM11 IRQ priority <0-255> +// Defines HWSEM11 Interrupt priority +// Default: 0 +#define RTE_HWSEM11_IRQPRIORITY 0 +#endif + +// HWSEM11 (Hardware Semaphore) [Driver_HWSEM11] + +// HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] +// Configuration settings for Driver_HWSEM12 in component ::Drivers:HWSEM +#define RTE_HWSEM12 0 +#if RTE_HWSEM12 + +// HWSEM12 IRQ priority <0-255> +// Defines HWSEM12 Interrupt priority +// Default: 0 +#define RTE_HWSEM12_IRQPRIORITY 0 +#endif + +// HWSEM12 (Hardware Semaphore) [Driver_HWSEM12] + +// HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] +// Configuration settings for Driver_HWSEM13 in component ::Drivers:HWSEM +#define RTE_HWSEM13 0 +#if RTE_HWSEM13 + +// HWSEM13 IRQ priority <0-255> +// Defines HWSEM13 Interrupt priority +// Default: 0 +#define RTE_HWSEM13_IRQPRIORITY 0 +#endif + +// HWSEM13 (Hardware Semaphore) [Driver_HWSEM13] + +// HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] +// Configuration settings for Driver_HWSEM14 in component ::Drivers:HWSEM +#define RTE_HWSEM14 0 +#if RTE_HWSEM14 + +// HWSEM14 IRQ priority <0-255> +// Defines HWSEM14 Interrupt priority +// Default: 0 +#define RTE_HWSEM14_IRQPRIORITY 0 +#endif + +// HWSEM14 (Hardware Semaphore) [Driver_HWSEM14] + +// HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] +// Configuration settings for Driver_HWSEM15 in component ::Drivers:HWSEM +#define RTE_HWSEM15 0 +#if RTE_HWSEM15 + +// HWSEM15 IRQ priority <0-255> +// Defines HWSEM15 Interrupt priority +// Default: 0 +#define RTE_HWSEM15_IRQPRIORITY 0 +#endif + +// HWSEM15 (Hardware Semaphore) [Driver_HWSEM15] +// + +// High speed Analog Comparator +// CMP0 (Analog Comparator ) [Driver_CMP0] +// Configuration settings for Driver_CMP0 in component ::Drivers:Comparator +#define RTE_HSCMP0 1 +#if RTE_HSCMP0 + +// CMP0 IRQ priority <0-255> +// Defines Interrupt priority for CMP0. +// Default: 0 +#define RTE_CMP0_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_0 +// <1=> PIN_P0_6 +// <2=> PIN_P1_4 +// <3=> PIN_P0_4 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_0; 01 = P0_6; 10 = P1_4; 11 = P0_4 +// Default : 0 +#define RTE_CMP0_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP0_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP0_SEL_HYSTERISIS 7 + +#endif +// CMP0 (Analog Comparator) [Driver_CMP0] + +// CMP1 (Analog Comparator ) [Driver_CMP1] +// Configuration settings for Driver_CMP1 in component ::Drivers:Comparator +#define RTE_HSCMP1 1 +#if RTE_HSCMP1 + +// CMP1 IRQ priority <0-255> +// Defines Interrupt priority for CMP1. +// Default: 0 +#define RTE_CMP1_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_1 +// <1=> PIN_P0_7 +// <2=> PIN_P1_5 +// <3=> PIN_P0_5 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_1; 01 = P0_7; 10 = P1_5; 11 = P0_5 +// Default : 0 +#define RTE_CMP1_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP1_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP1_SEL_HYSTERISIS 7 + +#endif +// CMP1 (Analog Comparator) [Driver_CMP1] + +// CMP2 (Analog Comparator ) [Driver_CMP2] +// Configuration settings for Driver_CMP2 in component ::Drivers:Comparator +#define RTE_HSCMP2 1 +#if RTE_HSCMP2 + +// CMP2 IRQ priority <0-255> +// Defines Interrupt priority for CMP2. +// Default: 0 +#define RTE_CMP2_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_2 +// <1=> PIN_P1_0 +// <2=> PIN_P1_6 +// <3=> PIN_P1_2 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_2; 01 = P1_0; 10 = P1_6; 11 = P1_2 +// Default : 0 +#define RTE_CMP2_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP2_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP2_SEL_HYSTERISIS 7 + +#endif +// CMP2 (Analog Comparator) [Driver_CMP2] + +// CMP3 (Analog Comparator ) [Driver_CMP3] +// Configuration settings for Driver_CMP3 in component ::Drivers:Comparator +#define RTE_HSCMP3 1 +#if RTE_HSCMP3 + +// CMP3 IRQ priority <0-255> +// Defines Interrupt priority for CMP3. +// Default: 0 +#define RTE_CMP3_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P0_3 +// <1=> PIN_P1_1 +// <2=> PIN_P1_7 +// <3=> PIN_P1_3 +// Defines:select input to the positive terminal of comparator; +// 00 = P0_3; 01 = P1_1; 10 = P1_7; 11 = P1_3 +// Default : 0 +#define RTE_CMP3_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> PIN_P2_0 +// <1=> PIN_P2_1 +// <2=> PIN_INT_VREF +// <3=> PIN_DAC6 +// Defines: select input to the negative terminal of comparator; +// 00 = P2_0; 01 = P2_1; 10 = Internal Vref; 11 = DAC6 +// Default : 3 +#define RTE_CMP3_SEL_NEGATIVE 3 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select comparator hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_CMP3_SEL_HYSTERISIS 7 + +#endif +// CMP3 (Analog Comparator) [Driver_CMP3] + +#if defined(RTSS_HE) +// LPCMP (Low Power Analog Comparator) [Driver_LPCMP] +// Configuration settings for Driver_LPCMP in component ::Drivers:LPCMP +#define RTE_LPCMP 1 + +#if RTE_LPCMP + +// LPCMP IRQ priority <0-255> +// Defines Interrupt priority for LPCMP. +// Default: 0 +#define RTE_LPCMP_IRQ_PRIORITY 0 + +// Select positive terminal +// <0=> PIN_P2_4 +// <1=> PIN_P2_5 +// <2=> PIN_P2_6 +// <3=> PIN_P2_7 +// Defines:select input to the positive terminal of LPCMP; +// 00 = P2_4; 01 = P2_5; 10 = P2_6; 11 = P2_7 +// Default : 0 +#define RTE_LPCMP_SEL_POSITIVE 0 + +// Select negative terminal +// <0=> AON_VREF +// <1=> PIN_P2_0 +// <2=> PIN_P2_1 +// <3=> PIN_P2_2 +// Defines: select input to the negative terminal of LPCMP; +// 00 = AON Vref(0.8v); 01 = P2_0; 10 = P2_1 Vref; 11 = P2_2 +// Default : 0 +#define RTE_LPCMP_SEL_NEGATIVE 0 + +// Select Hysteresis level +// <0=> 0mV +// <1=> 6mV +// <2=> 12mV +// <3=> 18mV +// <4=> 24mV +// <5=> 30mV +// <6=> 36mV +// <7=> 42mV +// Defines: Select LPCMP hysteresis level, step size is 6mv; +// 000 = 0mv; 001 = 6mv; 010 = 12mv; 011 = 18mv; 100 = 24mv; 101 = 30mv; +// 110 = 36mv; 111 = 42mV +// Default: 7 +#define RTE_LPCMP_SEL_HYSTERISIS 7 + +#endif +// LPCMP (Low Power Analog Comparator) [Driver_LPCMP] +#endif // defined(RTSS_HE) +// CMP (Analog Comparator) + +// I2C (Inter Integrated Circuit) +// I2C (Inter Integrated Circuit) [Driver_I2C0] +// Configuration settings for Driver_I2C0 in component ::Drivers:I2C +#define RTE_I2C0 1 + +#if RTE_I2C0 + +// I2C0 IRQ priority <0-255> +// Defines Interrupt priority for I2C0. +// Default: 0 +#define RTE_I2C0_IRQ_PRIORITY 0 +// I2C0 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C0. +// Default: 16 +#define RTE_I2C0_TX_FIFO_THRESHOLD 16 + +// I2C0 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C0. +// Default: 0 +#define RTE_I2C0_RX_FIFO_THRESHOLD 0 + +// I2C0 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C0 +// Default: DISABLE +#define RTE_I2C0_DMA_ENABLE 0 +#if RTE_I2C0_DMA_ENABLE + +// I2C0 DMA IRQ priority <0-255> +// Defines I2C0 DMA Interrupt priority +// Default: 0 +#define RTE_I2C0_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C0] + +// I2C (Inter Integrated Circuit) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::Drivers:I2C + +#define RTE_I2C1 1 +#if RTE_I2C1 + +// I2C1 IRQ priority <0-255> +// Defines Interrupt priority for I2C1. +// Default: 0 +#define RTE_I2C1_IRQ_PRIORITY 0 +// I2C1 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C1. +// Default: 16 +#define RTE_I2C1_TX_FIFO_THRESHOLD 16 + +// I2C1 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C1. +// Default: 0 +#define RTE_I2C1_RX_FIFO_THRESHOLD 0 + +// I2C1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C1 +// Default: DISABLE +#define RTE_I2C1_DMA_ENABLE 0 +#if RTE_I2C1_DMA_ENABLE + +// I2C1 DMA IRQ priority <0-255> +// Defines I2C1 DMA Interrupt priority +// Default: 0 +#define RTE_I2C1_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C1] + +// I2C (Inter Integrated Circuit) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::Drivers:I2C + +#define RTE_I2C2 1 +#if RTE_I2C2 + +// I2C2 IRQ priority <0-255> +// Defines Interrupt priority for I2C2. +// Default: 0 +#define RTE_I2C2_IRQ_PRIORITY 0 +// I2C2 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C2. +// Default: 16 +#define RTE_I2C2_TX_FIFO_THRESHOLD 16 + +// I2C2 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C2. +// Default: 0 +#define RTE_I2C2_RX_FIFO_THRESHOLD 0 + +// I2C2 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C2 +// Default: DISABLE +#define RTE_I2C2_DMA_ENABLE 0 +#if RTE_I2C2_DMA_ENABLE + +// I2C2 DMA IRQ priority <0-255> +// Defines I2C2 DMA Interrupt priority +// Default: 0 +#define RTE_I2C2_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C2] + +// I2C (Inter Integrated Circuit) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::Drivers:I2C + +#define RTE_I2C3 1 + +#if RTE_I2C3 + +// I2C3 IRQ priority <0-255> +// Defines Interrupt priority for I2C3. +// Default: 0 +#define RTE_I2C3_IRQ_PRIORITY 0 +// I2C3 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for I2C3. +// Default: 16 +#define RTE_I2C3_TX_FIFO_THRESHOLD 16 + +// I2C3 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for I2C3. +// Default: 0 +#define RTE_I2C3_RX_FIFO_THRESHOLD 0 + +// I2C3 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for I2C3 +// Default: DISABLE +#define RTE_I2C3_DMA_ENABLE 0 +#if RTE_I2C3_DMA_ENABLE + +// I2C3 DMA IRQ priority <0-255> +// Defines I2C3 DMA Interrupt priority +// Default: 0 +#define RTE_I2C3_DMA_IRQ_PRI 0 +#endif + +#endif +// I2C (Inter Integrated Circuit) [Driver_I2C3] + +// LPI2C0 (Low Power Inter-Integrated Circuit) [Driver_LPI2C0] +// Configuration settings for Driver_LPI2C0 in component ::Drivers:LPI2C +#if defined(RTSS_HE) +#define RTE_LPI2C0 1 +#if RTE_LPI2C0 + +// LPI2C0 IRQ PRIORITY <0-225> +// defines LPI2C0 interrupt priority +// default: 0 +#define RTE_LPI2C0_IRQ_PRIORITY 0 + +// LPI2C0 Bus-Speed <1-400000> +// defines LPI2C0 Bus-Speed - It is used for Bit-time calculation in driver +// default: 400KHz +#define RTE_LPI2C0_BUS_SPEED 400000 + +#endif +// LPI2C0(Low Power Inter-Integrated Circuit) [Driver_LPI2C0] + +// LPI2C (Low Power Inter Integrated Circuit) [Driver_LPI2C1] +// Configuration settings for Driver_LPI2C1 in component ::Drivers:LPI2C1 +#define RTE_LPI2C1 1 + +#if RTE_LPI2C1 + +// LPI2C1 IRQ priority <0-255> +// Defines Interrupt priority for LPI2C1. +// Default: 0 +#define RTE_LPI2C1_IRQ_PRIORITY 0 + +// LPI2C1 TX FIFO threshold <0-31> +// Defines TX FIFO threshold for LPI2C1. +// Default: 16 +#define RTE_LPI2C1_TX_FIFO_THRESHOLD 16 + +// LPI2C1 RX FIFO threshold <0-31> +// Defines RX FIFO threshold for LPI2C1. +// Default: 0 +#define RTE_LPI2C1_RX_FIFO_THRESHOLD 0 + +// LPI2C1 DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPI2C1 +// Default: DISABLE +#define RTE_LPI2C1_DMA_ENABLE 0 +#if RTE_LPI2C1_DMA_ENABLE + +// LPI2C1 DMA IRQ priority <0-255> +// Defines LPI2C1 DMA Interrupt priority +// Default: 0 +#define RTE_LPI2C1_DMA_IRQ_PRI 0 +#endif + +#endif +// LPI2C (Low Power Inter Integrated Circuit) [Driver_LPI2C1] +#endif // defined(RTSS_HE) +// I2C (Inter Integrated Circuit) + +// RANGE_SENSOR (Range Sensor) +// RANGE_SENSOR (Object Range Measurement Unit) [Driver_RANGE_SENSOR] +// Configuration settings for Driver_RANGE_SENSOR in component::Drivers:RANGE_SENSOR +#define RTE_RANGE_SENSOR 1 + +#if RTE_RANGE_SENSOR + +// CH201 (Time of Flight Sensor) [Driver_CH201] +// Configuration settings for Driver_CH201 in component::Drivers:CH201 +#define RTE_CH201 1 + +#if RTE_CH201 + +// CH201 I2C Bus speed range <0-400000> +// Defines CH201 I2C speed in Hertz +// Default: 400000 +#define RTE_CH201_I2C_SPEED_HZ 400000 + +// CH201 RTC calibration pulse range <1-1000> +// Defines CH201 sensor's internal RTC calculation pulse in millisec +// Default: 100 +#define RTE_CH201_RTC_CAL_PULSE_MS 100 + +// CH201 LPTIMER channel for Timeout trigger +// Defines LPTIMER's channel number for CH201 Timeout trigger +// <0=> LPTIMER_CHANNEL_0 +// <1=> LPTIMER_CHANNEL_1 +// <2=> LPTIMER_CHANNEL_2 +// <3=> LPTIMER_CHANNEL_3 +// Default: 1 +#define RTE_CH201_LPTIMER_CHANNEL 1 + +#endif +// CH201 (Time of Flight Sensor) [Driver_CH201] + +#endif +// RANGE_SENSOR (Object Range Measurement Unit) [Driver_RANGE_SENSOR] +// RANGE_SENSOR (Range Sensor) + +// DMA0 (Direct Memory Access Controller) [Driver_DMA0] +// Configuration settings for Driver_DMA0 in component ::Drivers:DMA +#define RTE_DMA0 1 +#if RTE_DMA0 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA0_APB_INTERFACE 0 +// DMA0 Abort interrupt priority <0-255> +// Defines DMA0 Abort interrupt priority. +// Default: 0 +#define RTE_DMA0_ABORT_IRQ_PRI 0 +// DMA0 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA0 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA0_BOOT_IRQ_NS_STATE 0 +// DMA0 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA0 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA0_BOOT_PERIPH_NS_STATE 0 +#endif +// DMA0 (Direct Memory Access Controller) [Driver_DMA0] + +// DMA1 (Direct Memory Access Controller) [Driver_DMA1] +#if defined(RTSS_HP) + +// Configuration settings for Driver_DMA1 in component ::Drivers:DMA +#define RTE_DMA1 1 +#if RTE_DMA1 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA1_APB_INTERFACE 0 +// DMA1 Abort interrupt priority <0-255> +// Defines DMA1 Abort interrupt priority. +// Default: 0 +#define RTE_DMA1_ABORT_IRQ_PRI 0 +// DMA1 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA1 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA1_BOOT_IRQ_NS_STATE 0 +// DMA1 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA1 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA1_BOOT_PERIPH_NS_STATE 0 +#endif + +#endif +// DMA1 (Direct Memory Access Controller) [Driver_DMA1] + +// DMA2 (Direct Memory Access Controller) [Driver_DMA2] +// Configuration settings for Driver_DMA2 in component ::Drivers:DMA +#if defined(RTSS_HE) + +#define RTE_DMA2 1 +#if RTE_DMA2 + +// DMA APB Interface to be used +// <0=> Secure APB interface +// <1=> Non-Secure +// Default: 0 +#define RTE_DMA2_APB_INTERFACE 0 +// DMA2 Abort interrupt priority <0-255> +// Defines DMA2 Abort interrupt priority. +// Default: 0 +#define RTE_DMA2_ABORT_IRQ_PRI 0 +// DMA2 Boot Event-IRQ Non-secure state <0-0xFFFFFFFF> +// Defines DMA2 Boot Event-IRQ Non-secure state +// Default: 0 +#define RTE_DMA2_BOOT_IRQ_NS_STATE 0 +// DMA2 Boot Peripheral Non-secure state <0-0xFFFFFFFF> +// Defines DMA2 Boot Peripheral Non-secure state +// Default: 0 +#define RTE_DMA2_BOOT_PERIPH_NS_STATE 0 +#endif + +#endif +// DMA2 (Direct Memory Access Controller) [Driver_DMA2] + +// GPIO (general purpose input and output) +// GPIO0 +// Configuration settings for Driver_GPIO0 in component ::Drivers:GPIO +#define RTE_GPIO0 1 + +#if RTE_GPIO0 + +// GPIO0 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO0. +// Default: 1 +#define RTE_GPIO0_DB_CLK_DIV 1 + +// GPIO0 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO0. +// Default: DISABLED +#define RTE_GPIO0_BIT_MANIPULATION 0 + +// GPIO0_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN0. +// Default: 0 +#define RTE_GPIO0_PIN0_IRQ_PRIORITY 0 + +// GPIO0_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN1. +// Default: 0 +#define RTE_GPIO0_PIN1_IRQ_PRIORITY 0 + +// GPIO0_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN2. +// Default: 0 +#define RTE_GPIO0_PIN2_IRQ_PRIORITY 0 + +// GPIO0_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN3. +// Default: 0 +#define RTE_GPIO0_PIN3_IRQ_PRIORITY 0 + +// GPIO0_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN4. +// Default: 0 +#define RTE_GPIO0_PIN4_IRQ_PRIORITY 0 + +// GPIO0_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN5. +// Default: 0 +#define RTE_GPIO0_PIN5_IRQ_PRIORITY 0 + +// GPIO0_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN6. +// Default: 0 +#define RTE_GPIO0_PIN6_IRQ_PRIORITY 0 + +// GPIO0_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO0_PIN7. +// Default: 0 +#define RTE_GPIO0_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO0 + +// GPIO1 +// Configuration settings for Driver_GPIO1 in component ::Drivers:GPIO +#define RTE_GPIO1 1 + +#if RTE_GPIO1 + +// GPIO1 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO1. +// Default: 1 +#define RTE_GPIO1_DB_CLK_DIV 1 + +// GPIO1 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO1. +// Default: DISABLED +#define RTE_GPIO1_BIT_MANIPULATION 0 + +// GPIO1_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN0. +// Default: 0 +#define RTE_GPIO1_PIN0_IRQ_PRIORITY 0 + +// GPIO1_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN1. +// Default: 0 +#define RTE_GPIO1_PIN1_IRQ_PRIORITY 0 + +// GPIO1_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN2. +// Default: 0 +#define RTE_GPIO1_PIN2_IRQ_PRIORITY 0 + +// GPIO1_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN3. +// Default: 0 +#define RTE_GPIO1_PIN3_IRQ_PRIORITY 0 + +// GPIO1_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN4. +// Default: 0 +#define RTE_GPIO1_PIN4_IRQ_PRIORITY 0 + +// GPIO1_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN5. +// Default: 0 +#define RTE_GPIO1_PIN5_IRQ_PRIORITY 0 + +// GPIO1_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN6. +// Default: 0 +#define RTE_GPIO1_PIN6_IRQ_PRIORITY 0 + +// GPIO1_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN7. +// Default: 0 +#define RTE_GPIO1_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO1 + +// GPIO2 +// Configuration settings for Driver_GPIO2 in component ::Drivers:GPIO +#define RTE_GPIO2 1 + +#if RTE_GPIO2 + +// GPIO2 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO2. +// Default: 1 +#define RTE_GPIO2_DB_CLK_DIV 1 + +// GPIO2 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO2. +// Default: DISABLED +#define RTE_GPIO2_BIT_MANIPULATION 0 + +// GPIO2_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN0. +// Default: 0 +#define RTE_GPIO2_PIN0_IRQ_PRIORITY 0 + +// GPIO2_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN1. +// Default: 0 +#define RTE_GPIO2_PIN1_IRQ_PRIORITY 0 + +// GPIO2_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN2. +// Default: 0 +#define RTE_GPIO2_PIN2_IRQ_PRIORITY 0 + +// GPIO2_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO1_PIN3. +// Default: 0 +#define RTE_GPIO2_PIN3_IRQ_PRIORITY 0 + +// GPIO2_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN4. +// Default: 0 +#define RTE_GPIO2_PIN4_IRQ_PRIORITY 0 + +// GPIO2_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN5. +// Default: 0 +#define RTE_GPIO2_PIN5_IRQ_PRIORITY 0 + +// GPIO2_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN6. +// Default: 0 +#define RTE_GPIO2_PIN6_IRQ_PRIORITY 0 + +// GPIO2_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO2_PIN7. +// Default: 0 +#define RTE_GPIO2_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO2 + +// GPIO3 +// Configuration settings for Driver_GPIO3 in component ::Drivers:GPIO +#define RTE_GPIO3 1 + +#if RTE_GPIO3 + +// GPIO3 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO3. +// Default: 1 +#define RTE_GPIO3_DB_CLK_DIV 1 + +// GPIO3 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO3. +// Default: DISABLED +#define RTE_GPIO3_BIT_MANIPULATION 0 + +// GPIO3_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN0. +// Default: 0 +#define RTE_GPIO3_PIN0_IRQ_PRIORITY 0 + +// GPIO3_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN1. +// Default: 0 +#define RTE_GPIO3_PIN1_IRQ_PRIORITY 0 + +// GPIO3_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN2. +// Default: 0 +#define RTE_GPIO3_PIN2_IRQ_PRIORITY 0 + +// GPIO3_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN3. +// Default: 0 +#define RTE_GPIO3_PIN3_IRQ_PRIORITY 0 + +// GPIO3_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN4. +// Default: 0 +#define RTE_GPIO3_PIN4_IRQ_PRIORITY 0 + +// GPIO3_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN5. +// Default: 0 +#define RTE_GPIO3_PIN5_IRQ_PRIORITY 0 + +// GPIO3_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN6. +// Default: 0 +#define RTE_GPIO3_PIN6_IRQ_PRIORITY 0 + +// GPIO3_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO3_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO3_PIN7. +// Default: 0 +#define RTE_GPIO3_PIN7_IRQ_PRIORITY 0 + +// GPIO3_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO3_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO3 + +// GPIO4 +// Configuration settings for Driver_GPIO4 in component ::Drivers:GPIO +#define RTE_GPIO4 1 + +#if RTE_GPIO4 + +// GPIO4 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO4. +// Default: 1 +#define RTE_GPIO4_DB_CLK_DIV 1 + +// GPIO4 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO4. +// Default: DISABLED +#define RTE_GPIO4_BIT_MANIPULATION 0 + +// GPIO4_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN0. +// Default: 0 +#define RTE_GPIO4_PIN0_IRQ_PRIORITY 0 + +// GPIO4_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN1. +// Default: 0 +#define RTE_GPIO4_PIN1_IRQ_PRIORITY 0 + +// GPIO4_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN2. +// Default: 0 +#define RTE_GPIO4_PIN2_IRQ_PRIORITY 0 + +// GPIO4_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN3. +// Default: 0 +#define RTE_GPIO4_PIN3_IRQ_PRIORITY 0 + +// GPIO4_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN4. +// Default: 0 +#define RTE_GPIO4_PIN4_IRQ_PRIORITY 0 + +// GPIO4_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN5. +// Default: 0 +#define RTE_GPIO4_PIN5_IRQ_PRIORITY 0 + +// GPIO4_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN6. +// Default: 0 +#define RTE_GPIO4_PIN6_IRQ_PRIORITY 0 + +// GPIO4_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO4_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO4_PIN7. +// Default: 0 +#define RTE_GPIO4_PIN7_IRQ_PRIORITY 0 + +// GPIO4_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO4_PIN7_DMA_GLITCH_FILTER_ENABLE 0 + +#endif +// GPIO4 + +// GPIO5 +// Configuration settings for Driver_GPIO5 in component ::Drivers:GPIO +#define RTE_GPIO5 1 + +#if RTE_GPIO5 + +// GPIO5 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO5. +// Default: 1 +#define RTE_GPIO5_DB_CLK_DIV 1 + +// GPIO5 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO5. +// Default: DISABLED +#define RTE_GPIO5_BIT_MANIPULATION 0 + +// GPIO5_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN0. +// Default: 0 +#define RTE_GPIO5_PIN0_IRQ_PRIORITY 0 + +// GPIO5_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN1. +// Default: 0 +#define RTE_GPIO5_PIN1_IRQ_PRIORITY 0 + +// GPIO5_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN2. +// Default: 0 +#define RTE_GPIO5_PIN2_IRQ_PRIORITY 0 + +// GPIO5_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN3. +// Default: 0 +#define RTE_GPIO5_PIN3_IRQ_PRIORITY 0 + +// GPIO5_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN4. +// Default: 0 +#define RTE_GPIO5_PIN4_IRQ_PRIORITY 0 + +// GPIO5_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN5. +// Default: 0 +#define RTE_GPIO5_PIN5_IRQ_PRIORITY 0 + +// GPIO5_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN6. +// Default: 0 +#define RTE_GPIO5_PIN6_IRQ_PRIORITY 0 + +// GPIO5_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO5_PIN7. +// Default: 0 +#define RTE_GPIO5_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO5 + +// GPIO6 +// Configuration settings for Driver_GPIO6 in component ::Drivers:GPIO +#define RTE_GPIO6 1 + +#if RTE_GPIO6 + +// GPIO6 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO6. +// Default: 1 +#define RTE_GPIO6_DB_CLK_DIV 1 + +// GPIO6 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO6. +// Default: DISABLED +#define RTE_GPIO6_BIT_MANIPULATION 0 + +// GPIO6_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN0. +// Default: 0 +#define RTE_GPIO6_PIN0_IRQ_PRIORITY 0 + +// GPIO6_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN1. +// Default: 0 +#define RTE_GPIO6_PIN1_IRQ_PRIORITY 0 + +// GPIO6_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN2. +// Default: 0 +#define RTE_GPIO6_PIN2_IRQ_PRIORITY 0 + +// GPIO6_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN3. +// Default: 0 +#define RTE_GPIO6_PIN3_IRQ_PRIORITY 0 + +// GPIO6_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN4. +// Default: 0 +#define RTE_GPIO6_PIN4_IRQ_PRIORITY 0 + +// GPIO6_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN5. +// Default: 0 +#define RTE_GPIO6_PIN5_IRQ_PRIORITY 0 + +// GPIO6_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN6. +// Default: 0 +#define RTE_GPIO6_PIN6_IRQ_PRIORITY 0 + +// GPIO6_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO6_PIN7. +// Default: 0 +#define RTE_GPIO6_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO6 + +// GPIO7 +// Configuration settings for Driver_GPIO7 in component ::Drivers:GPIO +#define RTE_GPIO7 1 + +#if RTE_GPIO7 + +// GPIO7 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO7. +// Default: 1 +#define RTE_GPIO7_DB_CLK_DIV 1 + +// GPIO7 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO7. +// Default: DISABLED +#define RTE_GPIO7_BIT_MANIPULATION 0 + +// GPIO7_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN0. +// Default: 0 +#define RTE_GPIO7_PIN0_IRQ_PRIORITY 0 + +// GPIO7_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN1. +// Default: 0 +#define RTE_GPIO7_PIN1_IRQ_PRIORITY 0 + +// GPIO7_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN2. +// Default: 0 +#define RTE_GPIO7_PIN2_IRQ_PRIORITY 0 + +// GPIO7_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN3. +// Default: 0 +#define RTE_GPIO7_PIN3_IRQ_PRIORITY 0 + +// GPIO7_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN4. +// Default: 0 +#define RTE_GPIO7_PIN4_IRQ_PRIORITY 0 + +// GPIO7_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN5. +// Default: 0 +#define RTE_GPIO7_PIN5_IRQ_PRIORITY 0 + +// GPIO7_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN6. +// Default: 0 +#define RTE_GPIO7_PIN6_IRQ_PRIORITY 0 + +// GPIO7_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO7_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO7_PIN7. +// Default: 0 +#define RTE_GPIO7_PIN7_IRQ_PRIORITY 0 + +// GPIO7_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO7_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO7 + +// GPIO8 +// Configuration settings for Driver_GPIO8 in component ::Drivers:GPIO +#define RTE_GPIO8 1 + +#if RTE_GPIO8 + +// GPIO8 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO8. +// Default: 1 +#define RTE_GPIO8_DB_CLK_DIV 1 + +// GPIO8 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO8. +// Default: DISABLED +#define RTE_GPIO8_BIT_MANIPULATION 0 + +// GPIO8_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN0. +// Default: 0 +#define RTE_GPIO8_PIN0_IRQ_PRIORITY 0 + +// GPIO8_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN1. +// Default: 0 +#define RTE_GPIO8_PIN1_IRQ_PRIORITY 0 + +// GPIO8_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN2. +// Default: 0 +#define RTE_GPIO8_PIN2_IRQ_PRIORITY 0 + +// GPIO8_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN3. +// Default: 0 +#define RTE_GPIO8_PIN3_IRQ_PRIORITY 0 + +// GPIO8_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN4. +// Default: 0 +#define RTE_GPIO8_PIN4_IRQ_PRIORITY 0 + +// GPIO8_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN5. +// Default: 0 +#define RTE_GPIO8_PIN5_IRQ_PRIORITY 0 + +// GPIO8_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN6. +// Default: 0 +#define RTE_GPIO8_PIN6_IRQ_PRIORITY 0 + +// GPIO8_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO8_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO8_PIN7. +// Default: 0 +#define RTE_GPIO8_PIN7_IRQ_PRIORITY 0 + +// GPIO8_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO8_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO8 + +// GPIO9 +// Configuration settings for Driver_GPIO9 in component ::Drivers:GPIO +#define RTE_GPIO9 1 + +#if RTE_GPIO9 + +// GPIO9 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO9. +// Default: 1 +#define RTE_GPIO9_DB_CLK_DIV 1 + +// GPIO9 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO9. +// Default: DISABLED +#define RTE_GPIO9_BIT_MANIPULATION 0 + +// GPIO9_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN0. +// Default: 0 +#define RTE_GPIO9_PIN0_IRQ_PRIORITY 0 + +// GPIO9_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN1. +// Default: 0 +#define RTE_GPIO9_PIN1_IRQ_PRIORITY 0 + +// GPIO9_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN2. +// Default: 0 +#define RTE_GPIO9_PIN2_IRQ_PRIORITY 0 + +// GPIO9_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN3. +// Default: 0 +#define RTE_GPIO9_PIN3_IRQ_PRIORITY 0 + +// GPIO9_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN4. +// Default: 0 +#define RTE_GPIO9_PIN4_IRQ_PRIORITY 0 + +// GPIO9_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN5. +// Default: 0 +#define RTE_GPIO9_PIN5_IRQ_PRIORITY 0 + +// GPIO9_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN6. +// Default: 0 +#define RTE_GPIO9_PIN6_IRQ_PRIORITY 0 + +// GPIO9_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// GPIO9_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO9_PIN7. +// Default: 0 +#define RTE_GPIO9_PIN7_IRQ_PRIORITY 0 + +// GPIO9_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_GPIO9_PIN7_DMA_GLITCH_FILTER_ENABLE 0 +#endif +// GPIO9 + +// GPIO10 +// Configuration settings for Driver_GPIO10 in component ::Drivers:GPIO +#define RTE_GPIO10 1 + +#if RTE_GPIO10 + +// GPIO10 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO10. +// Default: 1 +#define RTE_GPIO10_DB_CLK_DIV 1 + +// GPIO10 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO10. +// Default: DISABLED +#define RTE_GPIO10_BIT_MANIPULATION 0 + +// GPIO10_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN0. +// Default: 0 +#define RTE_GPIO10_PIN0_IRQ_PRIORITY 0 + +// GPIO10_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN1. +// Default: 0 +#define RTE_GPIO10_PIN1_IRQ_PRIORITY 0 + +// GPIO10_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN2. +// Default: 0 +#define RTE_GPIO10_PIN2_IRQ_PRIORITY 0 + +// GPIO10_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN3. +// Default: 0 +#define RTE_GPIO10_PIN3_IRQ_PRIORITY 0 + +// GPIO10_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN4. +// Default: 0 +#define RTE_GPIO10_PIN4_IRQ_PRIORITY 0 + +// GPIO10_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN5. +// Default: 0 +#define RTE_GPIO10_PIN5_IRQ_PRIORITY 0 + +// GPIO10_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN6. +// Default: 0 +#define RTE_GPIO10_PIN6_IRQ_PRIORITY 0 + +// GPIO10_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO10_PIN7. +// Default: 0 +#define RTE_GPIO10_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO10 + +// GPIO11 +// Configuration settings for Driver_GPIO11 in component ::Drivers:GPIO +#define RTE_GPIO11 1 + +#if RTE_GPIO11 + +// GPIO11 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO11. +// Default: 1 +#define RTE_GPIO11_DB_CLK_DIV 1 + +// GPIO11 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO11. +// Default: DISABLED +#define RTE_GPIO11_BIT_MANIPULATION 0 + +// GPIO11_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN0. +// Default: 0 +#define RTE_GPIO11_PIN0_IRQ_PRIORITY 0 + +// GPIO11_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN1. +// Default: 0 +#define RTE_GPIO11_PIN1_IRQ_PRIORITY 0 + +// GPIO11_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN2. +// Default: 0 +#define RTE_GPIO11_PIN2_IRQ_PRIORITY 0 + +// GPIO11_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN3. +// Default: 0 +#define RTE_GPIO11_PIN3_IRQ_PRIORITY 0 + +// GPIO11_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN4. +// Default: 0 +#define RTE_GPIO11_PIN4_IRQ_PRIORITY 0 + +// GPIO11_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN5. +// Default: 0 +#define RTE_GPIO11_PIN5_IRQ_PRIORITY 0 + +// GPIO11_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN6. +// Default: 0 +#define RTE_GPIO11_PIN6_IRQ_PRIORITY 0 + +// GPIO11_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO11_PIN7. +// Default: 0 +#define RTE_GPIO11_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO11 + +// GPIO12 +// Configuration settings for Driver_GPIO12 in component ::Drivers:GPIO +#define RTE_GPIO12 1 + +#if RTE_GPIO12 + +// GPIO12 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO12. +// Default: 1 +#define RTE_GPIO12_DB_CLK_DIV 1 + +// GPIO12 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO12. +// Default: DISABLED +#define RTE_GPIO12_BIT_MANIPULATION 0 + +// GPIO12_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN0. +// Default: 0 +#define RTE_GPIO12_PIN0_IRQ_PRIORITY 0 + +// GPIO12_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN1. +// Default: 0 +#define RTE_GPIO12_PIN1_IRQ_PRIORITY 0 + +// GPIO12_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN2. +// Default: 0 +#define RTE_GPIO12_PIN2_IRQ_PRIORITY 0 + +// GPIO12_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN3. +// Default: 0 +#define RTE_GPIO12_PIN3_IRQ_PRIORITY 0 + +// GPIO12_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN4. +// Default: 0 +#define RTE_GPIO12_PIN4_IRQ_PRIORITY 0 + +// GPIO12_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN5. +// Default: 0 +#define RTE_GPIO12_PIN5_IRQ_PRIORITY 0 + +// GPIO12_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN6. +// Default: 0 +#define RTE_GPIO12_PIN6_IRQ_PRIORITY 0 + +// GPIO12_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO12_PIN7. +// Default: 0 +#define RTE_GPIO12_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO12 + +// GPIO13 +// Configuration settings for Driver_GPIO13 in component ::Drivers:GPIO +#define RTE_GPIO13 1 + +#if RTE_GPIO13 + +// GPIO13 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO13. +// Default: 1 +#define RTE_GPIO13_DB_CLK_DIV 1 + +// GPIO13_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN0. +// Default: 0 +#define RTE_GPIO13_PIN0_IRQ_PRIORITY 0 + +// GPIO13 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO13. +// Default: DISABLED +#define RTE_GPIO13_BIT_MANIPULATION 0 + +// GPIO13_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN1. +// Default: 0 +#define RTE_GPIO13_PIN1_IRQ_PRIORITY 0 + +// GPIO13_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN2. +// Default: 0 +#define RTE_GPIO13_PIN2_IRQ_PRIORITY 0 + +// GPIO13_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN3. +// Default: 0 +#define RTE_GPIO13_PIN3_IRQ_PRIORITY 0 + +// GPIO13_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN4. +// Default: 0 +#define RTE_GPIO13_PIN4_IRQ_PRIORITY 0 + +// GPIO13_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN5. +// Default: 0 +#define RTE_GPIO13_PIN5_IRQ_PRIORITY 0 + +// GPIO13_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN6. +// Default: 0 +#define RTE_GPIO13_PIN6_IRQ_PRIORITY 0 + +// GPIO13_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO13_PIN7. +// Default: 0 +#define RTE_GPIO13_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO13 + +// GPIO14 +// Configuration settings for Driver_GPIO14 in component ::Drivers:GPIO +#define RTE_GPIO14 1 + +#if RTE_GPIO14 + +// GPIO14 Debounce Clock Divisor <0-1023> +// Defines debounce clock divisor for GPIO14. +// Default: 1 +#define RTE_GPIO14_DB_CLK_DIV 1 + +// GPIO14_PIN0 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN0. +// Default: 0 +#define RTE_GPIO14_PIN0_IRQ_PRIORITY 0 + +// GPIO14 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO14. +// Default: DISABLED +#define RTE_GPIO14_BIT_MANIPULATION 0 + +// GPIO14_PIN1 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN1. +// Default: 0 +#define RTE_GPIO14_PIN1_IRQ_PRIORITY 0 + +// GPIO14_PIN2 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN2. +// Default: 0 +#define RTE_GPIO14_PIN2_IRQ_PRIORITY 0 + +// GPIO14_PIN3 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN3. +// Default: 0 +#define RTE_GPIO14_PIN3_IRQ_PRIORITY 0 + +// GPIO14_PIN4 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN4. +// Default: 0 +#define RTE_GPIO14_PIN4_IRQ_PRIORITY 0 + +// GPIO14_PIN5 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN5. +// Default: 0 +#define RTE_GPIO14_PIN5_IRQ_PRIORITY 0 + +// GPIO14_PIN6 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN6. +// Default: 0 +#define RTE_GPIO14_PIN6_IRQ_PRIORITY 0 + +// GPIO14_PIN7 IRQ Priority +// Defines Interrupt priority for GPIO14_PIN7. +// Default: 0 +#define RTE_GPIO14_PIN7_IRQ_PRIORITY 0 +#endif +// GPIO14 + +// GPIO16 +// Configuration settings for Driver_GPIO16 in component ::Drivers:GPIO +#define RTE_GPIO16 1 + +#if RTE_GPIO16 + +// GPIO16 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO16. +// Default: DISABLED +#define RTE_GPIO16_BIT_MANIPULATION 0 + +// GPIO16 IRQ Priority +// Defines Interrupt priority for GPIO16 +// Default: 0 +#define RTE_GPIO16_IRQ_PRIORITY 0 +#endif +// GPIO16 + +// GPIO17 +// Configuration settings for Driver_GPIO17 in component ::Drivers:GPIO +#define RTE_GPIO17 1 +#if RTE_GPIO17 + +// GPIO17 Bit Manipulation Feature +// <0=> DISABLED +// <1=> ENABLED +// Defines Bit Manipulation Control for GPIO17. +// Default: DISABLED +#define RTE_GPIO17_BIT_MANIPULATION 0 + +// GPIO17 IRQ Priority +// Defines Interrupt priority for GPIO17 +// Default: 0 +#define RTE_GPIO17_IRQ_PRIORITY 0 +#endif +// GPIO17 + +// LPGPIO +// Configuration settings for Driver_LPGPIO in component ::Drivers:GPIO +#define RTE_LPGPIO 1 + +#if RTE_LPGPIO + +// LPGPIO Fast mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Fast mode +// Default: DISABLE +#define RTE_LPGPIO_FAST_MODE_ENABLE 0 + +// LPGPIO_PIN0 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN0. +// Default: 0 +#define RTE_LPGPIO_PIN0_IRQ_PRIORITY 0 + +// LPGPIO_PIN0 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN0_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN1 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN1. +// Default: 0 +#define RTE_LPGPIO_PIN1_IRQ_PRIORITY 0 + +// LPGPIO_PIN1 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN1_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN2 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN2. +// Default: 0 +#define RTE_LPGPIO_PIN2_IRQ_PRIORITY 0 + +// LPGPIO_PIN2 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN2_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN3 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN3. +// Default: 0 +#define RTE_LPGPIO_PIN3_IRQ_PRIORITY 0 + +// LPGPIO_PIN3 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN3_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN4 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN4. +// Default: 0 +#define RTE_LPGPIO_PIN4_IRQ_PRIORITY 0 + +// LPGPIO_PIN4 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN4_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN5 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN5. +// Default: 0 +#define RTE_LPGPIO_PIN5_IRQ_PRIORITY 0 + +// LPGPIO_PIN5 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN5_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN6 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN6. +// Default: 0 +#define RTE_LPGPIO_PIN6_IRQ_PRIORITY 0 + +// LPGPIO_PIN6 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN6_DMA_GLITCH_FILTER_ENABLE 0 + +// LPGPIO_PIN7 IRQ Priority +// Defines Interrupt priority for LPGPIO_PIN7. +// Default: 0 +#define RTE_LPGPIO_PIN7_IRQ_PRIORITY 0 + +// LPGPIO_PIN7 DMA Glitch Filter enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable Glitch Filter +// Default: DISABLE +#define RTE_LPGPIO_PIN7_DMA_GLITCH_FILTER_ENABLE 0 + +#endif +// LPGPIO + +// GPIO (general purpose input and output) + +// PDM(Pulse Density Modulation) +// PDM (Pulse density modulation) [Driver_PDM] +// Configuration settings for Driver_PDM in component ::Drivers:PDM +#define RTE_PDM 1 +#if RTE_PDM + +// PDM DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for PDM +// Default: ENABLE +#define RTE_PDM_DMA_ENABLE 0 + +// PDM DMA IRQ priority <0-255> +// Defines PDM DMA Interrupt priority +// Default: 0 +#define RTE_PDM_DMA_IRQ_PRIORITY 0 + +// PDM IRQ priority <0-255> +// Defines Interrupt priority for PDM. +// Default: 0 +#define RTE_PDM_IRQ_PRIORITY 0 + +// PDM Fifo watermark <0-7> +// Defines number of PCM samples in the internal FIFO +// Default: 5 +#define RTE_PDM_FIFO_WATERMARK 5 + +#endif +// PDM (Pulse density modulation) [Driver_PDM] + +// PDM (Pulse density modulation) + +#if defined(RTSS_HE) +// LPPDM(Low Power Pulse Density Modulation) +// LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] +// Configuration settings for Driver_LPPDM in component ::Drivers:LPPDM +#define RTE_LPPDM 1 + +#if RTE_LPPDM + +// LPPDM IRQ priority <0-255> +// Defines Interrupt priority for LPPDM. +// Default: 0 +#define RTE_LPPDM_IRQ_PRIORITY 0 + +// LPPDM Fifo watermark <0-7> +// Defines number of PCM samples in the internal FIFO +// Default: 5 +#define RTE_LPPDM_FIFO_WATERMARK 5 + +// LPPDM DMA ENABLE +// <0=> DISABLE +// <1=> ENABLE +// Defines DMA feature for LPPDM +// Default: ENABLE +#define RTE_LPPDM_DMA_ENABLE 0 +#if RTE_LPPDM_DMA_ENABLE + +// LPPDM DMA Selection +// <0=> DMA2 +// <1=> DMA0 +// Defines Select DMA0 for LPPDM. By default DMA2 will be considered +// Default: DMA2 +#define RTE_LPPDM_SELECT_DMA0 0 + +// PDM DMA IRQ priority <0-255> +// Defines PDM DMA Interrupt priority +// Default: 0 +#define RTE_LPPDM_DMA_IRQ_PRIORITY 0 +#endif +#endif +// LPPDM (Low Power Pulse density modulation) [Driver_LPPDM] +#endif // defined(RTSS_HE) +// LPPDM (Low Power Pulse density modulation) + +// CANFD (Controller Area Network - Fast Mode) +// CANFD0 (Controller Area Network - Fast Mode Interface) [Driver_CANFD0] +// Configuration settings for Driver_CANFD0 in component ::Drivers:CANFD +#define RTE_CANFD0 1 + +#if RTE_CANFD0 + +// CANFD0 IRQ priority <0-255> +// Defines Interrupt priority for CANFD0. +// Default: 0 +#define RTE_CANFD0_IRQ_PRIORITY 0 + +// CANFD0 Clock Source +// <0=> 38.4 MHz Clock +// <1=> 160 MHz Clock +// Defines Clock Source for CANFD0. +// Default: 160 MHz +#define RTE_CANFD0_CLK_SOURCE 1 + +// CANFD0 Clock Speed (Hz) <160000-80000000> +// Defines Clock Speed for CANFD0. +// Maximum Clock speed is 80MHz +// Recommended speeds with 160MHz clock source: 20MHz, 40MHz, 80MHz +// Default: 20MHz +#define RTE_CANFD0_CLK_SPEED 20000000 + +// CANFD0 blocking mode enable +// <0=> DISABLE +// <1=> ENABLE +// Defines Blocking mode support for CANFD0 +// Default: DISABLE +#define RTE_CANFD0_BLOCKING_MODE_ENABLE 0 + +#endif +// CANFD0 (Controller Area Network - Fast Mode Interface) [Driver_CANFD0] +// CANFD (Controller Area Network - Fast Mode) + +// SDC (Secure Digital Controller) +// SDC (Secure Digital Controller 0) [Driver_SDC0] +// Configuration settings for Driver_SDC0 in component ::Drivers:SDC +#define RTE_SDC 1 + +#if RTE_SDC + +// SDC BUS WIDTH SELECT +// <0=> BUS_WIDTH_1BIT +// <1=> BUS_WIDTH_4BIT +// Defines SDC0 size of bus width +// Default: BUS_WIDTH_4BIT +#define RTE_SDC_BUS_WIDTH 1 + +// SDC CLOCK SELECT (Hz) +// <12500000=> 12.5MHz +// <25000000=> 25MHz +// <50000000=> 50MHz +// Defines SDC0 Clock frequency in Hz +// Default: 25MHz +#define RTE_SDC_CLOCK_SELECT 25000000 + +// SDC DMA SELECT +// <0=> SDMA +// <1=> ADMA2 +// Defines SDC0 DMA select +// Default: ADMA2 +#define RTE_SDC_DMA_SELECT 1 + +// SDC IRQ MODE SELECT +// <0=> Polling Mode +// <1=> IRQ Mode +// Defines SDC IRQ MODE select +// Default: IRQ MODE +#define RTE_SDC_IRQ_MODE_SELECT 1 + +// SDC IRQ priority <0-255> +// Defines SDC Interrupt priority +// Default: 0 +#define RTE_SDC_IRQ_PRI 0 + +// SDC WAKEUP IRQ priority <0-255> +// Defines SDC Wakeup Interrupt priority +// Default: 0 +#define RTE_SDC_WAKEUP_IRQ_PRI 0 + +#endif +// SDC0 (Secure Digital Controller 0) [Driver_SDC0] +// SDC (Secure Digital Controller) + +// ETH_MAC (Ethernet MAC) +// ETH_MAC (Ethernet MAC) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::Drivers:ETH_MAC +#define RTE_ETH_MAC 1 + +#if RTE_ETH_MAC + +// ETH MAC IRQ priority <0-255> +// Defines ETH MAC Interrupt priority +// Default: 0 +#define RTE_ETH_MAC_IRQ_PRIORITY 0 + +#endif +// ETH (Ethernet MAC) [Driver_ETH_MAC0] +// ETH (Ethernet MAC) + +// Power Management (PM) +// Handle Spurious Wakeup +// <0=> Disable +// <1=> Enable +// define Handle Spurious Wakeup +// default: Enable +#define PM_HANDLE_SPURIOUS_WAKEUP 1 +// Power Management (PM) + +#endif /* __RTE_DEVICE_H */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_mem_regions.h b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_mem_regions.h new file mode 100644 index 00000000..7e54e76c --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_mem_regions.h @@ -0,0 +1,218 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +#ifndef APP_MEM_REGIONS_H +#define APP_MEM_REGIONS_H + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// MRAM XIP Configuration +// ======================= +// RTSS HE Base address <0x80000000-0x8057FFFF:8> +// Defines base address of RTSS HE application memory region. +// Default: 0x80000000 +#define APP_MRAM_HE_BASE 0x80000000 +// RTSS HE Region size [bytes] <0x0-0x00580000:8> +// Defines size of RTSS HE application memory region. +// Default: 0x00200000 +#define APP_MRAM_HE_SIZE 0x00200000 +// RTSS HP Base address <0x80000000-0x8057FFFF:8> +// Defines base address of RTSS HP application memory region. +// Default: 0x80000000 +#define APP_MRAM_HP_BASE 0x80200000 +// RTSS HP Region size [bytes] <0x0-0x00580000:8> +// Defines size of RTSS HP application memory region. +// Default: 0x00200000 +#define APP_MRAM_HP_SIZE 0x00370000 // 3.4375 MB: HP code region extended over the former MRAM_USER area for the ~2.8 MB model +// + +// MRAM User Configuration +// ======================= +// MRAM User Region +// User Base address <0x80000000-0x8057FFFF:8> +// Defines base address of MRAM user region +#define APP_MRAM_USER_BASE 0x80570000 // was 0x80400000; the HP code region ends here + +// User Region size [bytes] <0x0-0x00580000:8> +// Defines size of MRAM user region +#define APP_MRAM_USER_SIZE 0x00008000 // 32 kB, ends at 0x80578000 below the ATOC package (~0x8057C000); non-zero keeps mpu.c's regions well-formed + +// Application executable MRAM region (before USER area) +#define APP_CODE_MRAM_SIZE (APP_MRAM_USER_BASE - APP_MRAM_HP_BASE) +// + +// RAM Configuration +// ======================= +// Combine SRAM0 & SRAM1 +// Combines SRAM0 and SRAM1 into single memory region +#define SRAM0_SRAM1_COMBINED 0 // SRAM1 follows SRAM0, but the Ethos-U85 cannot reach it: keep NPU buffers in SRAM0 +// SRAM +// Base address <0x02000000-0x027FFFFF:8> +// Defines base address of SRAM memory region. +// Default: 0x02000000 +#define APP_SRAM_BASE 0x02000000 +// Region size [bytes] <0x0-0x00800000:8> +// Defines size of SRAM0 memory region. +// Default: 0x00800000 +#define APP_SRAM_SIZE 0x00800000 +// No zero initialize +// Excludes SRAM0 region from zero initialization. +#define APP_SRAM_NOINIT 1 +// Offset of the application pools <0x0-0x00400000:8> +// The ATOC loads the A32 boot stub (a32_stub_0.bin) to 0x02000000; the +// ExecuTorch pools (.bss.ai_pool) and the LCD frame buffer start above it. +#define APP_SRAM_POOL_OFFSET 0x00010000 +// + +// SRAM0 +// Base address <0x02000000-0x023FFFFF:8> +// Defines base address of SRAM0 memory region. +// Default: 0x02000000 +#define APP_SRAM0_BASE 0x02000000 +// Region size [bytes] <0x0-0x00400000:8> +// Defines size of SRAM0 memory region. +// Default: 0x00400000 +#define APP_SRAM0_SIZE 0x00400000 +// No zero initialize +// Excludes SRAM0 region from zero initialization. +#define APP_SRAM0_NOINIT 1 +// + +// SRAM1 +// Base address <0x02400000-0x027FFFFF:8> +// Defines base address of SRAM1 memory region. +// Default: 0x02400000 +#define APP_SRAM1_BASE 0x02400000 +// Region size [bytes] <0x0-0x00400000:8> +// Defines size of SRAM1 memory region. +// Default: 0x00400000 +#define APP_SRAM1_SIZE 0x00400000 +// No zero initialize +// Excludes SRAM1 region from zero initialization. +#define APP_SRAM1_NOINIT 1 +// + +// SRAM2 +// Base address <0x50000000-0x5003FFFF:8> +// Defines base address of SRAM2 memory region. +// Default: 0x50000000 +#define APP_SRAM2_BASE 0x50000000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM2 memory region. +// Default: 0x00040000 +#define APP_SRAM2_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM2 region from zero initialization. +#define APP_SRAM2_NOINIT 0 +// + +// SRAM3 +// Base address <0x50800000-0x508FFFFF:8> +// Defines base address of SRAM3 memory region. +// Default: 0x50800000 +#define APP_SRAM3_BASE 0x50800000 +// Region size [bytes] <0x0-0x00100000:8> +// Defines size of SRAM3 memory region. +// Default: 0x00100000 +#define APP_SRAM3_SIZE 0x00100000 +// No zero initialize +// Excludes SRAM3 region from zero initialization. +#define APP_SRAM3_NOINIT 0 +// + +// SRAM4 +// Base address <0x58000000-0x5803FFFF:8> +// Defines base address of SRAM4 memory region. +// Default: 0x58000000 +#define APP_SRAM4_BASE 0x58000000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM4 memory region. +// Default: 0x00040000 +#define APP_SRAM4_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM4 region from zero initialization. +#define APP_SRAM4_NOINIT 0 +// + +// SRAM5 +// Base address <0x58800000-0x5883FFFF:8> +// Defines base address of SRAM5 memory region. +// Default: 0x58800000 +#define APP_SRAM5_BASE 0x58800000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM5 memory region. +// Default: 0x00040000 +#define APP_SRAM5_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM5 region from zero initialization. +#define APP_SRAM5_NOINIT 0 +// + +// + +// Stack / Heap Configuration + +// RTSS HE +// Stack Size (in Bytes) <0x0-0x400000:8> +// Heap Size (in Bytes) <0x0-0x400000:8> +#define APP_HE_STACK_SIZE 0x00002000 +#define APP_HE_HEAP_SIZE 0x00004000 +// + +// RTSS HP +// Stack Size (in Bytes) <0x0-0x400000:8> +// Heap Size (in Bytes) <0x0-0x400000:8> +#define APP_HP_STACK_SIZE 0x00002000 +#define APP_HP_HEAP_SIZE 0x00018000 +// + +// + +// ITCM & DTCM Base Address +// ITCM Base address <0x0-0x400000:8> +// DTCM Base address <0x20000000-0x400000:8> +#define APP_ITCM_BASE 0x00000000 +#define APP_DTCM_BASE 0x20000000 +// + +// OSPI XIP Configuration +// ======================= +// Boot from OSPI +// Enable XIP from OSPI +#define APP_BOOT_OSPI_FLASH 0 +// RTSS HE Base address <0xC0000000-0xDFFFFFFF:8> +// Defines base address of RTSS HE application memory region. +// Default: 0xC0000000 +#define APP_OSPI_FLASH_HE_BASE 0xC0000000 +// RTSS HE Region size [bytes] <0x0-0x20000000:8> +// Defines size of RTSS HE application memory region. +// Default: 0x00200000 +#define APP_OSPI_FLASH_HE_SIZE 0x00200000 +// RTSS HP Base address <0xC0000000-0xDFFFFFFF:8> +// Defines base address of RTSS HP application memory region. +// Default: 0x80000000 +#define APP_OSPI_FLASH_HP_BASE 0xC0200000 +// RTSS HP Region size [bytes] <0x0-0x20000000:8> +// Defines size of RTSS HP application memory region. +// Default: 0x00200000 +#define APP_OSPI_FLASH_HP_SIZE 0x00200000 +// + +#define APP_HE_ITCM_SIZE APP_SRAM4_SIZE +#define APP_HE_DTCM_SIZE APP_SRAM5_SIZE + +#define APP_HP_ITCM_SIZE APP_SRAM2_SIZE +#define APP_HP_DTCM_SIZE APP_SRAM3_SIZE + +#define TGU_BLOCK_SIZE 16384 + +#define __HAS_BULK_SRAM 1 + +#endif /* APP_MEM_REGIONS_H */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_mem_regions.h.base@3.0.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_mem_regions.h.base@3.0.0 new file mode 100644 index 00000000..92296ea6 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_mem_regions.h.base@3.0.0 @@ -0,0 +1,214 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +#ifndef APP_MEM_REGIONS_H +#define APP_MEM_REGIONS_H + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// MRAM XIP Configuration +// ======================= +// RTSS HE Base address <0x80000000-0x8057FFFF:8> +// Defines base address of RTSS HE application memory region. +// Default: 0x80000000 +#define APP_MRAM_HE_BASE 0x80000000 +// RTSS HE Region size [bytes] <0x0-0x00580000:8> +// Defines size of RTSS HE application memory region. +// Default: 0x00200000 +#define APP_MRAM_HE_SIZE 0x00200000 +// RTSS HP Base address <0x80000000-0x8057FFFF:8> +// Defines base address of RTSS HP application memory region. +// Default: 0x80000000 +#define APP_MRAM_HP_BASE 0x80200000 +// RTSS HP Region size [bytes] <0x0-0x00580000:8> +// Defines size of RTSS HP application memory region. +// Default: 0x00200000 +#define APP_MRAM_HP_SIZE 0x00200000 +// + +// MRAM User Configuration +// ======================= +// MRAM User Region +// User Base address <0x80000000-0x8057FFFF:8> +// Defines base address of MRAM user region +#define APP_MRAM_USER_BASE 0x80400000 + +// User Region size [bytes] <0x0-0x00580000:8> +// Defines size of MRAM user region +#define APP_MRAM_USER_SIZE 0x00180000 // 1.5 MB + +// Application executable MRAM region (before USER area) +#define APP_CODE_MRAM_SIZE (APP_MRAM_USER_BASE - APP_MRAM_HP_BASE) +// + +// RAM Configuration +// ======================= +// Combine SRAM0 & SRAM1 +// Combines SRAM0 and SRAM1 into single memory region +#define SRAM0_SRAM1_COMBINED 1 +// SRAM +// Base address <0x02000000-0x027FFFFF:8> +// Defines base address of SRAM memory region. +// Default: 0x02000000 +#define APP_SRAM_BASE 0x02000000 +// Region size [bytes] <0x0-0x00800000:8> +// Defines size of SRAM0 memory region. +// Default: 0x00800000 +#define APP_SRAM_SIZE 0x00800000 +// No zero initialize +// Excludes SRAM0 region from zero initialization. +#define APP_SRAM_NOINIT 1 +// + +// SRAM0 +// Base address <0x02000000-0x023FFFFF:8> +// Defines base address of SRAM0 memory region. +// Default: 0x02000000 +#define APP_SRAM0_BASE 0x02000000 +// Region size [bytes] <0x0-0x00400000:8> +// Defines size of SRAM0 memory region. +// Default: 0x00400000 +#define APP_SRAM0_SIZE 0x00400000 +// No zero initialize +// Excludes SRAM0 region from zero initialization. +#define APP_SRAM0_NOINIT 1 +// + +// SRAM1 +// Base address <0x02400000-0x027FFFFF:8> +// Defines base address of SRAM1 memory region. +// Default: 0x02400000 +#define APP_SRAM1_BASE 0x02400000 +// Region size [bytes] <0x0-0x00400000:8> +// Defines size of SRAM1 memory region. +// Default: 0x00400000 +#define APP_SRAM1_SIZE 0x00400000 +// No zero initialize +// Excludes SRAM1 region from zero initialization. +#define APP_SRAM1_NOINIT 1 +// + +// SRAM2 +// Base address <0x50000000-0x5003FFFF:8> +// Defines base address of SRAM2 memory region. +// Default: 0x50000000 +#define APP_SRAM2_BASE 0x50000000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM2 memory region. +// Default: 0x00040000 +#define APP_SRAM2_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM2 region from zero initialization. +#define APP_SRAM2_NOINIT 0 +// + +// SRAM3 +// Base address <0x50800000-0x508FFFFF:8> +// Defines base address of SRAM3 memory region. +// Default: 0x50800000 +#define APP_SRAM3_BASE 0x50800000 +// Region size [bytes] <0x0-0x00100000:8> +// Defines size of SRAM3 memory region. +// Default: 0x00100000 +#define APP_SRAM3_SIZE 0x00100000 +// No zero initialize +// Excludes SRAM3 region from zero initialization. +#define APP_SRAM3_NOINIT 0 +// + +// SRAM4 +// Base address <0x58000000-0x5803FFFF:8> +// Defines base address of SRAM4 memory region. +// Default: 0x58000000 +#define APP_SRAM4_BASE 0x58000000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM4 memory region. +// Default: 0x00040000 +#define APP_SRAM4_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM4 region from zero initialization. +#define APP_SRAM4_NOINIT 0 +// + +// SRAM5 +// Base address <0x58800000-0x5883FFFF:8> +// Defines base address of SRAM5 memory region. +// Default: 0x58800000 +#define APP_SRAM5_BASE 0x58800000 +// Region size [bytes] <0x0-0x00040000:8> +// Defines size of SRAM5 memory region. +// Default: 0x00040000 +#define APP_SRAM5_SIZE 0x00040000 +// No zero initialize +// Excludes SRAM5 region from zero initialization. +#define APP_SRAM5_NOINIT 0 +// + +// + +// Stack / Heap Configuration + +// RTSS HE +// Stack Size (in Bytes) <0x0-0x400000:8> +// Heap Size (in Bytes) <0x0-0x400000:8> +#define APP_HE_STACK_SIZE 0x00002000 +#define APP_HE_HEAP_SIZE 0x00004000 +// + +// RTSS HP +// Stack Size (in Bytes) <0x0-0x400000:8> +// Heap Size (in Bytes) <0x0-0x400000:8> +#define APP_HP_STACK_SIZE 0x00002000 +#define APP_HP_HEAP_SIZE 0x00004000 +// + +// + +// ITCM & DTCM Base Address +// ITCM Base address <0x0-0x400000:8> +// DTCM Base address <0x20000000-0x400000:8> +#define APP_ITCM_BASE 0x00000000 +#define APP_DTCM_BASE 0x20000000 +// + +// OSPI XIP Configuration +// ======================= +// Boot from OSPI +// Enable XIP from OSPI +#define APP_BOOT_OSPI_FLASH 0 +// RTSS HE Base address <0xC0000000-0xDFFFFFFF:8> +// Defines base address of RTSS HE application memory region. +// Default: 0xC0000000 +#define APP_OSPI_FLASH_HE_BASE 0xC0000000 +// RTSS HE Region size [bytes] <0x0-0x20000000:8> +// Defines size of RTSS HE application memory region. +// Default: 0x00200000 +#define APP_OSPI_FLASH_HE_SIZE 0x00200000 +// RTSS HP Base address <0xC0000000-0xDFFFFFFF:8> +// Defines base address of RTSS HP application memory region. +// Default: 0x80000000 +#define APP_OSPI_FLASH_HP_BASE 0xC0200000 +// RTSS HP Region size [bytes] <0x0-0x20000000:8> +// Defines size of RTSS HP application memory region. +// Default: 0x00200000 +#define APP_OSPI_FLASH_HP_SIZE 0x00200000 +// + +#define APP_HE_ITCM_SIZE APP_SRAM4_SIZE +#define APP_HE_DTCM_SIZE APP_SRAM5_SIZE + +#define APP_HP_ITCM_SIZE APP_SRAM2_SIZE +#define APP_HP_DTCM_SIZE APP_SRAM3_SIZE + +#define TGU_BLOCK_SIZE 16384 + +#define __HAS_BULK_SRAM 1 + +#endif /* APP_MEM_REGIONS_H */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_tz.h b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_tz.h new file mode 100644 index 00000000..cc156f13 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_tz.h @@ -0,0 +1,1288 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef APP_TZ_H +#define APP_TZ_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#if defined(__ARMCC_VERSION) +extern const uint32_t Image$$NS_REGION_0$$Base; +#define SAU_INIT_START0 (uint32_t) &Image$$NS_REGION_0$$Base +#elif defined(__GNUC__) +extern const uint32_t __ns_region_0_start; +#define SAU_INIT_START0 (uint32_t) &__ns_region_0_start +#elif defined(__ICCARM__) +extern const uint32_t NS_REGION_0$$Base; +#define SAU_INIT_START0 (uint32_t) &NS_REGION_0$$Base +#else +#error Unknown compiler. +#endif + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#if defined(__ARMCC_VERSION) +extern const uint32_t Image$$NS_REGION_0_PAD$$Base; +#define SAU_INIT_END0 ((uint32_t) &Image$$NS_REGION_0_PAD$$Base - 1) +#elif defined(__GNUC__) +extern const uint32_t __ns_region_0_end; +#define SAU_INIT_END0 ((uint32_t) &__ns_region_0_end - 1) +#elif defined(__ICCARM__) +extern const uint32_t NS_REGION_0$$Limit; +#define SAU_INIT_END0 ((uint32_t) &NS_REGION_0$$Limit - 1) +#else +#error Unknown compiler. +#endif + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) +*/ +#define TZ_FPU_NS_USAGE 0 + +/* +// Floating Point and Vector Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + do { \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U; \ + } while (0) + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup(void) +{ + +#if defined(__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + +#if defined(SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); +#endif + +#if defined(SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); +#endif + +#if defined(SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); +#endif + +#if defined(SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); +#endif + +#if defined(SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); +#endif + +#if defined(SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); +#endif + +#if defined(SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); +#endif + +#if defined(SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); +#endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +#if defined(SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk); +#endif + +#if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = + (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); +#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + +#if (((defined(__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ + (defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) + + SCB->NSACR = + (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = + (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); +#endif + +#if defined(NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; +#endif + +#if defined(NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; +#endif + +#if defined(NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; +#endif + +#if defined(NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; +#endif + +#if defined(NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; +#endif + +#if defined(NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; +#endif + +#if defined(NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; +#endif + +#if defined(NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; +#endif + +#if defined(NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; +#endif + +#if defined(NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; +#endif + +#if defined(NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; +#endif + +#if defined(NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; +#endif + +#if defined(NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; +#endif + +#if defined(NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; +#endif + +#if defined(NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; +#endif + +#if defined(NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; +#endif + + /* repeat this for all possible ITNS elements */ +} + +#endif /* APP_TZ_H */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_tz.h.base@2.1.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_tz.h.base@2.1.0 new file mode 100644 index 00000000..cc156f13 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/app_tz.h.base@2.1.0 @@ -0,0 +1,1288 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef APP_TZ_H +#define APP_TZ_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#if defined(__ARMCC_VERSION) +extern const uint32_t Image$$NS_REGION_0$$Base; +#define SAU_INIT_START0 (uint32_t) &Image$$NS_REGION_0$$Base +#elif defined(__GNUC__) +extern const uint32_t __ns_region_0_start; +#define SAU_INIT_START0 (uint32_t) &__ns_region_0_start +#elif defined(__ICCARM__) +extern const uint32_t NS_REGION_0$$Base; +#define SAU_INIT_START0 (uint32_t) &NS_REGION_0$$Base +#else +#error Unknown compiler. +#endif + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#if defined(__ARMCC_VERSION) +extern const uint32_t Image$$NS_REGION_0_PAD$$Base; +#define SAU_INIT_END0 ((uint32_t) &Image$$NS_REGION_0_PAD$$Base - 1) +#elif defined(__GNUC__) +extern const uint32_t __ns_region_0_end; +#define SAU_INIT_END0 ((uint32_t) &__ns_region_0_end - 1) +#elif defined(__ICCARM__) +extern const uint32_t NS_REGION_0$$Limit; +#define SAU_INIT_END0 ((uint32_t) &NS_REGION_0$$Limit - 1) +#else +#error Unknown compiler. +#endif + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 0 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) +*/ +#define TZ_FPU_NS_USAGE 0 + +/* +// Floating Point and Vector Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 0 + +/* +// Interrupts 0..31 +// Interrupt 0 <0=> Secure state <1=> Non-Secure state +// Interrupt 1 <0=> Secure state <1=> Non-Secure state +// Interrupt 2 <0=> Secure state <1=> Non-Secure state +// Interrupt 3 <0=> Secure state <1=> Non-Secure state +// Interrupt 4 <0=> Secure state <1=> Non-Secure state +// Interrupt 5 <0=> Secure state <1=> Non-Secure state +// Interrupt 6 <0=> Secure state <1=> Non-Secure state +// Interrupt 7 <0=> Secure state <1=> Non-Secure state +// Interrupt 8 <0=> Secure state <1=> Non-Secure state +// Interrupt 9 <0=> Secure state <1=> Non-Secure state +// Interrupt 10 <0=> Secure state <1=> Non-Secure state +// Interrupt 11 <0=> Secure state <1=> Non-Secure state +// Interrupt 12 <0=> Secure state <1=> Non-Secure state +// Interrupt 13 <0=> Secure state <1=> Non-Secure state +// Interrupt 14 <0=> Secure state <1=> Non-Secure state +// Interrupt 15 <0=> Secure state <1=> Non-Secure state +// Interrupt 16 <0=> Secure state <1=> Non-Secure state +// Interrupt 17 <0=> Secure state <1=> Non-Secure state +// Interrupt 18 <0=> Secure state <1=> Non-Secure state +// Interrupt 19 <0=> Secure state <1=> Non-Secure state +// Interrupt 20 <0=> Secure state <1=> Non-Secure state +// Interrupt 21 <0=> Secure state <1=> Non-Secure state +// Interrupt 22 <0=> Secure state <1=> Non-Secure state +// Interrupt 23 <0=> Secure state <1=> Non-Secure state +// Interrupt 24 <0=> Secure state <1=> Non-Secure state +// Interrupt 25 <0=> Secure state <1=> Non-Secure state +// Interrupt 26 <0=> Secure state <1=> Non-Secure state +// Interrupt 27 <0=> Secure state <1=> Non-Secure state +// Interrupt 28 <0=> Secure state <1=> Non-Secure state +// Interrupt 29 <0=> Secure state <1=> Non-Secure state +// Interrupt 30 <0=> Secure state <1=> Non-Secure state +// Interrupt 31 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 0 + +/* +// Interrupts 32..63 +// Interrupt 32 <0=> Secure state <1=> Non-Secure state +// Interrupt 33 <0=> Secure state <1=> Non-Secure state +// Interrupt 34 <0=> Secure state <1=> Non-Secure state +// Interrupt 35 <0=> Secure state <1=> Non-Secure state +// Interrupt 36 <0=> Secure state <1=> Non-Secure state +// Interrupt 37 <0=> Secure state <1=> Non-Secure state +// Interrupt 38 <0=> Secure state <1=> Non-Secure state +// Interrupt 39 <0=> Secure state <1=> Non-Secure state +// Interrupt 40 <0=> Secure state <1=> Non-Secure state +// Interrupt 41 <0=> Secure state <1=> Non-Secure state +// Interrupt 42 <0=> Secure state <1=> Non-Secure state +// Interrupt 43 <0=> Secure state <1=> Non-Secure state +// Interrupt 44 <0=> Secure state <1=> Non-Secure state +// Interrupt 45 <0=> Secure state <1=> Non-Secure state +// Interrupt 46 <0=> Secure state <1=> Non-Secure state +// Interrupt 47 <0=> Secure state <1=> Non-Secure state +// Interrupt 48 <0=> Secure state <1=> Non-Secure state +// Interrupt 49 <0=> Secure state <1=> Non-Secure state +// Interrupt 50 <0=> Secure state <1=> Non-Secure state +// Interrupt 51 <0=> Secure state <1=> Non-Secure state +// Interrupt 52 <0=> Secure state <1=> Non-Secure state +// Interrupt 53 <0=> Secure state <1=> Non-Secure state +// Interrupt 54 <0=> Secure state <1=> Non-Secure state +// Interrupt 55 <0=> Secure state <1=> Non-Secure state +// Interrupt 56 <0=> Secure state <1=> Non-Secure state +// Interrupt 57 <0=> Secure state <1=> Non-Secure state +// Interrupt 58 <0=> Secure state <1=> Non-Secure state +// Interrupt 59 <0=> Secure state <1=> Non-Secure state +// Interrupt 60 <0=> Secure state <1=> Non-Secure state +// Interrupt 61 <0=> Secure state <1=> Non-Secure state +// Interrupt 62 <0=> Secure state <1=> Non-Secure state +// Interrupt 63 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + do { \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U; \ + } while (0) + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup(void) +{ + +#if defined(__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + +#if defined(SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); +#endif + +#if defined(SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); +#endif + +#if defined(SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); +#endif + +#if defined(SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); +#endif + +#if defined(SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); +#endif + +#if defined(SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); +#endif + +#if defined(SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); +#endif + +#if defined(SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); +#endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +#if defined(SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk); +#endif + +#if defined(SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = + (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); +#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + +#if (((defined(__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined(__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ + (defined(TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) + + SCB->NSACR = + (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = + (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos) & FPU_FPCCR_TS_Msk) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos) & FPU_FPCCR_CLRONRET_Msk); +#endif + +#if defined(NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; +#endif + +#if defined(NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; +#endif + +#if defined(NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; +#endif + +#if defined(NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; +#endif + +#if defined(NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; +#endif + +#if defined(NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; +#endif + +#if defined(NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; +#endif + +#if defined(NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; +#endif + +#if defined(NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; +#endif + +#if defined(NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; +#endif + +#if defined(NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; +#endif + +#if defined(NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; +#endif + +#if defined(NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; +#endif + +#if defined(NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; +#endif + +#if defined(NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; +#endif + +#if defined(NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; +#endif + + /* repeat this for all possible ITNS elements */ +} + +#endif /* APP_TZ_H */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/core_config.h b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/core_config.h new file mode 100644 index 00000000..7950fe8e --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/core_config.h @@ -0,0 +1,43 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __CORE_CONFIG_H +#define __CORE_CONFIG_H + +// Map Global to Local address of TCM Alias +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable this to return aliased address in GlobalToLocal function +// Default: 0 +#define CONFIG_MAP_GLOBAL_TO_LOCAL_TCM_ALIAS 0 + +// Prefetch Control +// Prefetch Control values for Performance Improvement + +// Maximum Outstanding Line-fills <1-6> +// Defines Maximum Outstanding line-fills issued on AXI +// Default: 5 +#define MEMSYSCTL_PFCR_MAX_OS_DEFAULT_VALUE 5 + +// Maximum Look Ahead Distance <0-6> +// Defines Maximum Look Ahead distance +// Default: 6 +#define MEMSYSCTL_PFCR_MAX_LA_DEFAULT_VALUE 6 + +// Minimum Look Ahead Distance <0-6> +// Defines Minimum Look Ahead distance +// Default: 2 +#define MEMSYSCTL_PFCR_MIN_LA_DEFAULT_VALUE 2 + +// Prefetch Control + +#endif /* __CORE_CONFIG_H */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/core_config.h.base@2.1.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/core_config.h.base@2.1.0 new file mode 100644 index 00000000..7950fe8e --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/core_config.h.base@2.1.0 @@ -0,0 +1,43 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __CORE_CONFIG_H +#define __CORE_CONFIG_H + +// Map Global to Local address of TCM Alias +// <0=> DISABLE +// <1=> ENABLE +// Defines Enable this to return aliased address in GlobalToLocal function +// Default: 0 +#define CONFIG_MAP_GLOBAL_TO_LOCAL_TCM_ALIAS 0 + +// Prefetch Control +// Prefetch Control values for Performance Improvement + +// Maximum Outstanding Line-fills <1-6> +// Defines Maximum Outstanding line-fills issued on AXI +// Default: 5 +#define MEMSYSCTL_PFCR_MAX_OS_DEFAULT_VALUE 5 + +// Maximum Look Ahead Distance <0-6> +// Defines Maximum Look Ahead distance +// Default: 6 +#define MEMSYSCTL_PFCR_MAX_LA_DEFAULT_VALUE 6 + +// Minimum Look Ahead Distance <0-6> +// Defines Minimum Look Ahead distance +// Default: 2 +#define MEMSYSCTL_PFCR_MIN_LA_DEFAULT_VALUE 2 + +// Prefetch Control + +#endif /* __CORE_CONFIG_H */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/dma_config.h b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/dma_config.h new file mode 100644 index 00000000..aa80ebd3 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/dma_config.h @@ -0,0 +1,69 @@ +/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef DMA_CONFIG_H_ +#define DMA_CONFIG_H_ + +// DMA Destination Cache Control <0-7> +// State of AWCACHE[3,1:0] when the DMAC write the destination data +// Bit [2] 0 = AWCACHE[3] is LOW +// 1 = AWCACHE[3] is HIGH. +// Bit [1] 0 = AWCACHE[1] is LOW +// 1 = AWCACHE[1] is HIGH. +// Bit [0] 0 = AWCACHE[0] is LOW +// 1 = AWCACHE[0] is HIGH. +// Setting AWCACHE[3,1]=0b10 violates the AXI protocol +// Default: 0x2 +#define DMA_DEST_CACHE_CTRL 0x2 + +// DMA Source Cache Control <0-7> +// State of ARCACHE[2:0] when the DMAC reads the source data +// Bit [2] 0 = ARCACHE[2] is LOW +// 1 = ARCACHE[2] is HIGH. +// Bit [1] 0 = ARCACHE[1] is LOW +// 1 = ARCACHE[1] is HIGH. +// Bit [0] 0 = ARCACHE[0] is LOW +// 1 = ARCACHE[0] is HIGH. +// Setting ARCACHE[2:1]=0b10 violates the AXI protocol +// Default: 0x2 +#define DMA_SRC_CACHE_CTRL 0x2 + +// DMA Source Protection Control <0-7> +// State of ARPROT[2:0] when the DMAC reads the source data +// Bit [2] 0 = ARPROT[2] is LOW +// 1 = ARPROT[2] is HIGH. +// Bit [1] 0 = ARPROT[1] is LOW +// 1 = ARPROT[1] is HIGH. +// Bit [0] 0 = ARPROT[0] is LOW +// 1 = ARPROT[0] is HIGH. +// Only DMA channels in the Secure state can program ARPROT[1] LOW +// Default: 0x0 +#define DMA_SRC_PROT_CTRL 0x0 + +// DMA Destination Protection Control <0-7> +// State of AWPROT[2:0] when the DMAC write the destination data +// Bit [2] 0 = AWPROT[2] is LOW +// 1 = AWPROT[2] is HIGH. +// Bit [1] 0 = AWPROT[1] is LOW +// 1 = AWPROT[1] is HIGH. +// Bit [0] 0 = AWPROT[0] is LOW +// 1 = AWPROT[0] is HIGH. +// Only DMA channels in the Secure state can program AWPROT[1] LOW +// Default: 0x0 +#define DMA_DEST_PROT_CTRL 0x0 + +// DMA Microcode size +// Defines Default memory size(bytes) to hold the microcode for a channel +// Default: 128 +#define DMA_MICROCODE_SIZE 128 + +#endif /* DMA_CONFIG_H_ */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/dma_config.h.base@2.1.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/dma_config.h.base@2.1.0 new file mode 100644 index 00000000..aa80ebd3 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/dma_config.h.base@2.1.0 @@ -0,0 +1,69 @@ +/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef DMA_CONFIG_H_ +#define DMA_CONFIG_H_ + +// DMA Destination Cache Control <0-7> +// State of AWCACHE[3,1:0] when the DMAC write the destination data +// Bit [2] 0 = AWCACHE[3] is LOW +// 1 = AWCACHE[3] is HIGH. +// Bit [1] 0 = AWCACHE[1] is LOW +// 1 = AWCACHE[1] is HIGH. +// Bit [0] 0 = AWCACHE[0] is LOW +// 1 = AWCACHE[0] is HIGH. +// Setting AWCACHE[3,1]=0b10 violates the AXI protocol +// Default: 0x2 +#define DMA_DEST_CACHE_CTRL 0x2 + +// DMA Source Cache Control <0-7> +// State of ARCACHE[2:0] when the DMAC reads the source data +// Bit [2] 0 = ARCACHE[2] is LOW +// 1 = ARCACHE[2] is HIGH. +// Bit [1] 0 = ARCACHE[1] is LOW +// 1 = ARCACHE[1] is HIGH. +// Bit [0] 0 = ARCACHE[0] is LOW +// 1 = ARCACHE[0] is HIGH. +// Setting ARCACHE[2:1]=0b10 violates the AXI protocol +// Default: 0x2 +#define DMA_SRC_CACHE_CTRL 0x2 + +// DMA Source Protection Control <0-7> +// State of ARPROT[2:0] when the DMAC reads the source data +// Bit [2] 0 = ARPROT[2] is LOW +// 1 = ARPROT[2] is HIGH. +// Bit [1] 0 = ARPROT[1] is LOW +// 1 = ARPROT[1] is HIGH. +// Bit [0] 0 = ARPROT[0] is LOW +// 1 = ARPROT[0] is HIGH. +// Only DMA channels in the Secure state can program ARPROT[1] LOW +// Default: 0x0 +#define DMA_SRC_PROT_CTRL 0x0 + +// DMA Destination Protection Control <0-7> +// State of AWPROT[2:0] when the DMAC write the destination data +// Bit [2] 0 = AWPROT[2] is LOW +// 1 = AWPROT[2] is HIGH. +// Bit [1] 0 = AWPROT[1] is LOW +// 1 = AWPROT[1] is HIGH. +// Bit [0] 0 = AWPROT[0] is LOW +// 1 = AWPROT[0] is HIGH. +// Only DMA channels in the Secure state can program AWPROT[1] LOW +// Default: 0x0 +#define DMA_DEST_PROT_CTRL 0x0 + +// DMA Microcode size +// Defines Default memory size(bytes) to hold the microcode for a channel +// Default: 128 +#define DMA_MICROCODE_SIZE 128 + +#endif /* DMA_CONFIG_H_ */ diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct new file mode 100644 index 00000000..3959b3d2 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct @@ -0,0 +1,123 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_MRAM_HP_BASE +#define __ROM_SIZE APP_CODE_MRAM_SIZE + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + * (.itcm*) ; Objects targeting ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + * (.*dtcm*) ; Objects targeting DTCM + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + + MRAM_USER APP_MRAM_USER_BASE APP_MRAM_USER_SIZE { + * (.mram_user) + * (.mram_user_bss) + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.bss.*) + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.bss.*) + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } + +#endif + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.0 new file mode 100644 index 00000000..ecf1f17b --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_mram.sct.base@2.2.0 @@ -0,0 +1,119 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_MRAM_HP_BASE +#define __ROM_SIZE APP_CODE_MRAM_SIZE + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + + MRAM_USER APP_MRAM_USER_BASE APP_MRAM_USER_SIZE { + * (.mram_user) + * (.mram_user_bss) + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } + +#endif + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct new file mode 100644 index 00000000..f0a07a01 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct @@ -0,0 +1,114 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_OSPI_FLASH_HP_BASE +#define __ROM_SIZE APP_OSPI_FLASH_HP_SIZE + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } + +#endif + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 new file mode 100644 index 00000000..f0a07a01 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_ospi_boot.sct.base@2.1.0 @@ -0,0 +1,114 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_OSPI_FLASH_HP_BASE +#define __ROM_SIZE APP_OSPI_FLASH_HP_SIZE + +#define __ITCM_BASE APP_ITCM_BASE +#define __ITCM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + ITCM_RAM __ITCM_BASE __ITCM_SIZE { ; RW code + ; Specify objects intended to execute out of ITCM + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } + +#endif + PADDING +0 OVERLAY ALIGN 16 FILL 0 16 + { + } +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct new file mode 100644 index 00000000..f5b0f486 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct @@ -0,0 +1,114 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_ITCM_BASE +#define __ROM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + * (.*itcm*) ; Objects targeting ITCM + + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + * (.*dtcm*) ; Objects targeting DTCM + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + * (.rodata.usbd0_device_descriptor) + * (.rodata.usbd0_device_qualifier_hs) + * (.rodata.usbd0_config_descriptor_hs) + * (.rodata.usbd0_other_speed_config_descriptor_hs) + * (.rodata.usbd0_string_descriptor) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.bss.*) + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + * (.bss.*) + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } +#endif +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.0 new file mode 100644 index 00000000..6521f7b5 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_ac6_tcm.sct.base@2.1.0 @@ -0,0 +1,109 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m55 -xc +; command above MUST be in first line (no comment above!) + +#include "app_mem_regions.h" + +#define __ROM_BASE APP_ITCM_BASE +#define __ROM_SIZE APP_HP_ITCM_SIZE + +#define __RAM_BASE APP_DTCM_BASE +#define __RAM_SIZE APP_HP_DTCM_SIZE + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00008000 + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ +#define __APP_HEAP_BASE (AlignExpr(+0, 8)) /* starts after HEAP, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE - __APP_HEAP_SIZE) + +LR_ROM __ROM_BASE __ROM_SIZE { ; load region size_region + ER_ROM_VECTORS (AlignExpr(__ROM_BASE, 2048)) { ; Vector Table + *vectors.o (RESET, +First) + } + + ER_ROM (AlignExpr(+0, 8)) { ; load address = execution address + *(InRoot$$Sections) + + ; These should be part of primary load region + *startup*.o (+RO) + *system*.o (+RO) + *sys_*.o (+RO) + *pm*.o (+RO) + *tgu*.o (+RO) + *mpu*.o (+RO) + *sau_tcm_ns_setup*.o (+RO) + + .ANY (+RO) + .ANY (+XO) + } + + RW_RAM __RW_BASE __RW_SIZE { ; RW data + .ANY (+RW +ZI) + } + + NS_REGION_0 (AlignExpr(+0, TGU_BLOCK_SIZE)) { ; Non secure region 0 + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + * (.rodata.usbd0_device_descriptor) + * (.rodata.usbd0_device_qualifier_hs) + * (.rodata.usbd0_config_descriptor_hs) + * (.rodata.usbd0_other_speed_config_descriptor_hs) + * (.rodata.usbd0_string_descriptor) + } + + NS_REGION_0_PAD (AlignExpr(ImageLimit(NS_REGION_0), TGU_BLOCK_SIZE)) { ; Non secure region 0 Padding + } + ScatterAssert((ImageBase(NS_REGION_0_PAD) - ImageBase(NS_REGION_0) + ImageLength(RW_RAM)) < __RW_SIZE) + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + APP_HEAP __APP_HEAP_BASE EMPTY __APP_HEAP_SIZE {; Reserve empty region for application heap + } + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } + +#if (SRAM0_SRAM1_COMBINED == 1) + RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } +#else + RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. + * (.bss.lcd_frame_buf) ; LCD frame Buffer. + * (.bss.camera_frame_buf) ; Camera Frame Buffer + * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. + } + + /* + * Note: + * The below empty regions are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + + RW_SRAM1 APP_SRAM1_BASE APP_SRAM1_SIZE { ; Update sections as needed + + } +#endif +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_mram.ld.src b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_mram.ld.src new file mode 100644 index 00000000..6f0b9e9d --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_mram.ld.src @@ -0,0 +1,308 @@ +/* This file was ported to work on Alif Semiconductor family of devices. */ + +/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "app_mem_regions.h" + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00004000 +#define __ROM_BASE APP_MRAM_HP_BASE +#define __ROM_SIZE APP_CODE_MRAM_SIZE + +/* + * Note: + * The empty regions(eg SRAM1) are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + +MEMORY +{ + ITCM (rwx) : ORIGIN = APP_ITCM_BASE , LENGTH = APP_HP_ITCM_SIZE + DTCM (rwx) : ORIGIN = APP_DTCM_BASE , LENGTH = APP_HP_DTCM_SIZE + #if __HAS_BULK_SRAM + SRAM0 (rwx) : ORIGIN = APP_SRAM0_BASE, LENGTH = APP_SRAM0_SIZE + SRAM1 (rwx) : ORIGIN = APP_SRAM1_BASE, LENGTH = APP_SRAM1_SIZE + #endif + MRAM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + MRAM_USER (rw) : ORIGIN = APP_MRAM_USER_BASE, LENGTH = APP_MRAM_USER_SIZE +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + + /DISCARD/ : + { + *(.ARM.exidx*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .startup.at_mram : ALIGN(2048) + { + KEEP(*(.vectors)) + + *startup*(.text* .rodata*) + *system*(.text* .rodata*) + *sys_*(.text* .rodata*) + *pm*(.text* .rodata*) + *tgu*(.text* .rodata*) + *mpu*(.text* .rodata*) + *sau_tcm_ns_setup*(.text* .rodata*) + + *lv_*(.text* .rodata*) + + . = ALIGN(16); + } > MRAM + + .copy.table : ALIGN(4) + { + __copy_table_start__ = .; + LONG ( LOADADDR(.data.at_dtcm) ) + LONG ( ADDR(.data.at_dtcm) ) + LONG ( SIZEOF(.data.at_dtcm)/4 ) + LONG ( LOADADDR(.code.at_itcm) ) + LONG ( ADDR(.code.at_itcm) ) + LONG ( SIZEOF(.code.at_itcm)/4 ) + __copy_table_end__ = .; + . = ALIGN(16); + } > MRAM + + .zero.table : ALIGN(4) + { + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss)/4) +#if __HAS_BULK_SRAM + LONG (ADDR(.bss.at_sram0)) + LONG (SIZEOF(.bss.at_sram0)/4) +#endif + __zero_table_end__ = .; + . = ALIGN(16); + } > MRAM + + /* Caution: .got, .tdata and .tbss sections come under + * RELRO section. So keep it adjacent one after another. + */ + .got : ALIGN(8) + { + *(.got) + *(.got*) + *(.data.rel.ro) + *(.data.rel.ro*) + *(.got.plt) + . = ALIGN(16); + } > MRAM + + /* Thread Local Storage sections */ + .tdata.at_mram : ALIGN(16) + { + /* TLS base = beginning of TLS block */ + __tls_base = .; + /* Offset inside TLS block where TCB is expected */ + __arm32_tls_tcb_offset = .; + /* Initialized TLS variables */ + *(.tdata .tdata.* .gnu.linkonce.td.*) + __tdata_end = .; + . = ALIGN(16); + } > MRAM + + /* Thread-Local Uninitialized Data (.tbss) */ + .tbss (NOLOAD) : ALIGN(16) + { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + /* TLS commons here */ + *(.tcommon) + __tbss_end = .; + . = ALIGN(16); + } > MRAM + + .code.at_itcm : ALIGN(8) + { + *(.text*) + *(.itcm*) /* Object targeting ITCM */ + . = ALIGN(16); + } > ITCM AT > MRAM + + .data.at_dtcm : ALIGN(8) + { + *(vtable) + *(.data) + *(.data*) + *arm_common_tables*(.data* .rodata*) + + KEEP(*(.jcr*)) + + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + . = ALIGN(16); + } > DTCM AT > MRAM + +#if __HAS_BULK_SRAM + .bss.at_sram0 (NOLOAD) : ALIGN(8) + { + *(.bss.lcd_crop_and_interpolate_buf) /* LCD crop and intrepolate image processing buffer. */ + *(.bss.lcd_frame_buf) /* LCD frame Buffer. */ + *(.bss.camera_frame_buf) /* Camer Frame Buffer */ + *(.bss.camera_frame_bayer_to_rgb_buf) /* (Optional) Camera Frame Buffer for Bayer to RGB Conversion. */ + } > SRAM0 +#endif + + .bss (NOLOAD) : ALIGN(8) + { + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(8); + __bss_end__ = .; + } > DTCM + + .nonsecure0_region (NOLOAD) : + { + . = ALIGN(TGU_BLOCK_SIZE); + __ns_region_0_start = .; + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + . = ALIGN(TGU_BLOCK_SIZE); + __ns_region_0_end = .; + } > DTCM + + .__app_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN(8); + __RAM_segment_used_end__ = .; + . = . + __APP_HEAP_SIZE; + . = ALIGN(8); + } > DTCM + + .heap (NOLOAD) : ALIGN(8) + { + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > DTCM + + .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (NOLOAD) : ALIGN(8) + { + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM + PROVIDE(__stack = __StackTop); + + .readonly.at_mram : ALIGN(8) + { + /* Use wildcards to mop up any read-only not directed to TCM */ + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + PROVIDE_HIDDEN (__bothinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + PROVIDE_HIDDEN (__bothinit_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + . = ALIGN(16); + } > MRAM + + .mram_user (NOLOAD) : ALIGN(16) + { + __mram_user_start__ = .; + *(.mram_user) + *(.mram_user*) + . = ALIGN(16); + __mram_user_end__ = .; + } > MRAM_USER + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Picolib crt on clang compiler requires below definitions for data and bss sections copy. + * We have multiple sections at diff memory locations to copy e.g. itcm, dtcm etc. + * but the __start of picolib copies one section only. + * So, setting data and bss defines to zero to skip it. + */ + PROVIDE(__stack_limit = __StackLimit); + PROVIDE(__data_start = 0); + PROVIDE(__data_source = 0); + PROVIDE(__data_size = 0); + PROVIDE(__bss_start = 0); + PROVIDE(__bss_size = 0); + PROVIDE(__heap_start = 0); + PROVIDE(__heap_end = 0); + + /* TLS helper sizes */ + __tdata_size = __tdata_end - __tls_base; + __tbss_size = __tbss_end - __tdata_end; + __tls_end = __tbss_end; +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_mram.ld.src.base@2.2.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_mram.ld.src.base@2.2.0 new file mode 100644 index 00000000..29194e5d --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_mram.ld.src.base@2.2.0 @@ -0,0 +1,305 @@ +/* This file was ported to work on Alif Semiconductor family of devices. */ + +/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "app_mem_regions.h" + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00004000 +#define __ROM_BASE APP_MRAM_HP_BASE +#define __ROM_SIZE APP_CODE_MRAM_SIZE + +/* + * Note: + * The empty regions(eg SRAM1) are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + +MEMORY +{ + ITCM (rwx) : ORIGIN = APP_ITCM_BASE , LENGTH = APP_HP_ITCM_SIZE + DTCM (rwx) : ORIGIN = APP_DTCM_BASE , LENGTH = APP_HP_DTCM_SIZE + #if __HAS_BULK_SRAM + SRAM0 (rwx) : ORIGIN = APP_SRAM0_BASE, LENGTH = APP_SRAM0_SIZE + SRAM1 (rwx) : ORIGIN = APP_SRAM1_BASE, LENGTH = APP_SRAM1_SIZE + #endif + MRAM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + MRAM_USER (rw) : ORIGIN = APP_MRAM_USER_BASE, LENGTH = APP_MRAM_USER_SIZE +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + + /DISCARD/ : + { + *(.ARM.exidx*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .startup.at_mram : ALIGN(2048) + { + KEEP(*(.vectors)) + + *startup*(.text .rodata*) + *system*(.text .rodata*) + *sys_*(.text .rodata*) + *pm*(.text .rodata*) + *tgu*(.text .rodata*) + *mpu*(.text .rodata*) + *sau_tcm_ns_setup*(.text .rodata*) + + *lv_*(.text .rodata*) + + . = ALIGN(16); + } > MRAM + + .copy.table : ALIGN(4) + { + __copy_table_start__ = .; + LONG ( LOADADDR(.data.at_dtcm) ) + LONG ( ADDR(.data.at_dtcm) ) + LONG ( SIZEOF(.data.at_dtcm)/4 ) + LONG ( LOADADDR(.code.at_itcm) ) + LONG ( ADDR(.code.at_itcm) ) + LONG ( SIZEOF(.code.at_itcm)/4 ) + __copy_table_end__ = .; + . = ALIGN(16); + } > MRAM + + .zero.table : ALIGN(4) + { + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss)/4) +#if __HAS_BULK_SRAM + LONG (ADDR(.bss.at_sram0)) + LONG (SIZEOF(.bss.at_sram0)/4) +#endif + __zero_table_end__ = .; + . = ALIGN(16); + } > MRAM + + /* Caution: .got, .tdata and .tbss sections come under + * RELRO section. So keep it adjacent one after another. + */ + .got : ALIGN(8) + { + *(.got) + *(.got*) + *(.data.rel.ro) + *(.data.rel.ro*) + *(.got.plt) + . = ALIGN(16); + } > MRAM + + /* Thread Local Storage sections */ + .tdata.at_mram : ALIGN(16) + { + /* TLS base = beginning of TLS block */ + __tls_base = .; + /* Offset inside TLS block where TCB is expected */ + __arm32_tls_tcb_offset = .; + /* Initialized TLS variables */ + *(.tdata .tdata.* .gnu.linkonce.td.*) + __tdata_end = .; + . = ALIGN(16); + } > MRAM + + /* Thread-Local Uninitialized Data (.tbss) */ + .tbss (NOLOAD) : ALIGN(16) + { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + /* TLS commons here */ + *(.tcommon) + __tbss_end = .; + . = ALIGN(16); + } > MRAM + + .code.at_itcm : ALIGN(8) + { + *(.text*) + . = ALIGN(16); + } > ITCM AT > MRAM + + .data.at_dtcm : ALIGN(8) + { + *(vtable) + *(.data) + *(.data*) + *arm_common_tables*(.data* .rodata*) + + KEEP(*(.jcr*)) + + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + . = ALIGN(16); + } > DTCM AT > MRAM + +#if __HAS_BULK_SRAM + .bss.at_sram0 (NOLOAD) : ALIGN(8) + { + *(.bss.lcd_crop_and_interpolate_buf) /* LCD crop and intrepolate image processing buffer. */ + *(.bss.lcd_frame_buf) /* LCD frame Buffer. */ + *(.bss.camera_frame_buf) /* Camer Frame Buffer */ + *(.bss.camera_frame_bayer_to_rgb_buf) /* (Optional) Camera Frame Buffer for Bayer to RGB Conversion. */ + } > SRAM0 +#endif + + .bss (NOLOAD) : ALIGN(8) + { + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(8); + __bss_end__ = .; + } > DTCM + + .nonsecure0_region (NOLOAD) : + { + . = ALIGN(TGU_BLOCK_SIZE); + __ns_region_0_start = .; + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + . = ALIGN(TGU_BLOCK_SIZE); + __ns_region_0_end = .; + } > DTCM + + .__app_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN(8); + __RAM_segment_used_end__ = .; + . = . + __APP_HEAP_SIZE; + . = ALIGN(8); + } > DTCM + + .heap (NOLOAD) : ALIGN(8) + { + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > DTCM + + .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (NOLOAD) : ALIGN(8) + { + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM + PROVIDE(__stack = __StackTop); + + .readonly.at_mram : ALIGN(8) + { + /* Use wildcards to mop up any read-only not directed to TCM */ + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + . = ALIGN(16); + } > MRAM + + .mram_user (NOLOAD) : ALIGN(16) + { + __mram_user_start__ = .; + *(.mram_user) + *(.mram_user*) + . = ALIGN(16); + __mram_user_end__ = .; + } > MRAM_USER + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Picolib crt on clang compiler requires below definitions for data and bss sections copy. + * We have multiple sections at diff memory locations to copy e.g. itcm, dtcm etc. + * but the __start of picolib copies one section only. + * So, setting data and bss defines to zero to skip it. + */ + PROVIDE(__stack_limit = __StackLimit); + PROVIDE(__data_start = 0); + PROVIDE(__data_source = 0); + PROVIDE(__data_size = 0); + PROVIDE(__bss_start = 0); + PROVIDE(__bss_size = 0); + PROVIDE(__heap_start = 0); + PROVIDE(__heap_end = 0); + + /* TLS helper sizes */ + __tdata_size = __tdata_end - __tls_base; + __tbss_size = __tbss_end - __tdata_end; + __tls_end = __tbss_end; +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_tcm.ld.src b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_tcm.ld.src new file mode 100644 index 00000000..f1ef7940 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_tcm.ld.src @@ -0,0 +1,292 @@ +/* This file was ported to work on Alif Semiconductor Ensemble family of devices. */ + +/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "app_mem_regions.h" + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00004000 + +/* + * Note: + * The empty regions(eg SRAM1) are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + +MEMORY +{ + ITCM (rwx) : ORIGIN = APP_ITCM_BASE , LENGTH = APP_HP_ITCM_SIZE + DTCM (rwx) : ORIGIN = APP_DTCM_BASE , LENGTH = APP_HP_DTCM_SIZE + #if __HAS_BULK_SRAM + SRAM0 (rwx) : ORIGIN = APP_SRAM0_BASE, LENGTH = APP_SRAM0_SIZE + SRAM1 (rwx) : ORIGIN = APP_SRAM1_BASE, LENGTH = APP_SRAM1_SIZE + #endif +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + /DISCARD/ : + { + *(.ARM.exidx*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .startup.at_itcm : ALIGN(2048) + { + KEEP(*(.vectors)) + + *startup*(.text* .rodata*) + *system*(.text* .rodata*) + *sys_*(.text* .rodata*) + *pm*(.text* .rodata*) + *tgu*(.text* .rodata*) + *mpu*(.text* .rodata*) + *sau_tcm_ns_setup*(.text* .rodata*) + + *lv_*(.text* .rodata*) + + } > ITCM + + .copy.table : ALIGN(4) + { + __copy_table_start__ = .; + LONG ( LOADADDR(.data.at_dtcm) ) + LONG ( ADDR(.data.at_dtcm) ) + LONG ( SIZEOF(.data.at_dtcm)/4 ) + + LONG ( LOADADDR(.nonsecure0_region_load) ) + LONG ( ADDR(.nonsecure0_region_load) ) + LONG ( SIZEOF(.nonsecure0_region_load)/4 ) + __copy_table_end__ = .; + } > ITCM + + .zero.table : ALIGN(4) + { + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss)/4) +#if __HAS_BULK_SRAM + LONG (ADDR(.bss.at_sram0)) + LONG (SIZEOF(.bss.at_sram0)/4) +#endif + __zero_table_end__ = .; + } > ITCM + + /* Caution: .got, .tdata and .tbss sections come under + * RELRO section. So keep it adjacent one after another. + */ + .got : ALIGN(4) + { + *(.got) + *(.got*) + *(.data.rel.ro) + *(.data.rel.ro*) + *(.got.plt) + } > ITCM + + /* Thread Local Storage (.tdata) */ + .tdata.at_itcm : ALIGN(8) + { + /* TLS base = beginning of TLS block */ + __tls_base = .; + /* Offset inside TLS block where TCB is expected */ + __arm32_tls_tcb_offset = .; + /* Initialized TLS variables */ + *(.tdata .tdata.* .gnu.linkonce.td.*) + __tdata_end = .; + } > ITCM + + /* Thread-Local Uninitialized Data (.tbss) */ + .tbss (NOLOAD) : ALIGN(8) + { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + /* TLS commons here */ + *(.tcommon) + __tbss_end = .; + } > ITCM + + .code.at_itcm : ALIGN(8) + { + *(.text*) + *(.itcm*) /* Object targeting ITCM */ + } > ITCM + + .data.at_dtcm : ALIGN(8) + { + *(vtable) + *(.data) + *(.data*) + *(.dtcm*) /* Objects targeting DTCM */ + *arm_common_tables*(.data* .rodata*) + + KEEP(*(.jcr*)) + + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + + } > DTCM AT > ITCM + +#if __HAS_BULK_SRAM + .bss.at_sram0 (NOLOAD) : ALIGN(8) + { + *(.bss.lcd_crop_and_interpolate_buf) /* LCD crop and intrepolate image processing buffer. */ + *(.bss.lcd_frame_buf) /* LCD frame Buffer. */ + *(.bss.camera_frame_buf) /* Camer Frame Buffer */ + *(.bss.camera_frame_bayer_to_rgb_buf) /* (Optional) Camera Frame Buffer for Bayer to RGB Conversion. */ + } > SRAM0 +#endif + + .bss (NOLOAD) : ALIGN(8) + { + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(8); + __bss_end__ = .; + } > DTCM + + .nonsecure0_region_load : + { + . = ALIGN(TGU_BLOCK_SIZE); + __ns_region_0_start = .; + *usbd_config*(.rodata*) + } > DTCM AT > ITCM + .nonsecure0_region_noload (NOLOAD) : + { + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + . = ALIGN(TGU_BLOCK_SIZE); + __ns_region_0_end = .; + } > DTCM + + .__app_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN(8); + __RAM_segment_used_end__ = .; + . = . + __APP_HEAP_SIZE; + . = ALIGN(8); + } > DTCM + + .heap (NOLOAD) : ALIGN(8) + { + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > DTCM + + .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (NOLOAD) : ALIGN(8) + { + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM + PROVIDE(__stack = __StackTop); + + .readonly.at_itcm : ALIGN(8) + { + /* Use wildcards to mop up any read-only not directed to TCM */ + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + PROVIDE_HIDDEN (__bothinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + PROVIDE_HIDDEN (__bothinit_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > ITCM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Picolib crt on clang compiler requires below definitions for data and bss sections copy. + * We have multiple sections at diff memory locations to copy e.g. itcm, dtcm etc. + * but the __start of picolib copies one section only. + * So, setting data and bss defines to zero to skip it. + */ + PROVIDE(__stack_limit = __StackLimit); + PROVIDE(__data_start = 0); + PROVIDE(__data_source = 0); + PROVIDE(__data_size = 0); + PROVIDE(__bss_start = 0); + PROVIDE(__bss_size = 0); + PROVIDE(__heap_start = 0); + PROVIDE(__heap_end = 0); + + /* TLS helper sizes */ + __tdata_size = __tdata_end - __tls_base; + __tbss_size = __tbss_end - __tdata_end; + __tls_end = __tbss_end; +} diff --git a/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_tcm.ld.src.base@2.1.0 b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_tcm.ld.src.base@2.1.0 new file mode 100644 index 00000000..10e93178 --- /dev/null +++ b/board/AppKit-E8/RTE/Device/AE822FA0E5597BS0_M55_HP/linker_gnu_tcm.ld.src.base@2.1.0 @@ -0,0 +1,288 @@ +/* This file was ported to work on Alif Semiconductor Ensemble family of devices. */ + +/* Copyright (C) 2023 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/* + * Copyright (c) 2021 Arm Limited. All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#include "app_mem_regions.h" + +#define __STACK_SIZE APP_HP_STACK_SIZE +#define __HEAP_SIZE APP_HP_HEAP_SIZE +#define __APP_HEAP_SIZE 0x00004000 + +/* + * Note: + * The empty regions(eg SRAM1) are ON by default, but may have been released + * by some example applications. So make sure your application requests + * power for these regions before adding contents. + */ + +MEMORY +{ + ITCM (rwx) : ORIGIN = APP_ITCM_BASE , LENGTH = APP_HP_ITCM_SIZE + DTCM (rwx) : ORIGIN = APP_DTCM_BASE , LENGTH = APP_HP_DTCM_SIZE + #if __HAS_BULK_SRAM + SRAM0 (rwx) : ORIGIN = APP_SRAM0_BASE, LENGTH = APP_SRAM0_SIZE + SRAM1 (rwx) : ORIGIN = APP_SRAM1_BASE, LENGTH = APP_SRAM1_SIZE + #endif +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + /DISCARD/ : + { + *(.ARM.exidx*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + } + + .startup.at_itcm : ALIGN(2048) + { + KEEP(*(.vectors)) + + *startup*(.text .rodata*) + *system*(.text .rodata*) + *sys_*(.text .rodata*) + *pm*(.text .rodata*) + *tgu*(.text .rodata*) + *mpu*(.text .rodata*) + *sau_tcm_ns_setup*(.text .rodata*) + + *lv_*(.text .rodata*) + + } > ITCM + + .copy.table : ALIGN(4) + { + __copy_table_start__ = .; + LONG ( LOADADDR(.data.at_dtcm) ) + LONG ( ADDR(.data.at_dtcm) ) + LONG ( SIZEOF(.data.at_dtcm)/4 ) + + LONG ( LOADADDR(.nonsecure0_region_load) ) + LONG ( ADDR(.nonsecure0_region_load) ) + LONG ( SIZEOF(.nonsecure0_region_load)/4 ) + __copy_table_end__ = .; + } > ITCM + + .zero.table : ALIGN(4) + { + __zero_table_start__ = .; + LONG (ADDR(.bss)) + LONG (SIZEOF(.bss)/4) +#if __HAS_BULK_SRAM + LONG (ADDR(.bss.at_sram0)) + LONG (SIZEOF(.bss.at_sram0)/4) +#endif + __zero_table_end__ = .; + } > ITCM + + /* Caution: .got, .tdata and .tbss sections come under + * RELRO section. So keep it adjacent one after another. + */ + .got : ALIGN(4) + { + *(.got) + *(.got*) + *(.data.rel.ro) + *(.data.rel.ro*) + *(.got.plt) + } > ITCM + + /* Thread Local Storage (.tdata) */ + .tdata.at_itcm : ALIGN(8) + { + /* TLS base = beginning of TLS block */ + __tls_base = .; + /* Offset inside TLS block where TCB is expected */ + __arm32_tls_tcb_offset = .; + /* Initialized TLS variables */ + *(.tdata .tdata.* .gnu.linkonce.td.*) + __tdata_end = .; + } > ITCM + + /* Thread-Local Uninitialized Data (.tbss) */ + .tbss (NOLOAD) : ALIGN(8) + { + *(.tbss .tbss.* .gnu.linkonce.tb.*) + /* TLS commons here */ + *(.tcommon) + __tbss_end = .; + } > ITCM + + .code.at_itcm : ALIGN(8) + { + *(.text*) + } > ITCM + + .data.at_dtcm : ALIGN(8) + { + *(vtable) + *(.data) + *(.data*) + *arm_common_tables*(.data* .rodata*) + + KEEP(*(.jcr*)) + + . = ALIGN(8); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(8); + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + + } > DTCM AT > ITCM + +#if __HAS_BULK_SRAM + .bss.at_sram0 (NOLOAD) : ALIGN(8) + { + *(.bss.lcd_crop_and_interpolate_buf) /* LCD crop and intrepolate image processing buffer. */ + *(.bss.lcd_frame_buf) /* LCD frame Buffer. */ + *(.bss.camera_frame_buf) /* Camer Frame Buffer */ + *(.bss.camera_frame_bayer_to_rgb_buf) /* (Optional) Camera Frame Buffer for Bayer to RGB Conversion. */ + } > SRAM0 +#endif + + .bss (NOLOAD) : ALIGN(8) + { + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(8); + __bss_end__ = .; + } > DTCM + + .nonsecure0_region_load : + { + . = ALIGN(TGU_BLOCK_SIZE); + __ns_region_0_start = .; + *usbd_config*(.rodata*) + } > DTCM AT > ITCM + .nonsecure0_region_noload (NOLOAD) : + { + * (eth_buf) + * (usb_dma_buf) + * (sd_dma_buf) + * (.driver.usbd0) + . = ALIGN(TGU_BLOCK_SIZE); + __ns_region_0_end = .; + } > DTCM + + .__app_heap (NOLOAD) : ALIGN(8) + { + . = ALIGN(8); + __RAM_segment_used_end__ = .; + . = . + __APP_HEAP_SIZE; + . = ALIGN(8); + } > DTCM + + .heap (NOLOAD) : ALIGN(8) + { + __end__ = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > DTCM + + .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (NOLOAD) : ALIGN(8) + { + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > DTCM + PROVIDE(__stack = __StackTop); + + .readonly.at_itcm : ALIGN(8) + { + /* Use wildcards to mop up any read-only not directed to TCM */ + KEEP(*(.init)) + KEEP(*(.fini)) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + + KEEP(*(.eh_frame*)) + } > ITCM + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + /* Picolib crt on clang compiler requires below definitions for data and bss sections copy. + * We have multiple sections at diff memory locations to copy e.g. itcm, dtcm etc. + * but the __start of picolib copies one section only. + * So, setting data and bss defines to zero to skip it. + */ + PROVIDE(__stack_limit = __StackLimit); + PROVIDE(__data_start = 0); + PROVIDE(__data_source = 0); + PROVIDE(__data_size = 0); + PROVIDE(__bss_start = 0); + PROVIDE(__bss_size = 0); + PROVIDE(__heap_start = 0); + PROVIDE(__heap_end = 0); + + /* TLS helper sizes */ + __tdata_size = __tdata_end - __tls_base; + __tbss_size = __tbss_end - __tdata_end; + __tls_end = __tbss_end; +} diff --git a/board/AppKit-E8/RTE/Services/AE822FA0E5597BS0_M55_HP/retarget_config.h b/board/AppKit-E8/RTE/Services/AE822FA0E5597BS0_M55_HP/retarget_config.h new file mode 100644 index 00000000..ba2505c7 --- /dev/null +++ b/board/AppKit-E8/RTE/Services/AE822FA0E5597BS0_M55_HP/retarget_config.h @@ -0,0 +1,172 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/******************************************************************************* + * @file retarget_config.h + * @author Raj Ranjan + * @email raj.ranjan@alifsemi.com + * @version V1.0.0 + * @date 10-Jun-2025 + * @brief Disable Semihosting + * @bug None. + * @Note None + ******************************************************************************/ + +#ifndef RETARGET_STD_IN_OUT_CONFIG_H__ +#define RETARGET_STD_IN_OUT_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "pinconf.h" +#include "RTE_Device.h" + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// UART Console +// Select UART Console +// <0=> UART0 +// <1=> UART1 +// <2=> UART2 +// <3=> UART3 +// <4=> UART4 +// <5=> UART5 +// <6=> UART6 +// <7=> UART7 +// LPUART +// Default: 4 +#define PRINTF_UART_CONSOLE 4 + +// UART Baudrate +// Select UART Baudrate +// Default: 115200 +#define PRINTF_UART_CONSOLE_BAUD_RATE 115200 + +#define STR(x) #x +#define XSTR(x) STR(x) +#define LP 8 + +/* UART Related Macros */ +#if (PRINTF_UART_CONSOLE == LP) +#define _UART_BLOCKING_(n) RTE_LPUART_BLOCKING_MODE_ENABLE +#elif ((PRINTF_UART_CONSOLE >= 0) && (PRINTF_UART_CONSOLE <= 7)) +#define _UART_BLOCKING_(n) RTE_UART##n##_BLOCKING_MODE_ENABLE +#else +#pragma message("UART" XSTR(PRINTF_UART_CONSOLE) " NOT AVAILABLE") +#error "SELECTED UART IS NOT CORRECT" +#endif + +#define UART_BLOCKING(n) _UART_BLOCKING_(n) + +#if (UART_BLOCKING(PRINTF_UART_CONSOLE) == 0) +#if (PRINTF_UART_CONSOLE == LP) +#pragma message("Selected UART : LPUART") +#else +#pragma message("Selected UART : UART" XSTR(PRINTF_UART_CONSOLE)) +#endif + +#pragma message("NEED TO ENABLE FLAG: " XSTR(UART_BLOCKING(PRINTF_UART_CONSOLE))) + +#error \ + " ***** [RETARGET-FAILED] POLLING MODE IS NOT ENABLED (Enable Polling mode in RTE_Device.h)" \ + " !!! ****** \n" +#endif + +#if (PRINTF_UART_CONSOLE == LP) /* Instance B */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_9 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_9 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_2 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 0) /* Instance A */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_0 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_0 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_0 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 1) /* Instance A */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_0 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_0 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_4 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_5 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 2) /* Instance A */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_1 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_1 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_0 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 3) /* Instance A */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_1 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_1 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_2 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_3 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 4) /* Instance B */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_12 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_12 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_2 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 5) /* Instance B */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_11 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_11 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_3 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_4 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 6) /* Instance C */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_14 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_14 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_0 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 7) /* Instance B */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_9 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_9 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_3 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_4 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#endif /* PRINTF_UART_CONSOLE */ + +#undef LP + +#ifdef __cplusplus +} +#endif + +#endif /* RETARGET_STD_IN_OUT_H__ */ diff --git a/board/AppKit-E8/RTE/Services/AE822FA0E5597BS0_M55_HP/retarget_config.h.base@2.1.0 b/board/AppKit-E8/RTE/Services/AE822FA0E5597BS0_M55_HP/retarget_config.h.base@2.1.0 new file mode 100644 index 00000000..ba2505c7 --- /dev/null +++ b/board/AppKit-E8/RTE/Services/AE822FA0E5597BS0_M55_HP/retarget_config.h.base@2.1.0 @@ -0,0 +1,172 @@ +/* Copyright (C) 2025 Alif Semiconductor - All Rights Reserved. + * Use, distribution and modification of this code is permitted under the + * terms stated in the Alif Semiconductor Software License Agreement + * + * You should have received a copy of the Alif Semiconductor Software + * License Agreement with this file. If not, please write to: + * contact@alifsemi.com, or visit: https://alifsemi.com/license + * + */ + +/******************************************************************************* + * @file retarget_config.h + * @author Raj Ranjan + * @email raj.ranjan@alifsemi.com + * @version V1.0.0 + * @date 10-Jun-2025 + * @brief Disable Semihosting + * @bug None. + * @Note None + ******************************************************************************/ + +#ifndef RETARGET_STD_IN_OUT_CONFIG_H__ +#define RETARGET_STD_IN_OUT_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "pinconf.h" +#include "RTE_Device.h" + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// UART Console +// Select UART Console +// <0=> UART0 +// <1=> UART1 +// <2=> UART2 +// <3=> UART3 +// <4=> UART4 +// <5=> UART5 +// <6=> UART6 +// <7=> UART7 +// LPUART +// Default: 4 +#define PRINTF_UART_CONSOLE 4 + +// UART Baudrate +// Select UART Baudrate +// Default: 115200 +#define PRINTF_UART_CONSOLE_BAUD_RATE 115200 + +#define STR(x) #x +#define XSTR(x) STR(x) +#define LP 8 + +/* UART Related Macros */ +#if (PRINTF_UART_CONSOLE == LP) +#define _UART_BLOCKING_(n) RTE_LPUART_BLOCKING_MODE_ENABLE +#elif ((PRINTF_UART_CONSOLE >= 0) && (PRINTF_UART_CONSOLE <= 7)) +#define _UART_BLOCKING_(n) RTE_UART##n##_BLOCKING_MODE_ENABLE +#else +#pragma message("UART" XSTR(PRINTF_UART_CONSOLE) " NOT AVAILABLE") +#error "SELECTED UART IS NOT CORRECT" +#endif + +#define UART_BLOCKING(n) _UART_BLOCKING_(n) + +#if (UART_BLOCKING(PRINTF_UART_CONSOLE) == 0) +#if (PRINTF_UART_CONSOLE == LP) +#pragma message("Selected UART : LPUART") +#else +#pragma message("Selected UART : UART" XSTR(PRINTF_UART_CONSOLE)) +#endif + +#pragma message("NEED TO ENABLE FLAG: " XSTR(UART_BLOCKING(PRINTF_UART_CONSOLE))) + +#error \ + " ***** [RETARGET-FAILED] POLLING MODE IS NOT ENABLED (Enable Polling mode in RTE_Device.h)" \ + " !!! ****** \n" +#endif + +#if (PRINTF_UART_CONSOLE == LP) /* Instance B */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_9 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_9 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_2 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 0) /* Instance A */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_0 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_0 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_0 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 1) /* Instance A */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_0 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_0 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_4 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_5 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 2) /* Instance A */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_1 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_1 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_0 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 3) /* Instance A */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_1 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_1 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_2 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_3 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 4) /* Instance B */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_12 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_12 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_2 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 5) /* Instance B */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_11 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_11 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_3 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_4 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 6) /* Instance C */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_14 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_14 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_0 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_1 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#elif (PRINTF_UART_CONSOLE == 7) /* Instance B */ +#define PRINTF_UART_CONSOLE_RX_PORT_NUM PORT_9 +#define PRINTF_UART_CONSOLE_TX_PORT_NUM PORT_9 +#define PRINTF_UART_CONSOLE_RX_PIN PIN_3 +#define PRINTF_UART_CONSOLE_TX_PIN PIN_4 +#define PRINTF_UART_CONSOLE_RX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_2 +#define PRINTF_UART_CONSOLE_TX_PINMUX_FUNCTION PINMUX_ALTERNATE_FUNCTION_1 +#define PRINTF_UART_CONSOLE_RX_PADCTRL PADCTRL_READ_ENABLE +#define PRINTF_UART_CONSOLE_TX_PADCTRL 0 +#endif /* PRINTF_UART_CONSOLE */ + +#undef LP + +#ifdef __cplusplus +} +#endif + +#endif /* RETARGET_STD_IN_OUT_H__ */ diff --git a/board/Corstone-320/Board-U85.clayer.yml b/board/Corstone-320/Board-U85.clayer.yml index 3ba21104..7a6e914e 100644 --- a/board/Corstone-320/Board-U85.clayer.yml +++ b/board/Corstone-320/Board-U85.clayer.yml @@ -22,6 +22,10 @@ layer: - CMSIS_target_header: \"Corstone-320.h\" - ETHOSU85 - ARM_MODEL_USE_PMU_COUNTERS + # The runner saves the demo image and its measurements through semihosting + # (board_save_file in retarget_stdio.c) into this directory, relative to the + # model's working directory (the workspace): out/fvp_image.bin, out/fvp_result.txt + - APP_RESULT_DIR: \"out\" packs: - pack: ARM::CMSIS @@ -55,4 +59,7 @@ layer: - file: ./retarget_stdio.c linker: + # The linker scripts are the Device:Startup configuration files in + # RTE/Device/SSE-320-FVP/; they place the ExecuTorch program + # (.rodata.model, ~2.8 MB) in DDR (ROM2), not in the 2 MB FPGA SRAM. - regions: ./regions_SSE-320.h diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src b/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src index 7820e1f1..4cb13732 100644 --- a/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/ac6_linker_script.sct.src @@ -16,6 +16,14 @@ * limitations under the License. */ +/* Changed for the CMSIS-Executorch example (the gcc_ and clang_ scripts next + * to this one have the same changes): + * - The exported ExecuTorch program (ai_layer/model_pte.c, section + * .rodata.model, ~2.8 MB) goes to the DDR region ROM2 instead of the 2 MB + * FPGA SRAM that holds the code; the Ethos-U85 reads its weights from there. + * - RAM is a load region of its own (see LR_RAM0), and RW_RAM0 is NOCOMPRESS. + */ + /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ @@ -42,13 +50,29 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { *(Veneer$$CMSE) } #endif +} + +/* + * RAM gets its own load region rather than living inside LR_ROM0: armlink emits + * one PT_LOAD per load region and sizes it to span every execution region it + * contains. With the ExecuTorch pools (8 MB of ZI in app_main.cpp) inside + * LR_ROM0 the ELF segment based at ROM0 would claim ~9 MB, and the FVP refuses + * the image ("Failed to write bytes at address range [0x12200000..]", past the + * end of the 2 MB FPGA SRAM). The RW data is loaded straight into DDR. + */ +LR_RAM0 __RAM0_BASE __RAM0_SIZE { RW_NOINIT __RAM0_BASE UNINIT (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE) { *.o(.bss.noinit) *.o(.bss.noinit.*) } - RW_RAM0 AlignExpr(+0, 8) (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + ; NOCOMPRESS: this load region has the same base as the execution region, so + ; the image loader places the initial RW data in place. If armlink compressed + ; it, SystemInit() (which runs before the C library decompresses the region) + ; would write SystemCoreClock into the compressed blob and corrupt the data + ; that follows it (seen: the ExecuTorch PAL function table held 25000000). + RW_RAM0 AlignExpr(+0, 8) NOCOMPRESS (__RAM0_SIZE - __HEAP_SIZE - __STACK_SIZE - __STACKSEAL_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { *(+RW +ZI) } @@ -64,24 +88,6 @@ LR_ROM0 __ROM0_BASE __ROM0_SIZE { STACKSEAL +0 EMPTY __STACKSEAL_SIZE { ; Reserve empty region for stack seal immediately after stack } #endif - -#if __RAM1_SIZE > 0 - RW_RAM1 __RAM1_BASE __RAM1_SIZE { - .ANY (+RW +ZI) - } -#endif - -#if __RAM2_SIZE > 0 - RW_RAM2 __RAM2_BASE __RAM2_SIZE { - .ANY (+RW +ZI) - } -#endif - -#if __RAM3_SIZE > 0 - RW_RAM3 __RAM3_BASE __RAM3_SIZE { - .ANY (+RW +ZI) - } -#endif } #if __ROM1_SIZE > 0 @@ -95,6 +101,7 @@ LR_ROM1 __ROM1_BASE __ROM1_SIZE { #if __ROM2_SIZE > 0 LR_ROM2 __ROM2_BASE __ROM2_SIZE { ER_ROM2 +0 __ROM2_SIZE { + *(.rodata.model) ; the ExecuTorch program; a named selector outranks the +RO of ER_ROM0 .ANY (+RO +XO) } } diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/clang_linker_script.ld.src b/board/Corstone-320/RTE/Device/SSE-320-FVP/clang_linker_script.ld.src index e7ec9d02..b80f1962 100644 --- a/board/Corstone-320/RTE/Device/SSE-320-FVP/clang_linker_script.ld.src +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/clang_linker_script.ld.src @@ -33,6 +33,10 @@ * OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* Changed for the CMSIS-Executorch example: the section .rodata.model (the + * ExecuTorch program) goes to ROM2 in a program header of its own, see + * SECTIONS. */ + /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ @@ -75,6 +79,7 @@ ENTRY(Reset_Handler) PHDRS { text PT_LOAD; + model PT_LOAD; ram PT_LOAD; ram_init PT_LOAD; tls PT_TLS; @@ -82,6 +87,16 @@ PHDRS SECTIONS { +#if __ROM2_SIZE > 0 + /* The ExecuTorch program (ai_layer/model_pte.c, ~2.8 MB) goes to the DDR + region ROM2 instead of the 2 MB FPGA SRAM that holds the code. It comes + before .text, whose .rodata pattern would otherwise take it, and before + .init, so that lld keeps the text segment contiguous in the file. */ + .rodata.model : ALIGN(16) { + *(.rodata.model) + } >ROM2 AT>ROM2 :model +#endif + .init : { KEEP (*(.vectors)) diff --git a/board/Corstone-320/RTE/Device/SSE-320-FVP/gcc_linker_script.ld.src b/board/Corstone-320/RTE/Device/SSE-320-FVP/gcc_linker_script.ld.src index 7cd986d8..694e7571 100644 --- a/board/Corstone-320/RTE/Device/SSE-320-FVP/gcc_linker_script.ld.src +++ b/board/Corstone-320/RTE/Device/SSE-320-FVP/gcc_linker_script.ld.src @@ -16,6 +16,9 @@ * limitations under the License. */ +/* Changed for the CMSIS-Executorch example: the section .rodata.model (the + * ExecuTorch program) goes to ROM2, see SECTIONS. */ + /* ---------------------------------------------------------------------------- Stack seal size definition *----------------------------------------------------------------------------*/ @@ -89,6 +92,16 @@ ENTRY(Reset_Handler) SECTIONS { +#if __ROM2_SIZE > 0 + /* The ExecuTorch program (ai_layer/model_pte.c, ~2.8 MB) goes to the DDR + region ROM2 instead of the 2 MB FPGA SRAM that holds the code. It comes + before .text, whose .rodata pattern would otherwise take it. */ + .rodata.model : ALIGN(16) + { + *(.rodata.model) + } > ROM2 +#endif + .text : { KEEP(*(.vectors)) diff --git a/board/Corstone-320/main.c b/board/Corstone-320/main.c index 3949a17f..ddafabd5 100644 --- a/board/Corstone-320/main.c +++ b/board/Corstone-320/main.c @@ -39,5 +39,8 @@ int main (void) { osKernelInitialize(); #endif - return (app_main()); + /* End the simulation: the FVP stops on the semihosting exit call (or + --simlimit), not on the EOT character the application prints. */ + stdio_exit(app_main()); + return 0; } diff --git a/board/Corstone-320/main.h b/board/Corstone-320/main.h index 6e2048ee..3fcd7064 100644 --- a/board/Corstone-320/main.h +++ b/board/Corstone-320/main.h @@ -26,6 +26,7 @@ extern "C" { /* Prototypes */ extern int app_main (void); extern int stdio_init (void); +extern void stdio_exit (int status); #if defined(ETHOSU_ARCH) extern void ethos_setup (void); diff --git a/board/Corstone-320/regions_SSE-320.h b/board/Corstone-320/regions_SSE-320.h index fa441955..e15850de 100644 --- a/board/Corstone-320/regions_SSE-320.h +++ b/board/Corstone-320/regions_SSE-320.h @@ -118,7 +118,7 @@ // keeps its method table and planned buffers on the heap. // Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> // Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -#define __STACK_SIZE 0x00001000 +#define __STACK_SIZE 0x00008000 #define __HEAP_SIZE 0x00018000 // diff --git a/board/Corstone-320/retarget_stdio.c b/board/Corstone-320/retarget_stdio.c index 8efb957b..c93c0507 100644 --- a/board/Corstone-320/retarget_stdio.c +++ b/board/Corstone-320/retarget_stdio.c @@ -24,11 +24,24 @@ * semihosting (BKPT 0xAB), which the FVP serves directly on its stdout -- * no UART model, base address, or driver involved. Requires * mps4_board.subsystem.cpu0.semihosting-enable=1 (see fvp_config.txt). + * The same channel ends the simulation (stdio_exit) and writes files on the + * host (board_save_file). *---------------------------------------------------------------------------*/ +#include +#include + /* Semihosting operation numbers (Arm semihosting specification). */ +#define SYS_OPEN 0x01 +#define SYS_CLOSE 0x02 #define SYS_WRITEC 0x03 +#define SYS_WRITE 0x05 #define SYS_READC 0x07 +#define SYS_EXIT 0x18 + +/* SYS_EXIT reason codes */ +#define ADP_Stopped_RunTimeErrorUnknown 0x20023 +#define ADP_Stopped_ApplicationExit 0x20026 static int semihosting_call (int op, void *param) { register int r0 __asm__("r0") = op; @@ -79,3 +92,41 @@ int stdout_putchar (int ch) { int stdin_getchar (void) { return semihosting_call(SYS_READC, 0); } + +/** + End the simulation through semihosting SYS_EXIT (the FVP stops). + + \param[in] status Exit status of the application: 0 reports a normal exit, + anything else a run-time error +*/ +void stdio_exit (int status) { + /* On AArch32, R1 holds the reason code itself, not a parameter block. */ + uintptr_t reason = (status == 0) ? ADP_Stopped_ApplicationExit : ADP_Stopped_RunTimeErrorUnknown; + (void)semihosting_call(SYS_EXIT, (void *)reason); + for (;;) { __asm__ volatile ("wfi"); } +} + +/** + Save a buffer to a file on the simulation host through semihosting + (SYS_OPEN "wb", SYS_WRITE, SYS_CLOSE). Relative paths resolve against the + model's working directory, i.e. the workspace when the CMSIS extension + starts the FVP. Used by the runner to hand the generated image and the + measurements to the host for checking (APP_RESULT_DIR). + + \param[in] path File to create + \param[in] data Bytes to write + \param[in] n Number of bytes + \return 0 on success, -1 on failure +*/ +int board_save_file (const char *path, const void *data, size_t n) { + size_t len = 0U; + while (path[len] != '\0') { len++; } + uintptr_t open_args[3] = { (uintptr_t)path, 5U /* "wb" */, len }; + int fd = semihosting_call(SYS_OPEN, open_args); + if (fd < 0) { return -1; } + uintptr_t write_args[3] = { (uintptr_t)fd, (uintptr_t)data, n }; + int not_written = semihosting_call(SYS_WRITE, write_args); + uintptr_t close_args[1] = { (uintptr_t)fd }; + (void)semihosting_call(SYS_CLOSE, close_args); + return (not_written == 0) ? 0 : -1; +} diff --git a/board/DevKit-E8/Board-U85.clayer.yml b/board/DevKit-E8/Board-U85.clayer.yml index 5f0cb96f..d130aaf9 100644 --- a/board/DevKit-E8/Board-U85.clayer.yml +++ b/board/DevKit-E8/Board-U85.clayer.yml @@ -3,14 +3,15 @@ # # Alif Ensemble E8 DevKit board bring-up for the Ethos-U85 NPU, running on the # Cortex-M55 high-performance (HP) core. Derived from the pack's -# Boards/DevKit-e8/Layers/M55_HP/Board_HP-U85.clayer.yml and trimmed to what a -# headless ExecuTorch inference runner needs: device startup, the Secure -# Enclave services (clocks, pin mux), a UART-backed stdout on the PRG USB -# connector, and the Ethos-U driver. Camera, display, Ethernet, USB, VIO and -# the vStream drivers are omitted. +# Boards/DevKit-e8/Layers/M55_HP/Board_HP-U85.clayer.yml and trimmed to what an +# ExecuTorch face generator needs: device startup, the Secure Enclave services +# (clocks, pin mux), a UART-backed stdout on the PRG USB connector, the Ethos-U +# driver, and the MIPI-DSI display (CDC200 + ILI9806E panel) that shows the +# generated images. Camera, Ethernet, USB, VIO and the vStream drivers are +# omitted. layer: type: Board - description: DevKit-E8 board setup for headless Ethos-U85 inference on M55_HP + description: DevKit-E8 board setup for Ethos-U85 inference on M55_HP with the LCD for-board: Alif Semiconductor::DevKit-E8 for-device: Alif Semiconductor::AE822FA0E5597LS0:M55_HP device: :M55_HP @@ -30,14 +31,23 @@ layer: - CMSIS_target_header: \"DevKit-E8.h\" - ETHOSU85 # The runner's memory pools (src/app_main.cpp) do not fit the 1 MB DTCM - # that the Alif linker scripts use for .bss. Place them in the bulk SRAM - # at 0x02000000 (NPU-accessible; SRAM0+SRAM1 combined, 8 MB, with the AC6 - # script, SRAM0 alone, 4 MB, with the GNU one) via the section named here, and - # size them for that region; the linker scripts in this layer route the - # section there. + # that the Alif linker scripts use for .bss. Place them in the bulk SRAM0 + # (4 MB at 0x02000000, NPU-accessible) via the section named here; the + # linker scripts in this layer route the section there, above the A32 boot + # stub and next to the 1.15 MB LCD frame buffer. The temp pool holds the + # Ethos-U scratch of the decoder. - APP_POOL_SECTION: \".bss.ai_pool\" - APP_METHOD_POOL_SIZE: 0x100000 - - APP_TEMP_POOL_SIZE: 0x200000 + - APP_TEMP_POOL_SIZE: 0x180000 + # After the boot demo the runner keeps serving pico-faces' serial protocol + # on the console, for pico-faces' viewer/view_serial.py (APP_INTERACTIVE), + # and generates new faces on the SW2 joystick: left, one image; right, + # start or stop back-to-back generation (APP_BUTTONS, buttons.c). + - APP_INTERACTIVE + - APP_BUTTONS + # Every generated image is shown on the LCD (board_display_image(), + # display.c). + - APP_DISPLAY packs: - pack: AlifSemiconductor::Ensemble@^2.2.0-0 @@ -68,6 +78,14 @@ layer: - component: Device:SOC Peripherals:MHU - component: Device:SOC Peripherals:PINCONF + # Display: CDC200 controller, 2-lane MIPI DSI + DPHY, the ILI9806E panel of + # the DevKit (480 x 800), GPIO for the panel reset and backlight + - component: Device:SOC Peripherals:CDC + - component: Device:SOC Peripherals:MIPI DSI + - component: Device:SOC Peripherals:MIPI DSI CSI2 DPHY + - component: Device:SOC Peripherals:GPIO + - component: BSP:External peripherals:ILI9806E LCD panel + - component: Machine Learning:NPU Support:Ethos-U Driver&Generic U85 - component: Services:Retarget IO:STDERR @@ -84,6 +102,8 @@ layer: - file: ./DevKit-E8.h - file: ./ethos_setup.c - file: ./retarget_stdio.c + - file: ./display.c + - file: ./buttons.c - group: Ethos Interface files: diff --git a/board/DevKit-E8/README.md b/board/DevKit-E8/README.md index 70913e79..dc7377ac 100644 --- a/board/DevKit-E8/README.md +++ b/board/DevKit-E8/README.md @@ -4,32 +4,67 @@ Device: `Alif Semiconductor::AE822FA0E5597LS0:M55_HP` (Cortex-M55 high-performan core, 400 MHz) with the Ethos-U85 (256 MACs) of the Ensemble E8. Derived from the Ensemble pack's `Boards/DevKit-e8/Layers/M55_HP/Board_HP-U85.clayer.yml` -and trimmed to what a headless inference runner needs. Camera, display, -Ethernet, USB, VIO and vStream drivers are left out. The target-set in the -csolution debugs it through the on-board J-Link (`J-Link Server`, SWD at -4 MHz, `start-pname: M55_HP`). +and trimmed to what the face generator needs: the console, the NPU, the SW2 +joystick and the 4.3" MIPI-DSI display (ILI9806E, 480 x 800) on connector +J21, driven by the CDC200 display controller. Camera, Ethernet, USB, VIO and +the vStream drivers are left out. The target-set in the csolution debugs it +through the on-board J-Link (`J-Link Server`, SWD at 4 MHz, +`start-pname: M55_HP`). | File | Purpose | |------|---------| -| `Board-U85.clayer.yml` | Layer: startup, SE services, UART4 stdio, Ethos-U85 driver, memory placement | -| `main.c` | Pin/GPIO config, SE services, clocks, stdio, NPU init, then `app_main()` | +| `Board-U85.clayer.yml` | Layer: startup, SE services, UART4 stdio, Ethos-U85 driver, display, memory placement | +| `main.c` | Cache invalidation, pin/GPIO config, SE services, clocks, MIPI DPHY power-up, stdio, NPU init, then `app_main()` | +| `display.c` | `board_display_image()`: brings up CDC200 + DSI + panel on first use and shows an RGB image scaled and centred in the RGB888 frame buffer | +| `buttons.c` | `board_buttons()`: SW2 joystick presses since the last call; `board_console_poll()`: a console read that does not block | | `retarget_stdio.c` | `stdio_init()` for UART4 through the CMSIS USART driver (115200 8N1) | | `ethos_setup.c` | Ethos-U85 driver init at `NPU_HG_BASE`, IRQ 366, prints the NPU banner | | `ethosu_cb_dcache.c` | D-cache clean/invalidate hooks for NPU buffers outside the TCMs | -| `linker_ac6_mram.sct.src`, `linker_gnu_mram.ld.src` | Pack linker scripts plus a 32 kB stack and the `.bss.ai_pool` section in bulk SRAM | +| `linker_ac6_mram.sct.src`, `linker_gnu_mram.ld.src` | Pack linker scripts plus a 32 kB stack and the `.bss.ai_pool` section in bulk SRAM, above the A32 boot stub | | `RTE/` | Configuration files carried with the layer (see below) | +The layer's `define:` node sets what `src/app_main.cpp` does on this board: +the pool sizes and their section (`APP_METHOD_POOL_SIZE`, +`APP_TEMP_POOL_SIZE`, `APP_POOL_SECTION`), `APP_DISPLAY` (show every image +on the LCD, 128x128 scaled 3x to 384x384 and centred on black), +`APP_INTERACTIVE` (serve image requests on the console after the boot demo, +see STDIO) and `APP_BUTTONS` (SW2 left: one new image; right: start or stop +generating back to back). + ## Memory layout | Region | Address | Used for | |--------|---------|----------| -| MRAM (HP application region) | `0x80200000`, 2 MB | Constants, the embedded `.pte` model; with AC6 also the code, which executes in place. With GCC and Clang the startup code executes from MRAM and copies the rest of the code to ITCM (`linker_gnu_mram.ld.src`) | -| DTCM (SRAM3) | `0x20000000` (core alias; `0x50800000` global), 1 MB | `.data`/`.bss`, 96 kB heap, 32 kB stack | -| SRAM0/SRAM1 (bulk) | `0x02000000`, 8 MB combined (`SRAM0_SRAM1_COMBINED` in `app_mem_regions.h`; the GNU script uses SRAM0 alone, 4 MB) | `.bss.ai_pool`: the runner's 1 MB method pool and 2 MB temp pool (NPU scratch) | +| MRAM (HP application region) | `0x80200000`, 3.4375 MB | Constants and the embedded 2.8 MB `.pte` model; with AC6 also the code, which executes in place. With GCC and Clang the startup code executes from MRAM and copies the rest of the code to ITCM (`linker_gnu_mram.ld.src`) | +| MRAM (user region) | `0x80570000`, 32 kB | Unused; keeps the pack's MPU setup well-formed | +| DTCM (SRAM3) | `0x20000000` (core alias; `0x50800000` global), 1 MB | `.data`/`.bss` (latents, image buffer), 96 kB heap, 32 kB stack | +| SRAM0 (bulk) | `0x02010000`, 4 MB less 64 kB | `.bss.ai_pool`: the runner's 1 MB method pool and 1.5 MB temp pool (NPU scratch); `.bss.lcd_frame_buf`: the 1.15 MB RGB888 frame buffer | + +The numbers are set in `RTE/Device/AE822FA0E5597LS0_M55_HP/app_mem_regions.h`. +The pack's default splits the 5.5 MB of application MRAM into 2 MB for the +HE core, 2 MB for the HP core and a 1.5 MB user region; the model does not +fit 2 MB, and this layer runs only the HP core, so its code region extends +over the user area up to `0x80570000`. The HP vector table stays at +`0x80200000`, where the debug stub's ATOC entry boots from, and the ATOC +package at the top of MRAM is not touched. The A32 boot stub the ATOC loads +to the start of SRAM0 is the reason the pools start 64 kB in +(`APP_SRAM_POOL_OFFSET`). -The pool sizes and section come from the `define:` node of the layer -(`APP_METHOD_POOL_SIZE`, `APP_TEMP_POOL_SIZE`, `APP_POOL_SECTION`) and are -consumed by `src/app_main.cpp`. +SRAM1 follows SRAM0 at `0x02400000` (the ATOC device configuration stitches +the two banks together; the device pack's `0x08000000` is not mapped then). +The M55_HP and the debugger can use it, but the Ethos-U85 could not run with +its weights there (`ethosu_invoke` returned -1), so the layer keeps +`SRAM0_SRAM1_COMBINED 0` and places nothing the NPU reads in SRAM1. + +> [!Warning] +> Do not change the Secure Enclave run profile from this core. On the +> DevKit-E8, `SERVICES_set_run_cfg` calls that assign `memory_blocks` (the +> pack display demo's `MRAM_MASK | SRAM0_MASK`, for example) returned success +> and then left MRAM or SRAM0 unusable: MRAM reads `0xFF`, writes to +> `0x02xxxxxx` read back zero, and neither a debugger reset nor a power cycle +> recovers it. Recovery is SETOOLS over the SE UART (SW4 = SEUART): +> `maintenance`, Hard Maintenance mode, then the "Alif: Install M55_HP debug +> stubs" task and a new flash. ## RTE configuration @@ -37,7 +72,8 @@ consumed by `src/app_main.cpp`. matters: Alif's stdio retarget refuses to build unless UART4 is in polling mode (`RTE_UART4_BLOCKING_MODE_ENABLE 1` in `RTE_Device.h`), and the Conductor-generated `pins.h`/`board_defs.h` differ from the pack defaults. The -files are the pack's own DevKit-E8 layer configuration. +files are the pack's own DevKit-E8 layer configuration, with the memory +regions above changed in `app_mem_regions.h`. ## STDIO @@ -46,6 +82,14 @@ console; SW4 in position **SEUART** (the default) routes the same USB serial port to the Secure Enclave for SETOOLS. The on-board J-Link sits behind the same connector. +With `APP_INTERACTIVE` the console carries binary image frames too, in +pico-faces' serial protocol: the host sends `G [steps] [class] [w]`, +the runner answers with the timing as text and a 49 kB RGB frame, which +takes about 4.3 s at 115200 baud. pico-faces' `viewer/view_serial.py` works +unchanged; close the Serial Monitor first, the viewer needs the port. A +faster console (`UART_BAUDRATE: 921600` in the layer's `define:` node, 0.5 s +per frame) needs the same rate in the viewer's `serial.Serial()` call. + ## Before the first debug session Program the debug stubs into the device's ATOC with Alif SETOOLS once: diff --git a/board/DevKit-E8/RTE/Device/AE822FA0E5597LS0_M55_HP/app_mem_regions.h b/board/DevKit-E8/RTE/Device/AE822FA0E5597LS0_M55_HP/app_mem_regions.h index f43bbb33..7e54e76c 100644 --- a/board/DevKit-E8/RTE/Device/AE822FA0E5597LS0_M55_HP/app_mem_regions.h +++ b/board/DevKit-E8/RTE/Device/AE822FA0E5597LS0_M55_HP/app_mem_regions.h @@ -30,7 +30,7 @@ // RTSS HP Region size [bytes] <0x0-0x00580000:8> // Defines size of RTSS HP application memory region. // Default: 0x00200000 -#define APP_MRAM_HP_SIZE 0x00200000 +#define APP_MRAM_HP_SIZE 0x00370000 // 3.4375 MB: HP code region extended over the former MRAM_USER area for the ~2.8 MB model // // MRAM User Configuration @@ -38,11 +38,11 @@ // MRAM User Region // User Base address <0x80000000-0x8057FFFF:8> // Defines base address of MRAM user region -#define APP_MRAM_USER_BASE 0x80400000 +#define APP_MRAM_USER_BASE 0x80570000 // was 0x80400000; the HP code region ends here // User Region size [bytes] <0x0-0x00580000:8> // Defines size of MRAM user region -#define APP_MRAM_USER_SIZE 0x00180000 // 1.5 MB +#define APP_MRAM_USER_SIZE 0x00008000 // 32 kB, ends at 0x80578000 below the ATOC package (~0x8057C000); non-zero keeps mpu.c's regions well-formed // Application executable MRAM region (before USER area) #define APP_CODE_MRAM_SIZE (APP_MRAM_USER_BASE - APP_MRAM_HP_BASE) @@ -52,7 +52,7 @@ // ======================= // Combine SRAM0 & SRAM1 // Combines SRAM0 and SRAM1 into single memory region -#define SRAM0_SRAM1_COMBINED 1 +#define SRAM0_SRAM1_COMBINED 0 // SRAM1 follows SRAM0, but the Ethos-U85 cannot reach it: keep NPU buffers in SRAM0 // SRAM // Base address <0x02000000-0x027FFFFF:8> // Defines base address of SRAM memory region. @@ -65,6 +65,10 @@ // No zero initialize // Excludes SRAM0 region from zero initialization. #define APP_SRAM_NOINIT 1 +// Offset of the application pools <0x0-0x00400000:8> +// The ATOC loads the A32 boot stub (a32_stub_0.bin) to 0x02000000; the +// ExecuTorch pools (.bss.ai_pool) and the LCD frame buffer start above it. +#define APP_SRAM_POOL_OFFSET 0x00010000 // // SRAM0 diff --git a/board/DevKit-E8/buttons.c b/board/DevKit-E8/buttons.c new file mode 100644 index 00000000..6096ec52 --- /dev/null +++ b/board/DevKit-E8/buttons.c @@ -0,0 +1,95 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * DevKit-E8 user input for the runner: the SW2 joystick and a non-blocking + * console read. + * + * SW2 is a five-way switch on LPGPIO (port 15) pins 0-4, active low with the + * pad pull-ups (schematic 220-00319-B sheet 12, "Use Internal GPIO Pullups"). + * The direction names follow the pack's own VIO driver for this board + * (Boards/DevKit-e8/Drivers/vio_DevKit-E8.c): A = left, B = up, C = down, + * D = right, CENTER = select. The Conductor GPIO configuration of the layer + * (RTE/BSP/.../gpios.h, applied by board_gpios_config()) makes the pins + * inputs with debounce and falling-edge interrupt detection; the interrupt + * is never enabled in the NVIC, so the LPGPIO interrupt status register works + * as a press latch: a press is recorded even while the CPU is busy in an + * inference, and board_buttons() collects and clears it. + *---------------------------------------------------------------------------*/ + +#include + +#include "RTE_Components.h" +#include CMSIS_device_header + +#include "board_defs.h" + +#define BUTTON_LEFT (1u << 0) +#define BUTTON_RIGHT (1u << 1) +#define BUTTON_UP (1u << 2) +#define BUTTON_DOWN (1u << 3) +#define BUTTON_SELECT (1u << 4) + +#define LPGPIO ((volatile GPIO_Type *) LPGPIO_BASE) + +static unsigned map_pins(uint32_t pins) +{ + unsigned m = 0u; + if (pins & (1u << BOARD_JOY_SW_A_GPIO_PIN)) m |= BUTTON_LEFT; + if (pins & (1u << BOARD_JOY_SW_D_GPIO_PIN)) m |= BUTTON_RIGHT; + if (pins & (1u << BOARD_JOY_SW_B_GPIO_PIN)) m |= BUTTON_UP; + if (pins & (1u << BOARD_JOY_SW_C_GPIO_PIN)) m |= BUTTON_DOWN; + if (pins & (1u << BOARD_JOY_SW_CENTER_GPIO_PIN)) m |= BUTTON_SELECT; + return m; +} + +/* + Return the SW2 directions pressed since the previous call as a bit mask + (BUTTON_LEFT, BUTTON_RIGHT, BUTTON_UP, BUTTON_DOWN, BUTTON_SELECT) and + clear them. +*/ +unsigned board_buttons(void) +{ + uint32_t pressed = LPGPIO->GPIO_INTSTATUS & 0x1Fu; + if (pressed) { + LPGPIO->GPIO_PORTA_EOI = pressed; + } + return map_pins(pressed); +} + +/* + Return the SW2 directions currently held down (same bits), for the debugger + and for tests of the wiring. +*/ +unsigned board_buttons_held(void) +{ + return map_pins(~LPGPIO->GPIO_EXT_PORTA & 0x1Fu); +} + +/* + Return the next console character, or -1 when none is waiting. The pack's + stdin_getchar() blocks until a character arrives, which would stop the + runner from polling the joystick; this reads the console UART's receive + register directly (UART4 on the PRG USB connector, set up by stdio_init()). +*/ +int board_console_poll(void) +{ + volatile UART_Type *uart = (volatile UART_Type *) UART4_BASE; + if (uart->UART_LSR & 0x01u) { /* LSR[0]: receiver data ready */ + return (int) (uart->UART_RBR & 0xFFu); + } + return -1; +} diff --git a/board/DevKit-E8/display.c b/board/DevKit-E8/display.c new file mode 100644 index 00000000..1e5f4803 --- /dev/null +++ b/board/DevKit-E8/display.c @@ -0,0 +1,142 @@ +/*--------------------------------------------------------------------------- + * Copyright (c) 2026 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * DevKit-E8 display: shows an RGB image on the 4.3" MIPI-DSI panel (ILI9806E, + * 480 x 800 portrait) through the CDC200 display controller. The application + * calls board_display_image() with an 8-bit RGB image (HWC); the image is + * scaled up by the largest integer factor that fits the panel, centred on a + * black background and written into the RGB888 frame buffer in bulk SRAM. + * The display is brought up on the first call (CDC200 + DSI + panel), as in + * the pack's Boards/Templates/Baremetal/demo_cdc200.c. + *---------------------------------------------------------------------------*/ + +#include +#include +#include + +#include "RTE_Components.h" +#include CMSIS_device_header +#include "RTE_Device.h" + +#include "Driver_CDC200.h" + +#define LCD_WIDTH RTE_PANEL_HACTIVE_TIME /* 480 */ +#define LCD_HEIGHT RTE_PANEL_VACTIVE_LINE /* 800 */ + +#if RTE_CDC200_PIXEL_FORMAT != 1 +#error "display.c expects RTE_CDC200_PIXEL_FORMAT 1 (RGB888) in RTE_Device.h" +#endif +#define LCD_BPP 3 + +extern ARM_DRIVER_CDC200 Driver_CDC200; +static ARM_DRIVER_CDC200 *CDCdrv = &Driver_CDC200; + +/* RGB888 frame buffer, 480 x 800 x 3 = 1152000 bytes, in bulk SRAM (NPU and + display DMA accessible); the layer's linker scripts route the section. */ +static uint8_t lcd_frame[LCD_HEIGHT][LCD_WIDTH][LCD_BPP] + __attribute__((section(".bss.lcd_frame_buf"), aligned(32))); + +static int display_ready = 0; + +static void display_callback(uint32_t event) +{ + if (event & ARM_CDC_DSI_ERROR_EVENT) { + printf("Display: DSI error event\n"); + } +} + +/* Bring up the display controller, DSI link and panel; returns 0 on success. */ +static int display_init(void) +{ + int32_t ret; + + memset(lcd_frame, 0, sizeof(lcd_frame)); + SCB_CleanDCache_by_Addr((uint32_t *) lcd_frame, sizeof(lcd_frame)); + + ret = CDCdrv->Initialize(display_callback); + if (ret != ARM_DRIVER_OK) { + printf("Display: CDC200 Initialize failed (%d)\n", (int) ret); + return -1; + } + ret = CDCdrv->PowerControl(ARM_POWER_FULL); + if (ret != ARM_DRIVER_OK) { + printf("Display: CDC200 PowerControl failed (%d)\n", (int) ret); + return -1; + } + ret = CDCdrv->Control(CDC200_CONFIGURE_DISPLAY, (uint32_t) lcd_frame); + if (ret != ARM_DRIVER_OK) { + printf("Display: CDC200 configure failed (%d)\n", (int) ret); + return -1; + } + ret = CDCdrv->Start(); + if (ret != ARM_DRIVER_OK) { + printf("Display: CDC200 Start failed (%d)\n", (int) ret); + return -1; + } + printf("Display: %ux%u RGB888 panel started\n", (unsigned) LCD_WIDTH, (unsigned) LCD_HEIGHT); + return 0; +} + +/* + Show an 8-bit RGB (HWC, or gray when channels == 1) image on the panel. + + \param[in] rgb Pixel data, height x width x channels bytes + \param[in] width Image width in pixels + \param[in] height Image height in pixels + \param[in] channels 1 (gray) or 3 (RGB) + \return 0 on success, -1 when the display is not available +*/ +int board_display_image(const uint8_t *rgb, int width, int height, int channels) +{ + if (!display_ready) { + if (display_init() != 0) { + return -1; + } + display_ready = 1; + } + if (width <= 0 || height <= 0 || (channels != 1 && channels != 3)) { + return -1; + } + + /* Largest integer scale that fits, centred. */ + int scale = LCD_WIDTH / width; + if (LCD_HEIGHT / height < scale) { + scale = LCD_HEIGHT / height; + } + if (scale < 1) { + scale = 1; + } + const int out_w = width * scale, out_h = height * scale; + const int x0 = (LCD_WIDTH - out_w) / 2, y0 = (LCD_HEIGHT - out_h) / 2; + + for (int y = 0; y < out_h && y0 + y < LCD_HEIGHT; y++) { + const uint8_t *row = rgb + (size_t)(y / scale) * width * channels; + uint8_t *dst = &lcd_frame[y0 + y][x0][0]; + for (int x = 0; x < out_w && x0 + x < LCD_WIDTH; x++) { + const uint8_t *px = row + (x / scale) * channels; + /* CDC200 RGB888: little-endian 0x00RRGGBB in memory, i.e. B, G, R */ + dst[0] = channels == 3 ? px[2] : px[0]; + dst[1] = channels == 3 ? px[1] : px[0]; + dst[2] = px[0]; + dst += LCD_BPP; + } + } + /* The frame buffer is read by the display controller's DMA: push the + cached lines out (bulk SRAM is write-through, but be explicit). */ + SCB_CleanDCache_by_Addr((uint32_t *) &lcd_frame[y0][0][0], (int32_t)(out_h * LCD_WIDTH * LCD_BPP)); + return 0; +} diff --git a/board/DevKit-E8/linker_ac6_mram.sct.src b/board/DevKit-E8/linker_ac6_mram.sct.src index 91d55874..6c7984ff 100644 --- a/board/DevKit-E8/linker_ac6_mram.sct.src +++ b/board/DevKit-E8/linker_ac6_mram.sct.src @@ -5,7 +5,8 @@ /* Copied from the Ensemble pack (Device/core/rtss_hp/linker/linker_ac6_mram.sct) for the CMSIS-Executorch DevKit-E8 layer: a larger main stack, and the - .bss.ai_pool section (the ExecuTorch memory pools of the runner) in bulk SRAM. */ + .bss.ai_pool section (the ExecuTorch memory pools of the runner) in bulk SRAM, + above the A32 boot stub the ATOC loads to the start of SRAM0. */ #define __ROM_BASE APP_MRAM_HP_BASE #define __ROM_SIZE APP_CODE_MRAM_SIZE @@ -91,7 +92,7 @@ LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region } #if (SRAM0_SRAM1_COMBINED == 1) - RW_SRAM APP_SRAM_BASE APP_SRAM_SIZE { ; Update sections as needed + RW_SRAM (APP_SRAM_BASE + APP_SRAM_POOL_OFFSET) (APP_SRAM_SIZE - APP_SRAM_POOL_OFFSET) { ; above the A32 boot stub * (.bss.ai_pool) ; ExecuTorch method/temp pools (src/app_main.cpp) * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. * (.bss.lcd_frame_buf) ; LCD frame Buffer. @@ -99,7 +100,7 @@ LR_ROM __ROM_BASE NOCOMPRESS __ROM_SIZE { ; load region size_region * (.bss.camera_frame_bayer_to_rgb_buf) ; (Optional) Camera Frame Buffer for Bayer to RGB Conversion. } #else - RW_SRAM0 APP_SRAM0_BASE APP_SRAM0_SIZE { ; Update sections as needed + RW_SRAM0 (APP_SRAM0_BASE + APP_SRAM_POOL_OFFSET) (APP_SRAM0_SIZE - APP_SRAM_POOL_OFFSET) { ; above the A32 boot stub * (.bss.ai_pool) ; ExecuTorch method/temp pools (src/app_main.cpp) * (.bss.lcd_crop_and_interpolate_buf) ; LCD crop and interpolate image processing buffer. * (.bss.lcd_frame_buf) ; LCD frame Buffer. diff --git a/board/DevKit-E8/linker_gnu_mram.ld.src b/board/DevKit-E8/linker_gnu_mram.ld.src index 4f9b99de..53a2b230 100644 --- a/board/DevKit-E8/linker_gnu_mram.ld.src +++ b/board/DevKit-E8/linker_gnu_mram.ld.src @@ -28,7 +28,8 @@ */ /* Copied from the Ensemble pack (Device/core/rtss_hp/linker/linker_gnu_mram.ld.src) for the CMSIS-Executorch DevKit-E8 layer: a larger main stack, and the - .bss.ai_pool section (the runner's ExecuTorch memory pools) in bulk SRAM. */ + .bss.ai_pool section (the runner's ExecuTorch memory pools) in bulk SRAM, + above the A32 boot stub the ATOC loads to the start of SRAM0. */ /* app_mem_regions.h (the layer's RTE copy) is force-included by the CMSIS-Toolbox through the layer's `linker: regions:` entry, which also makes the toolbox preprocess this .src file with the project defines. */ @@ -51,7 +52,8 @@ MEMORY ITCM (rwx) : ORIGIN = APP_ITCM_BASE , LENGTH = APP_HP_ITCM_SIZE DTCM (rwx) : ORIGIN = APP_DTCM_BASE , LENGTH = APP_HP_DTCM_SIZE #if __HAS_BULK_SRAM - SRAM0 (rwx) : ORIGIN = APP_SRAM0_BASE, LENGTH = APP_SRAM0_SIZE + /* Above the A32 boot stub the ATOC loads to the start of SRAM0 */ + SRAM0 (rwx) : ORIGIN = APP_SRAM0_BASE + APP_SRAM_POOL_OFFSET, LENGTH = APP_SRAM0_SIZE - APP_SRAM_POOL_OFFSET SRAM1 (rwx) : ORIGIN = APP_SRAM1_BASE, LENGTH = APP_SRAM1_SIZE #endif MRAM (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE diff --git a/board/DevKit-E8/main.c b/board/DevKit-E8/main.c index d2a402e7..239e8a2f 100644 --- a/board/DevKit-E8/main.c +++ b/board/DevKit-E8/main.c @@ -15,9 +15,9 @@ * See the License for the specific language governing permissions and * limitations under the License. * - * DevKit-E8 (M55_HP) board bring-up for a headless Ethos-U85 runner. Derived - * from the pack's Boards/DevKit-e8/Layers/M55_HP/main.c without the MIPI, - * USB, Ethernet and VIO initialisation. + * DevKit-E8 (M55_HP) board bring-up for the Ethos-U85 face generator. Derived + * from the pack's Boards/DevKit-e8/Layers/M55_HP/main.c without the USB, + * Ethernet and VIO initialisation; the MIPI DPHY is powered for the display. *---------------------------------------------------------------------------*/ #include "RTE_Components.h" @@ -28,8 +28,33 @@ #include "se_services_port.h" +/* VBAT PWR_CTRL fields: power and isolation of the MIPI DPHYs and their PLL */ +#define VBAT_PWR_CTRL_TX_DPHY_PWR_MASK (1U << 0) +#define VBAT_PWR_CTRL_TX_DPHY_ISO (1U << 1) +#define VBAT_PWR_CTRL_RX_DPHY_PWR_MASK (1U << 4) +#define VBAT_PWR_CTRL_RX_DPHY_ISO (1U << 5) +#define VBAT_PWR_CTRL_DPHY_PLL_PWR_MASK (1U << 8) +#define VBAT_PWR_CTRL_DPHY_PLL_ISO (1U << 9) +#define VBAT_PWR_CTRL_DPHY_VPH_1P8_PWR_BYP_EN (1U << 12) + +/* Power up the MIPI DPHYs (the display's DSI link needs the TX DPHY and PLL) */ +static void vbat_init(void) +{ + VBAT->PWR_CTRL &= ~(VBAT_PWR_CTRL_TX_DPHY_PWR_MASK | VBAT_PWR_CTRL_RX_DPHY_PWR_MASK | + VBAT_PWR_CTRL_DPHY_PLL_PWR_MASK | VBAT_PWR_CTRL_DPHY_VPH_1P8_PWR_BYP_EN); + VBAT->PWR_CTRL &= ~(VBAT_PWR_CTRL_TX_DPHY_ISO | VBAT_PWR_CTRL_RX_DPHY_ISO | + VBAT_PWR_CTRL_DPHY_PLL_ISO); +} + int main(void) { + /* The pack's startup enables the caches without invalidating them, but + after a flash update and a warm reset from the debugger the data cache + can still hold lines of the previous image, and the runtime then reads + a corrupted program. Drop them before anything uses the model. */ + SCB_CleanInvalidateDCache(); + SCB_InvalidateICache(); + /* Apply the Conductor pin configuration (includes the UART4 console pins) */ board_pins_config(); @@ -39,9 +64,13 @@ int main(void) /* Bring up the Secure Enclave services (MHU link to the SE) */ se_services_port_init(); - /* Request the clocks the SE has to enable for this core */ + /* Request the clocks the SE has to enable for this core (HFOSC and + 100 MHz also feed the display controller and the DSI link) */ board_clocks_config(CLKEN_HFOSC_MASK | CLKEN_CLK_100M_MASK); + /* Power up the MIPI DPHY for the display */ + vbat_init(); + /* Initialize STDIO (UART4 on the PRG USB connector) */ stdio_init(); diff --git a/cmsis-executorch.cproject.yml b/cmsis-executorch.cproject.yml index 62ac0773..b5e02d31 100644 --- a/cmsis-executorch.cproject.yml +++ b/cmsis-executorch.cproject.yml @@ -1,10 +1,11 @@ # Copyright 2026 Arm Limited and/or its affiliates. # SPDX-License-Identifier: Apache-2.0 # -# The application: a headless runner that loads the embedded .pte and runs one -# inference on the Ethos-U85. The AI layer (generated by create_ai_layer.py) -# brings the ExecuTorch runtime, the operator components and the model data; -# the Board layer brings the board bring-up. +# The application: a headless face generator that loads the embedded .pte, +# runs pico-faces' sampler around its two Ethos-U85 methods and, on the +# DevKit, serves image requests on the console. The AI layer (generated by +# create_ai_layer.py) brings the ExecuTorch runtime, the operator components +# and the model data; the Board layer brings the board bring-up. project: packs: - pack: PyTorch::ExecuTorch@1.5.1 diff --git a/cmsis-executorch.csolution.yml b/cmsis-executorch.csolution.yml index a6fe2bf5..a88925f8 100644 --- a/cmsis-executorch.csolution.yml +++ b/cmsis-executorch.csolution.yml @@ -1,8 +1,10 @@ # Copyright 2026 Arm Limited and/or its affiliates. # SPDX-License-Identifier: Apache-2.0 # -# A minimal ExecuTorch-on-Ethos-U85 example for the Corstone-320 (SSE-320) FVP -# and the Alif Ensemble E8 DevKit (target-type DevKit-E8). Three steps build it: +# pico-faces (a latent diffusion transformer that generates 128x128 faces) on +# the Ethos-U85 with ExecuTorch, for the Corstone-320 (SSE-320) FVP, the +# Alif Ensemble E8 DevKit (target-type DevKit-E8) and the Alif Ensemble E8 +# AI/ML AppKit (target-type AppKit-E8). Three steps build it: # # cbuild setup cmsis-executorch.csolution.yml --active SSE-320-U85 # python create_ai_layer.py cmsis-executorch.cbuild-mlops.yml @@ -29,7 +31,7 @@ solution: # here keeps the mlops: simulator target resolvable when another # target-type is active. - pack: ARM::SSE_320_BSP@1.0.0 - # DFP + BSP of the Alif Ensemble E8 DevKit target. + # DFP + BSP of the Alif Ensemble E8 DevKit and AppKit targets. - pack: AlifSemiconductor::Ensemble@^2.2.0-0 target-types: @@ -80,6 +82,28 @@ solution: clock: 4000000 start-pname: M55_HP + # Alif Ensemble E8 AI/ML AppKit: the same E8 (M55_HP + Ethos-U85) in the + # WLCSP package, with the LCD on board. Same debug path as the DevKit: the + # on-board J-Link (SWD) on the PRG USB connector. Program the debug stubs + # with the AppKit variant of the SETOOLS task once; see README.md. + - type: AppKit-E8 + board: Alif Semiconductor::AppKit-E8-AIML + device: Alif Semiconductor::AE822FA0E5597BS0:M55_HP + variables: + - Board-Layer: $SolutionDir()$/board/AppKit-E8/Board-U85.clayer.yml + - AI-Layer: $SolutionDir()$/ai_layer/ai_layer.clayer.yml + target-set: + - set: + images: + - project-context: cmsis-executorch.Debug + debugger: + name: J-Link Server + # SWD at 4 MHz is the pack's setting for AppKit-E8-AIML + # too; see the DevKit-E8 note on JTAG. + protocol: swd + clock: 4000000 + start-pname: M55_HP + build-types: - type: Debug debug: on @@ -95,7 +119,7 @@ solution: # keys under model: are passed through to create_ai_layer.py. # https://open-cmsis-pack.github.io/cmsis-toolbox/build-overview/#mlops-information mlops: - description: TinyCNN int8 image classifier for Ethos-U85 + description: pico-faces rectified-flow face generator for Ethos-U85 npu: type: Ethos-U85 # explicit: the Ensemble pack lists an Ethos-U55 first vela: @@ -107,8 +131,4 @@ solution: memory: Shared_Sram model: clayer: $AI-Layer$ - name: TinyCNN - # Model parameters for create_ai_layer.py: the NHWC input shape and the - # number of samples the quantizer is calibrated with. - input-shape: 1x16x16x3 - calibration-samples: 2 + name: PicoFaces diff --git a/create_ai_layer.py b/create_ai_layer.py index e55cce24..b43fae87 100644 --- a/create_ai_layer.py +++ b/create_ai_layer.py @@ -15,32 +15,84 @@ of the csolution. This script reads the NPU and Vela settings from it, exports the PyTorch model in model/model.py for that NPU (quantize, delegate to Ethos-U, compile with Vela) and writes the complete AI layer into the -directory of the clayer named under `model.clayer`. The extra keys of the -`model:` node (input-shape, calibration-samples) are model parameters that -CMSIS-Toolbox passes through to this script: +directory of the clayer named under `model.clayer`: ai_layer.clayer.yml runtime, kernel utilities and registration, Ethos-U backend and the operator components the exported program actually uses - model_pte.c / .h the ExecuTorch program as a C array + model_pte_data.inc the ExecuTorch program as the rows of a C array + model_pte.c / .h the array around them; model_pte.c is the same on + every run and stops with #error while + model_pte_data.inc is missing, so a checkout that + commits it but not the data loads in csolution + model_params.h constants of the model for the application (optional) model.pte the program itself, for inspection +model/model.py describes the model through a small contract: + + get_model(), get_calibration_inputs() one method, "forward" (the simple case) + get_methods() several methods, each with its module, + example inputs, quantization and + calibration data (see Method below) + get_params() constants written to model_params.h + +The extra keys of the `model:` node (input-shape, calibration-samples), which +CMSIS-Toolbox passes through, reach get_methods(), or get_model() and +get_calibration_inputs(), as keyword arguments. + +Every method is quantized, calibrated on its data and delegated to the Ethos-U. +The script prints, per method, how many Ethos-U delegates the graph has and +which operators remain on the CPU. Set AI_LAYER_STRICT=1 to fail when a method +is not a single delegate, AI_LAYER_VERBOSE=1 for the backend's partitioning +diagnostics, AI_LAYER_DUMP= to keep the TOSA and Vela artefacts, and +AI_LAYER_VELA_FLAGS for Vela options on top of the vela: node's (e.g. +--verbose-performance). + The script runs itself in the solution's .venv (see setup_venv.py) when it is -started with an interpreter that has no torch. +started with another interpreter. """ from __future__ import annotations +import logging +import operator import os import re import shlex import subprocess import sys +import time +from collections import Counter +from dataclasses import dataclass from pathlib import Path +from typing import Any, Callable, Iterable HERE = Path(__file__).resolve().parent PACK = "PyTorch::ExecuTorch" SYMBOL = "model_pte" +DATA = f"{SYMBOL}_data.inc" +PARAMS_HEADER = "model_params.h" +# The float <-> integer boundary of a fully delegated method stays on the CPU. +BOUNDARY_OPS = { + "quantized_decomposed::quantize_per_tensor", + "quantized_decomposed::dequantize_per_tensor", +} + + +@dataclass(frozen=True) +class Method: + """One method of the exported program (model.get_methods() returns these). + + calibration yields input tuples for the quantizer's observers; without it + the example inputs are used. quantization is "a8w8" (int8 activations and + weights) or "a16w8" (int16 activations, int8 weights). + """ + + name: str + module: Any + example_inputs: tuple + calibration: Callable[[], Iterable[tuple]] | None = None + quantization: str = "a8w8" def run_in_venv() -> None: @@ -75,27 +127,27 @@ def pack_root() -> Path: def executorch_version(mlops_file: Path) -> str: - """The ExecuTorch pack version cbuild setup resolved, from .cbuild-pack.yml. + """The ExecuTorch pack version cbuild setup resolved for the csolution. - The file is a lock file that keeps earlier resolutions, so an unversioned - selector can still point at an older pack; the entry selected by the - csolution's exact pin (PyTorch::ExecuTorch@) is the one in use. + .cbuild-pack.yml is a lock file that keeps earlier resolutions: + after a pack update, an AI layer generated for the previous version still + selects that one. The entry selected by the csolution's own pack entry + (PyTorch::ExecuTorch@) is the one in use. """ import yaml + solution = mlops_file.with_name(mlops_file.name.replace(".cbuild-mlops.yml", ".csolution.yml")) + wanted = [ + entry["pack"] + for entry in yaml.safe_load(solution.read_text())["solution"].get("packs", []) + if entry["pack"].partition("@")[0] == PACK + ] pack_file = mlops_file.with_name(mlops_file.name.replace(".cbuild-mlops.yml", ".cbuild-pack.yml")) - fallback = None for entry in yaml.safe_load(pack_file.read_text())["cbuild-pack"]["resolved-packs"]: name, _, version = entry["resolved-pack"].partition("@") - selectors = entry.get("selected-by-pack", []) - if name != PACK or not selectors: - continue - if f"{PACK}@{version}" in selectors: + if name == PACK and set(wanted) & set(entry.get("selected-by-pack", [])): return version - fallback = fallback or version - if fallback: - return fallback - sys.exit(f"{pack_file}: {PACK} is not among the resolved packs") + sys.exit(f"{pack_file}: no {PACK} resolved for {wanted or 'the csolution'}; run cbuild setup first") def executorch_pack(version: str) -> Path: @@ -148,22 +200,56 @@ def compile_spec(mlops: dict, mlops_dir: Path): if not npu: sys.exit("the solution's mlops: node names no NPU; this example needs an Ethos-U") vela = mlops.get("vela", {}) - spec, extra = vela_options(vela.get("options", "")) + spec_options, extra = vela_options(vela.get("options", "")) - target = spec.get("accelerator-config") or f"{npu['type'].lower()}-{npu.get('macs', 256)}" + target = spec_options.get("accelerator-config") or f"{npu['type'].lower()}-{npu.get('macs', 256)}" kwargs = { "target": target, - "system_config": spec.get("system-config"), - "memory_mode": spec.get("memory-mode"), - "extra_flags": extra, + "system_config": spec_options.get("system-config"), + "memory_mode": spec_options.get("memory-mode"), } if vela.get("ini"): # ExecuTorch stores the path in the compile spec, and the spec ends up # in the .pte. A path relative to the working directory keeps the # program identical between checkouts; Vela resolves it from there. kwargs["config_ini"] = os.path.relpath(mlops_dir / vela["ini"]) + extra += os.environ.get("AI_LAYER_VELA_FLAGS", "").split() + if extra: + kwargs["extra_flags"] = extra print(f"[ai_layer] Vela: {kwargs}") - return EthosUCompileSpec(**kwargs) + spec = EthosUCompileSpec(**kwargs) + if dump := os.environ.get("AI_LAYER_DUMP"): + spec.dump_intermediate_artifacts_to(dump) + return spec + + +def compile_spec_from_file(mlops_file: str | Path): + """compile_spec() for a *.cbuild-mlops.yml (used by model/verify_export.py).""" + import yaml + + path = Path(mlops_file).resolve() + return compile_spec(yaml.safe_load(path.read_text())["cbuild-mlops"], path.parent) + + +def default_compile_spec(): + """An Ethos-U85-256 spec with Vela's built-in system config, for host checks + that run without a *.cbuild-mlops.yml (the quantizer only needs the NPU).""" + return compile_spec( + {"npu": {"type": "Ethos-U85", "macs": 256}, + "vela": {"options": "--system-config Ethos_U85_SYS_DRAM_Mid --memory-mode Shared_Sram"}}, + HERE, + ) + + +# ---------------------------------------------------------------------------- +# The model contract + + +def load_model_module(): + sys.path.insert(0, str(HERE / "model")) + import model + + return model def model_params(mlops: dict) -> dict: @@ -181,42 +267,155 @@ def model_params(mlops: dict) -> dict: return params -def export_model(spec, params: dict) -> bytes: - """Quantize model/model.py, delegate it to the Ethos-U and return the .pte.""" +def methods(model, params: dict | None = None) -> list[Method]: + """model.get_methods(), or "forward" from get_model() and get_calibration_inputs().""" + params = params or {} + if hasattr(model, "get_methods"): + return list(model.get_methods(**params)) + samples = model.get_calibration_inputs(**params) + module = model.get_model(**{k: v for k, v in params.items() if k == "input_shape"}) + return [Method("forward", module, (samples[0],), lambda: [(s,) for s in samples])] + + +def quant_config(kind: str): + from executorch.backends.arm.quantizer import ( + get_symmetric_a16w8_quantization_config, + get_symmetric_quantization_config, + ) + + if kind == "a8w8": + return get_symmetric_quantization_config(is_per_channel=True) + if kind == "a16w8": + return get_symmetric_a16w8_quantization_config(is_per_channel=True) + sys.exit(f"unknown quantization {kind!r}: expected a8w8 or a16w8") + + +def strip_guards_fn(gm) -> None: + """Drop the dead `_guards_fn` call_module that torch.export emits for some + models; the Arm annotation passes iterate over every module unconditionally.""" + changed = False + for node in list(gm.graph.nodes): + if node.op == "call_module" and str(node.target) == "_guards_fn": + gm.graph.erase_node(node) + changed = True + if changed: + gm.graph.eliminate_dead_code() + gm.recompile() + + +def calibrate(prepared, method: Method) -> None: + """Run the observers over the method's calibration data (or its example inputs).""" import torch - from executorch.backends.arm.ethosu import EthosUPartitioner - from executorch.backends.arm.quantizer import EthosUQuantizer, get_symmetric_quantization_config - from executorch.exir import EdgeCompileConfig, ExecutorchBackendConfig, to_edge_transform_and_lower - from torchao.quantization.pt2e.quantize_pt2e import convert_pt2e, prepare_pt2e - sys.path.insert(0, str(HERE / "model")) - from model import get_calibration_inputs, get_model + batches = method.calibration() if method.calibration else [method.example_inputs] + count, t0 = 0, time.time() + with torch.no_grad(): + for inputs in batches: + prepared(*inputs) + count += 1 + print(f"[ai_layer] {method.name}: calibrated on {count} input set(s) in {time.time() - t0:.1f} s") + - model = get_model(**{k: v for k, v in params.items() if k == "input_shape"}) - samples = get_calibration_inputs(**params) - example = (samples[0],) - graph = torch.export.export(model, example).module() +def quantize_method(method: Method, spec): + """The method's module with quantize/dequantize nodes (the fake-quant graph).""" + import torch + from executorch.backends.arm.quantizer import EthosUQuantizer + from torchao.quantization.pt2e.quantize_pt2e import convert_pt2e, prepare_pt2e + graph = torch.export.export(method.module, method.example_inputs).module() + strip_guards_fn(graph) # Quantize the whole graph so the partitioner can move every node into the - # Ethos-U delegate; only a float<->int8 boundary stays on the CPU. + # Ethos-U delegate; only the float <-> integer boundary stays on the CPU. quantizer = EthosUQuantizer(spec) - quantizer.set_global(get_symmetric_quantization_config(is_per_channel=True)) + quantizer.set_global(quant_config(method.quantization)) prepared = prepare_pt2e(graph, quantizer) - with torch.no_grad(): - for sample in samples: - prepared(sample) # calibrate - quantized = convert_pt2e(prepared) + calibrate(prepared, method) + return convert_pt2e(prepared) + + +# ---------------------------------------------------------------------------- +# Export + + +def op_name(target) -> str | None: + """`aten::mul.Tensor` for an edge or aten op object; None for graph plumbing.""" + if target is operator.getitem: + return None + name = getattr(target, "name", None) + if callable(name): + try: + return name() + except Exception: + pass + text = str(target) + if found := re.search(r"schema = ([a-z_0-9]+::[\w.]+)", text): + return found.group(1) + if found := re.match(r"^([a-z_0-9]+::[\w.]+)$", text): + return found.group(1) + return None + + +def count_ops(graph_module) -> tuple[int, Counter]: + delegates, cpu_ops = 0, Counter() + for node in graph_module.graph.nodes: + if node.op != "call_function": + continue + if "executorch_call_delegate" in str(node.target): + delegates += 1 + elif name := op_name(node.target): + cpu_ops[name] += 1 + return delegates, cpu_ops + + +def report_partitioning(edge, name: str) -> set[str]: + """Print the delegate count and CPU operators of one method; return the CPU ops.""" + delegates, cpu_ops = count_ops(edge.exported_program(name).graph_module) + ops = ", ".join(f"{op} x{n}" if n > 1 else op for op, n in cpu_ops.most_common()) or "none" + print(f"[ai_layer] {name}: {delegates} Ethos-U delegate(s); CPU operators: {ops}") + stray = {re.sub(r"\.\w+$", "", op) for op in cpu_ops} - BOUNDARY_OPS + if delegates != 1 or stray: + message = ( + f"[ai_layer] warning: {name} is not a single Ethos-U delegate " + f"({delegates} delegate(s), CPU operators beyond the quantize/dequantize " + f"boundary: {sorted(stray) or 'none'}); set AI_LAYER_VERBOSE=1 for the reasons" + ) + if os.environ.get("AI_LAYER_STRICT"): + sys.exit(message) + print(message, file=sys.stderr) + return set(cpu_ops) + + +def export_model(spec, model, params: dict | None = None) -> tuple[bytes, set[str]]: + """Quantize, delegate and serialize every method; return the .pte and the CPU operators.""" + import torch + from executorch.backends.arm.ethosu import EthosUPartitioner + from executorch.exir import EdgeCompileConfig, ExecutorchBackendConfig, to_edge_transform_and_lower + + programs = {} + for method in methods(model, params): + print(f"[ai_layer] {method.name}: quantization {method.quantization}") + programs[method.name] = torch.export.export(quantize_method(method, spec), method.example_inputs) edge = to_edge_transform_and_lower( - torch.export.export(quantized, example), - partitioner=[EthosUPartitioner(spec)], + programs, + partitioner={name: [EthosUPartitioner(spec)] for name in programs}, compile_config=EdgeCompileConfig(_check_ir_validity=False), ) + cpu_ops: set[str] = set() + for name in programs: + cpu_ops |= report_partitioning(edge, name) + program = edge.to_executorch(ExecutorchBackendConfig(extract_delegate_segments=False)) - return bytes(program.buffer) + for name in programs: # operators to_executorch adds (copies, for example) need components too + cpu_ops |= set(count_ops(program.exported_program(name).graph_module)[1]) + return bytes(program.buffer), cpu_ops + + +# ---------------------------------------------------------------------------- +# The generated layer -def components(pte: bytes, pack: Path) -> tuple[list[str], list[str]]: +def components(pte: bytes, pack: Path, cpu_ops: set[str]) -> tuple[list[str], list[str]]: """Runtime, kernel utils and registration, backend, plus one operator component per operator the .pte uses. The pack's "Extension Tensor" is not selected: its tensor_ptr_maker.cpp @@ -227,9 +426,14 @@ def components(pte: bytes, pack: Path) -> tuple[list[str], list[str]]: available = set(re.findall(r'Csub="([^"]+)"', pdsc.read_text())) family = {"aten": "Portable", "quantized_decomposed": "Quantized", "cortex_m": "Cortex-M"} + found = {(ns.decode(), op.decode()) for ns, op in re.findall(rb"(aten|quantized_decomposed|cortex_m)::(\w+)", pte)} + for name in cpu_ops: + ns, _, op = name.partition("::") + if ns in family: + found.add((ns, op.split(".")[0])) + selected, unknown = set(), [] - for ns, op in sorted(set(re.findall(rb"(aten|quantized_decomposed|cortex_m)::(\w+)", pte))): - ns, op = ns.decode(), op.decode() + for ns, op in sorted(found): candidates = [ f"{family[ns]} {op}", f"{family[ns]} {re.sub(r'_(per_tensor|per_channel|byte|copy)$', '', op)}", @@ -244,14 +448,27 @@ def components(pte: bytes, pack: Path) -> tuple[list[str], list[str]]: return ["Runtime", "Kernel Utils", "Kernel Registration", "Backend EthosU"], sorted(selected) -def c_array(pte: bytes) -> str: +def c_rows(pte: bytes) -> str: + """The program as the initializer rows of the array in SOURCE.""" rows = [", ".join(f"0x{b:02x}" for b in pte[i : i + 16]) for i in range(0, len(pte), 16)] - return ( - "// Generated by create_ai_layer.py -- do not edit.\n" - f"__attribute__((aligned(16))) const unsigned char {SYMBOL}[] = {{\n " - + ",\n ".join(rows) - + f"\n}};\nconst unsigned long {SYMBOL}_size = sizeof({SYMBOL});\n" - ) + return "// Generated by create_ai_layer.py -- do not edit.\n " + ",\n ".join(rows) + "\n" + + +# The array in the section .rodata.model, so a board layer's linker script can +# give it a memory of its own (the Corstone-320 layer puts it in DDR: the 2 MB +# FPGA SRAM that holds the code is too small); scripts that only know .rodata* +# or +RO still pick it up. The rows come from DATA, which the clayer does not +# list: csolution checks the files of a layer, and DATA may be missing. +SOURCE = f"""// Generated by create_ai_layer.py -- do not edit. +#if __has_include("{DATA}") +__attribute__((aligned(16), section(".rodata.model"))) const unsigned char {SYMBOL}[] = {{ +#include "{DATA}" +}}; +const unsigned long {SYMBOL}_size = sizeof({SYMBOL}); +#else +#error "{DATA} is missing: run the task 'Create AI layer' (python create_ai_layer.py .cbuild-mlops.yml)" +#endif +""" HEADER = f"""// Generated by create_ai_layer.py -- do not edit. @@ -267,7 +484,50 @@ def c_array(pte: bytes) -> str: """ -def clayer(mlops: dict, runtime: list[str], operators: list[str], mlops_file: Path, version: str) -> str: +def c_number(value: float) -> str: + text = f"{float(value):.9g}" + if not any(ch in text for ch in ".en"): # e, inf, nan + text += ".0" + return text + "f" + + +def c_initializer(values, indent: str = " ") -> list[str]: + """Lines of a nested brace initializer for a float array of any rank.""" + if values.ndim == 1: + items = [c_number(v) for v in values.tolist()] + return [indent + ", ".join(items[i : i + 8]) + "," for i in range(0, len(items), 8)] + lines = [] + for row in values: + lines += [indent + "{", *c_initializer(row, indent + " "), indent + "},"] + return lines + + +def params_header(params: dict[str, Any]) -> str: + """model_params.h from model.get_params(), names as given: strings, integers + and floats become #defines, sequences and tensors of numbers `static const + float` arrays of the same shape.""" + import numpy as np + + lines = [ + "// Generated by create_ai_layer.py from get_params() in model/model.py -- do not edit.", + "#pragma once", + "", + ] + for name, value in params.items(): + if isinstance(value, str): + lines.append(f'#define {name} "{value}"') + elif isinstance(value, (bool, int)): + lines.append(f"#define {name} {int(value)}") + elif isinstance(value, float): + lines.append(f"#define {name} {c_number(value)}") + else: + array = np.asarray(value.detach().cpu() if hasattr(value, "detach") else value, dtype=np.float32) + dims = "".join(f"[{d}]" for d in array.shape) + lines += ["", f"static const float {name}{dims} = {{", *c_initializer(array), "};"] + return "\n".join(lines) + "\n" + + +def clayer(mlops: dict, runtime: list[str], operators: list[str], mlops_file: Path, version: str, files: list[str]) -> str: lines = [ f"# Generated by create_ai_layer.py from {mlops_file.name} -- do not edit.", f"# Re-run `python create_ai_layer.py {mlops_file.name}` after changing", @@ -280,7 +540,8 @@ def clayer(mlops: dict, runtime: list[str], operators: list[str], mlops_file: Pa f" - pack: {PACK}@{version}", "", " define:", - " - ET_LOG_ENABLED: 0", + " - ET_LOG_ENABLED: 1", # the runner prints the runtime's error messages, + " - ET_MIN_LOG_LEVEL: Error", # but not its progress notes "", " add-path:", " - .", @@ -292,8 +553,7 @@ def clayer(mlops: dict, runtime: list[str], operators: list[str], mlops_file: Pa " groups:", f" - group: {mlops['model'].get('name', 'Model')}", " files:", - f" - file: ./{SYMBOL}.c", - f" - file: ./{SYMBOL}.h", + *[f" - file: ./{name}" for name in files], "", ] return "\n".join(lines) @@ -306,20 +566,30 @@ def main() -> None: import yaml + if os.environ.get("AI_LAYER_VERBOSE"): + logging.basicConfig(level=logging.INFO) + logging.getLogger("executorch.backends.arm").setLevel(logging.INFO) + mlops_file = Path(sys.argv[1]).resolve() mlops = yaml.safe_load(mlops_file.read_text())["cbuild-mlops"] layer_file = mlops_file.parent / mlops["model"]["clayer"] layer_dir = layer_file.parent - pte = export_model(compile_spec(mlops, mlops_file.parent), model_params(mlops)) + model = load_model_module() + pte, cpu_ops = export_model(compile_spec(mlops, mlops_file.parent), model, model_params(mlops)) version = executorch_version(mlops_file) - runtime, operators = components(pte, executorch_pack(version)) + runtime, operators = components(pte, executorch_pack(version), cpu_ops) layer_dir.mkdir(parents=True, exist_ok=True) + files = [f"{SYMBOL}.c", f"{SYMBOL}.h"] (layer_dir / "model.pte").write_bytes(pte) - (layer_dir / f"{SYMBOL}.c").write_text(c_array(pte), newline="\n") + (layer_dir / DATA).write_text(c_rows(pte), newline="\n") + (layer_dir / f"{SYMBOL}.c").write_text(SOURCE, newline="\n") (layer_dir / f"{SYMBOL}.h").write_text(HEADER, newline="\n") - layer_file.write_text(clayer(mlops, runtime, operators, mlops_file, version), newline="\n") + if hasattr(model, "get_params"): + (layer_dir / PARAMS_HEADER).write_text(params_header(model.get_params()), newline="\n") + files.append(PARAMS_HEADER) + layer_file.write_text(clayer(mlops, runtime, operators, mlops_file, version, files), newline="\n") print(f"[ai_layer] {len(pte)} byte program, operators: {operators}") print(f"[ai_layer] wrote {layer_file}") diff --git a/documentation/example.md b/documentation/example.md index 55175959..cc66ec85 100644 --- a/documentation/example.md +++ b/documentation/example.md @@ -1,7 +1,14 @@ -# ExecuTorch on Ethos-U +# ExecuTorch on Ethos-U: pico-faces This example shows how to deploy and run an [ExecuTorch](https://github.com/pytorch/executorch) model on an Arm Ethos-U NPU. +The model is [pico-faces](https://github.com/cpldcpu/pico-faces) by cpldcpu: a +latent rectified-flow diffusion transformer (DiT, 128 x 8 layers, 2.5M +parameters) plus a small convolutional decoder that generate 128x128 RGB faces +in five classes (gender x smile, plus unconditional). Upstream runs it through a +hand-written int8 engine on a Raspberry Pi Pico 2; here its float checkpoints +are exported through the ExecuTorch Arm backend and every layer runs on the +Ethos-U85, while the Cortex-M drives the sampling loop. The pack [`PyTorch::ExecuTorch`](https://www.keil.arm.com/packs/executorch-pytorch/) provides the source code components to build the ExecuTorch runtime, required operators, and Ethos-U backend. The build process uses the [CMSIS-Toolbox 2.15.0](https://open-cmsis-pack.github.io/cmsis-toolbox/) or higher. @@ -24,6 +31,15 @@ the first debug session, is the [getting-started README](../README.md). ## What the example demonstrates +- Exporting a generative model with two methods (`dit_step` and `decode`) into + one ExecuTorch program, quantized to 16-bit activations and 8-bit weights + (the decoder to 8-bit activations) and calibrated on real sampling + trajectories, with both methods fully delegated to the Ethos-U85. +- A runner (`src/app_main.cpp`) that loads both methods once and runs the + rectified-flow Euler sampler with classifier-free guidance around them; on + the DevKit it shows every face on the board's LCD, generates new ones on the + joystick, and serves pico-faces' serial protocol so the upstream viewer + displays them on the host too. - Exporting an ExecuTorch model for Ethos-U from a Python virtual environment. - The pack [`PyTorch::ExecuTorch`](https://www.keil.arm.com/packs/executorch-pytorch/) links only the required and operator components that the ML model needs. - Managing the NPU and Vela configuration in the CMSIS solution project rather than duplicating it in the Python exporter. @@ -59,15 +75,17 @@ The example can be built and run entirely in Keil Studio for VS Code. 2. Clone or download this repository, then open its folder in VS Code. 3. Before using the example for the first time, select **Terminal > Run Task > Setup Python virtual environment**. Wait for the task to create the `.venv` - environment and install the packages required to export the model. (The - **(uv)** variant of the task uses [uv](https://docs.astral.sh/uv/) instead - of pip and can download the Python version it asks for.) + environment, install the packages required to export the model and + download the pico-faces checkpoints (about 60 MB) into `model/pico_faces/`. + (The **(uv)** variant of the task uses [uv](https://docs.astral.sh/uv/) + instead of pip and can download the Python version it asks for.) 4. Select **Terminal > Run Task > Create AI layer**. This exports the model for the NPU of the active target and writes the `ai_layer/` directory. It reads `cmsis-executorch.cbuild-mlops.yml`, which the extension writes when the solution is loaded or built (`cbuild setup` on the command line). The - repository ships a generated layer, so this step is only needed after - changing the model or the target. + model data (`ai_layer/model_pte_data.inc`, 2.8 MB of program as 14 MB of + C source) is generated, not committed, so this step is needed once per checkout and + again after changing the model. 5. Use the CMSIS action buttons to build the application, then select **Run** or **Debug**. Keil Studio starts the Corstone-320 FVP automatically. On macOS, where Arm ships no FVP build, run the model in Docker instead: set `model:` @@ -81,19 +99,63 @@ For the Alif Ensemble E8 DevKit, choose the `DevKit-E8` target-type in **Manage Solution** and follow the [getting-started README](../README.md) for the one-time board preparation (SETOOLS, switches, J-Link). -A successful run prints the Ethos-U configuration, output logits, and a pass -result: +A successful run prints the Ethos-U configuration, the loaded methods, the +timings of the boot demo (seed 3, 4 steps, class 1, guidance 4), the CRC-32 +of the image, a coarse ASCII preview and a pass result. On the Corstone-320 +FVP: ```text Ethos-U version info: Arch: v2.0.0 MACs/cc: 256 Cmd stream: v1 -ExecuTorch Ethos-U85 example: 8736 byte model -Output: 10 element(s): -0.0142 0.0206 0.0601 -0.0886 0.0791 0.0522 -0.0301 -0.0775 -0.2800 -0.0095 +ExecuTorch pico-faces (m3_long_cfg, a16w8/a8w8): 2796016 byte program +Methods: + dit_step 2 input(s), 1 output(s), 16384 planned byte(s) + decode 1 input(s), 1 output(s), 245760 planned byte(s) +Generating: seed 3, 4 steps, class 1, w 4.0 + dit_step: 8 call(s), 835 ms total (104 ms each) + decode: 41 ms + total: 953 ms at 25 MHz (wall clock; not meaningful on the FVP) + dit_step: NPU 20040 kcycles, active 99%, MAC active 52%, 44 MAC/cycle, read 21279 kB on AXI0 + 0 kB on AXI1 + decode: NPU 617 kcycles, active 99%, MAC active 78%, 175 MAC/cycle, read 434 kB on AXI0 + 0 kB on AXI1 +Image: 128x128x3, CRC32 6b938c66 + |::::::::....... . ..........| + |::::::::........... ..... | + |:.:::::::...:---:::.. .... | + |:.::...:..:-==+++=-:............| + ... +Result files in out: written Test_result: PASS ``` +The CRC identifies the exported program's image: AC6, GCC and Clang builds, +the FVP and the DevKit-E8 all produce the same image from the same program. +The program itself can differ in a few quantization parameters from one host +to the next, because the calibration runs in floating point: the export +behind this listing (macOS) gives CRC 6b938c66, CI's export on Linux gives +3f8a2b1e. Either way the image matches the host's fake-quant rendering of the +same seed at about 48.5 dB PSNR, and the float model at 44 dB (`--compare`, +see step 5 below). On the DevKit-E8 +the face takes 78 ms at 400 MHz: 8.5 ms per `dit_step` (27.1 M NPU cycles for +the eight calls, NPU active 95%, MAC array active 39%) and 3 ms for `decode` +(1.3 M cycles). + +The two `NPU` lines come from the Ethos-U performance monitoring unit, read +by the runner around every method call: NPU clock cycles, the share of them +the NPU and its MAC array were busy, the average MACs per cycle derived from +the model's MAC count (`PF_MACS_*` in `model_params.h`), and the data read on +the NPU's two AXI ports. The DiT keeps the NPU busy but its MAC array only +40 to 50 percent of the time: most of the rest is the elementwise work of the +16-bit graph. Vela's per-operator estimate (`AI_LAYER_VELA_FLAGS=--verbose-performance`) +attributes the largest share to the RESCALE operators around every 16-bit +add and multiply, followed by the multiplies themselves, the softmax +max-reduction and transposes; the convolutions and matrix products are about +a quarter. The weights, 2.6 MB per `dit_step` pass, are streamed from DDR +on the FVP and from MRAM on the DevKit concurrently with that work. The +FVP's NPU cycle counts are its performance model's estimates; the DevKit's +come from the silicon. + ### Command-line build The same workflow from the VS Code Terminal (or any shell with the tools from @@ -114,9 +176,14 @@ On Windows: .\setup_venv.bat ``` -The setup script creates `.venv/` and installs the packages required to -quantize and export the model. It is safe to run again; use `--recreate` when -you want a completely new environment. The wrappers use `python3` (`python` on +The setup script creates `.venv/`, installs the packages required to +quantize and export the model, and downloads the three pico-faces checkpoint +files from a pinned upstream commit into `model/pico_faces/m3_long_cfg/`, +verifying their SHA-256. It is safe to run again; use `--recreate` when you +want a completely new environment, `--skip-download` to leave the checkpoints +alone, or `--download-only` to fetch just the checkpoints. With +`PICO_FACES_DIR` pointing at a local pico-faces clone, its `checkpoints/` +directory is used instead of the download. The wrappers use `python3` (`python` on Windows); point them at another interpreter with `PYTHON=python3.12 ./setup_venv.sh`. With [uv](https://docs.astral.sh/uv/getting-started/installation/) on `PATH`, @@ -150,10 +217,15 @@ python3 create_ai_layer.py cmsis-executorch.cbuild-mlops.yml ``` This is the MLOps step. The script reads the NPU and Vela settings from the -file, quantizes and exports `model/model.py` for that NPU, and writes the -complete AI layer into `ai_layer/`: the component selection and the model as a -C array. It runs itself in `.venv` when started with another interpreter (use -`python` on Windows). +file, quantizes and exports the two methods of `model/model.py` for that NPU +(calibrating each on data the model provides), and writes the complete AI +layer into `ai_layer/`: the component selection, the model as a C array and +`model_params.h` with the sampling schedule and the conditioning table. It +prints, per method, the number of Ethos-U delegates and the operators left on +the CPU; for this model both methods are one delegate each, with only the +quantize/dequantize boundary on the CPU. It runs itself in `.venv` when +started with another interpreter (use `python` on Windows) and takes a few +minutes (calibration plus Vela). #### 3. Build the application @@ -176,7 +248,50 @@ FVP_Corstone_SSE-320 \ ``` This is the model command the Run and Debug buttons use too. On macOS, call -`.vscode/fvp.sh` with the same arguments; it runs the model in Docker. +`.vscode/fvp.sh` with the same arguments; it runs the model in Docker. The +application generates one face (seed 3, 4 steps, class 1, +guidance 4), prints the timings, the CRC-32 of the image and a coarse ASCII +preview, writes the image and the measurements to `out/fvp_image.bin` and +`out/fvp_result.txt` through semihosting, and ends the simulation. A run +takes a few minutes. + +#### 5. Check the result on the host + +```bash +python3 model/verify_export.py --stage fakequant --seed 3 --class 1 --w 4 --k 4 --out out/pf_fakequant.png +python3 model/verify_export.py --compare out/fvp_image.bin out/pf_fakequant.png +``` + +The host stages use the firmware's noise generator, so the same seed, class, +guidance and step count give the same face as on the FVP and the board. +`--stage float` samples with the float model, `--stage fakequant` with the +quantized graphs the export produces (what the NPU is expected to compute); +`--compare` prints the PSNR between two images (PNGs, or the raw frame the +FVP writes), and `--min-psnr` turns it into a check, as in CI. `--stage tosa` +executes both methods through the TOSA reference model, the integer +semantics the Ethos-U implements, and reports the deviation from the +fake-quant graphs: the check that catches 16-bit lowering problems before a +build. `--check-upstream ` verifies the re-implementation in +`model/model.py` against the original pico-faces modules. + +#### 6. Generate faces on the DevKit-E8 + +On the board the runner keeps going after the boot demo. Every face appears +on the LCD; the SW2 joystick generates new ones (left: one image; right: +start or stop generating back to back). The runner also serves image +requests on the UART console in the serial protocol of pico-faces' firmware, +so pico-faces' viewer works unchanged (in a clone of the upstream repository, +`pip install pyserial pillow`): + +```bash +python viewer/view_serial.py --port /dev/tty.usbmodemXXXX --seed 3 --steps 4 --class 1 --cfg 4 --show +``` + +Close the Serial Monitor first: the viewer needs the port. `--class` is 0 +(female, neutral), 1 (female, smiling), 2 (male, neutral), 3 (male, smiling) +or 4 (unconditional); `--cfg` is the guidance strength (0 = plain); +`--steps` is 8, 4, 2 or 1. A frame takes about 4 s to transfer at 115200 +baud, much longer than its generation. ## How model generation works @@ -192,9 +307,7 @@ mlops: memory: Shared_Sram model: clayer: $AI-Layer$ - name: TinyCNN - input-shape: 1x16x16x3 - calibration-samples: 2 + name: PicoFaces ``` `cbuild setup --active DevKit-E8` resolves it into @@ -205,14 +318,47 @@ copies the pack's Vela configuration to `.cmsis/ensemble_vela.ini` and adds `--accelerator-config ethos-u85-256`, for both targets; the system configuration named above comes from that file. `create_ai_layer.py` reads those options and passes all of them to ExecuTorch's `EthosUCompileSpec`, so -the target configuration is never duplicated in Python. The two extra keys -under `model:` are parameters of the model itself; the toolbox passes them -through and the script hands them to `model/model.py`. The script then writes: +the target configuration is never duplicated in Python. Extra keys under +`model:` (`input-shape`, `calibration-samples`) are parameters of the model +itself; the toolbox passes them through and the script hands them to +`model/model.py` (pico-faces takes none). The script then writes: - `ai_layer/ai_layer.clayer.yml`: the CMSIS components required by the model. -- `ai_layer/model_pte.c` and `model_pte.h`: the ExecuTorch program embedded as a C array. +- `ai_layer/model_pte_data.inc`: the ExecuTorch program as the rows of a C + array, which `model_pte.c` embeds and `model_pte.h` declares. +- `ai_layer/model_params.h`: the constants the runner needs (latent and image + shapes, the schedule, the conditioning vectors per class and step). - `ai_layer/model.pte`: the program itself, for inspection. +`model/model.py` re-implements the pico-faces modules with the operators the +Ethos-U delegate supports (RMSNorm from primitives, attention on rank-3 +tensors, patchify as a strided convolution) and loads the upstream weights by +name. Two details of the graph matter for the 16-bit path and were found with +the TOSA reference model (the host fake-quant reference does not model them): +reductions (the mean in RMSNorm, the softmax row sums) are matrix products +with a constant ones vector instead of `aten.mean`/`aten.sum`, whose +`REDUCE_SUM` has a documented 16-bit issue on the Ethos-U85; and the output +projection stays a Linear with its bias, followed by a transposed convolution +with fixed 0/1 weights for the unpatchify, because a bias add after the +transposed convolution fuses into a RESCALE whose shift is too small for +16-bit accumulators (the reference model reports "value should stay within +[-262144, 262143]", and the NPU output saturates). The conditioning tower +(timestep embedding, class embedding) is evaluated at export time for the 8 +schedule points and 5 classes, so the program takes the conditioning vector as +an input and the firmware needs no float operators on the CPU. + +| Method | Runs on | Work | +|--------|---------|------| +| `dit_step(z, c) -> v` | Ethos-U85 | 111 MMAC per call; 2 calls per step with guidance | +| `decode(z) -> img` | Ethos-U85 | 109 MMAC | +| Euler update, guidance blend, noise, RGB conversion | Cortex-M | a few thousand float operations | + +The DiT runs at `a16w8` (16-bit activations, 8-bit weights): it reproduces +the float model closely, whereas int8 activations (`PICO_FACES_QUANT=a8w8`) +give visibly degraded faces because the DiT's residual stream needs more than +8 bits. The decoder runs at `a8w8` (`PICO_FACES_DECODE_QUANT`): its +convolutions do not need the 16-bit path and run about three times as fast. + See [the MLOps flow](mlops-flow.md) for a detailed walkthrough. ## Component selection @@ -226,20 +372,18 @@ changes the operator set needs nothing more than re-running steps 2 and 3. ## Adapting the example -To use a different model, replace or modify `model/model.py` and update the -model name or input handling as required: `get_model(input_shape)` builds the -model for the `input-shape` of the `mlops:` node, and -`get_calibration_inputs(input_shape, calibration_samples)` returns the samples -the quantizer is calibrated with; give it representative data for a trained -model. The runner in `src/app_main.cpp` builds its input tensor with the same -fixed shape and prints the output as ten floats, so a model with another input -shape or output needs matching changes there. Then re-run `create_ai_layer.py` -and build. - -Give an image model its input as NHWC, the layout of a camera frame, as -`model/model.py` does: the model permutes it to the NCHW its convolutions take, -and Vela folds that into the first convolution. With an NCHW input the NPU -first reorders the image in an operation of its own. +To use a different model, replace or modify `model/model.py`. A model with +one method needs only `get_model()` and `get_calibration_inputs()` (the +samples the quantizer is calibrated with; give it representative data for a +trained model). Several methods, their calibration data and quantization, +and constants for the firmware come through `get_methods()` and +`get_params()` (see [the MLOps flow](mlops-flow.md)). The runner in +`src/app_main.cpp` is written for pico-faces' two methods, so another model +needs a runner of its own; `EmbeddedModule` (`src/arm_embedded_module.hpp`) +loads and executes methods by name. Then re-run `create_ai_layer.py` and +build. `PICO_FACES_VARIANT=m3_decD_deep_full` exports pico-faces' larger +model (12 layers, 3.7 MB of weights), which does not fit the DevKit's MRAM +region without further memory work. To target another Ethos-U configuration, update the target and `mlops:` settings in the CMSIS solution and re-run all three steps. The generated Vela @@ -258,16 +402,18 @@ together. More information is available in | ------ | --------- | | `cmsis-executorch.csolution.yml` | Solution, target, and MLOps configuration | | `cmsis-executorch.cproject.yml` | Application project: sources plus the Board and AI layers | -| `model/model.py` | Example TinyCNN model | +| `model/model.py` | pico-faces re-expressed as the ExecuTorch methods `dit_step` and `decode` | +| `model/verify_export.py` | Host checks: float and fake-quant sampling to PNG, TOSA reference model, upstream comparison, PSNR | +| `model/pico_faces/` | Downloaded checkpoints (not committed) | | `create_ai_layer.py` | Exports the model for the target and writes the AI layer | -| `ai_layer/` | Generated: component selection and the embedded model data | -| `setup_venv.py` (`.sh` / `.bat`) | Creates the Python environment for the export | +| `ai_layer/` | Generated: component selection, `model_params.h` and the embedded model data (`model_pte_data.inc` not committed) | +| `setup_venv.py` (`.sh` / `.bat`) | Creates the Python environment for the export and downloads the checkpoints | | `.vscode.d/tasks.json` | The VS Code tasks (venv setup, Create AI layer, Alif debug stubs) merged by the CMSIS Solution extension | | `.vscode/fvp.sh`, `.vscode/fvp.Dockerfile`, `.vscode/launch.json.mac` | macOS only: runs the FVP in Docker, and the debug configuration that waits for it | -| `board/Corstone-320/` | Corstone-320 platform support and FVP configuration | -| `board/DevKit-E8/` | Alif Ensemble E8 DevKit board layer (M55_HP core, Ethos-U85, UART console) | +| `board/Corstone-320/` | Corstone-320 platform support and FVP configuration; the linker scripts in its `RTE/` put the model in DDR | +| `board/DevKit-E8/` | Alif Ensemble E8 DevKit board layer (M55_HP core, Ethos-U85, UART console, LCD, joystick) | | `.alif/` | SETOOLS configuration and debug stubs for the DevKit-E8 (from the Ensemble pack) | -| `src/app_main.cpp` | Loads the model, runs inference, and prints the result; pool sizes overridable with `APP_METHOD_POOL_SIZE`, `APP_TEMP_POOL_SIZE`, `APP_POOL_SECTION` | +| `src/app_main.cpp` | Loads the two methods and runs the sampler; board features through `APP_DISPLAY`, `APP_INTERACTIVE`, `APP_BUTTONS`; pool sizes overridable with `APP_METHOD_POOL_SIZE`, `APP_TEMP_POOL_SIZE`, `APP_POOL_SECTION` | | `src/arm_embedded_module.*` | `EmbeddedModule`: ExecuTorch's `Module` class without the POSIX file loading (BSD-3-Clause, `src/LICENSE-ExecuTorch`) | | `board/DevKit-E8/README.md` | The DevKit-E8 layer, its memory map and RTE configuration | | `documentation/mlops-flow.md` | The MLOps flow in detail | @@ -287,10 +433,13 @@ together. More information is available in The example code is licensed under Apache-2.0; see `LICENSE`. ExecuTorch and `src/arm_embedded_module.*`, which is derived from it, use a BSD-3-Clause -license; see `src/LICENSE-ExecuTorch`. +license; see `src/LICENSE-ExecuTorch`. pico-faces, whose modules +`model/model.py` re-implements and whose checkpoints `setup_venv.py` +downloads, is MIT-licensed; see `model/LICENSE-pico-faces`. ## References +- [pico-faces](https://github.com/cpldcpu/pico-faces) - [PyTorch ExecuTorch CMSIS Pack](https://www.keil.arm.com/packs/executorch-pytorch/) - [ExecuTorch](https://github.com/pytorch/executorch) - [ExecuTorch Arm Ethos-U backend](https://docs.pytorch.org/executorch/main/backends-arm-ethos-u.html) diff --git a/documentation/mlops-flow.md b/documentation/mlops-flow.md index 1e0ad06b..a96b1c7d 100644 --- a/documentation/mlops-flow.md +++ b/documentation/mlops-flow.md @@ -10,11 +10,13 @@ propagate that information. flowchart TD A["cmsis-executorch.csolution.yml
mlops: node"] -->|"1. cbuild setup --active <target>"| B["cmsis-executorch.cbuild-mlops.yml
npu, vela.options, model.clayer"] B -->|"2. create_ai_layer.py"| C["EthosUCompileSpec
quantize, delegate, Vela"] - D["model/model.py
TinyCNN"] --> C - C --> E["ai_layer/model_pte.c
the program as a C array"] + D["model/model.py
pico-faces: dit_step, decode"] --> C + C --> E["ai_layer/model_pte_data.inc
the program as a C array"] C --> F["ai_layer/ai_layer.clayer.yml
component selection"] + C --> P["ai_layer/model_params.h
schedule, conditioning table"] E --> G["3. cbuild --active <target>"] F --> G + P --> G G --> H["cmsis-executorch.axf"] ``` @@ -25,7 +27,7 @@ The csolution is the only place where the NPU is described: ```yaml solution: mlops: - description: TinyCNN int8 image classifier for Ethos-U85 + description: pico-faces rectified-flow face generator for Ethos-U85 npu: type: Ethos-U85 vela: @@ -33,14 +35,13 @@ solution: memory: Shared_Sram # memory-mode from the Vela config model: clayer: $AI-Layer$ - name: TinyCNN - input-shape: 1x16x16x3 # passed through to create_ai_layer.py - calibration-samples: 2 + name: PicoFaces ``` CMSIS-Toolbox detects the `hardware:` target (DevKit-E8, J-Link Server) and the `simulator:` target (SSE-320-U85, Arm-FVP) from the target-sets, and -passes the extra keys under `model:` through unchanged. +passes extra keys under `model:` (parameters of the model, none for +pico-faces) through unchanged. `cbuild setup cmsis-executorch.csolution.yml --active DevKit-E8` resolves it and writes `cmsis-executorch.cbuild-mlops.yml`: @@ -48,7 +49,7 @@ resolves it and writes `cmsis-executorch.cbuild-mlops.yml`: ```yaml cbuild-mlops: generated-by: csolution version 2.15.1+p3-gf46d68bf - description: TinyCNN int8 image classifier for Ethos-U85 + description: pico-faces rectified-flow face generator for Ethos-U85 processor: type: Cortex-M55 npu: @@ -59,9 +60,7 @@ cbuild-mlops: options: --accelerator-config ethos-u85-256 --system-config Ethos_U85_SRAM_MRAM --memory-mode Shared_Sram model: clayer: ai_layer/ai_layer.clayer.yml - name: TinyCNN - input-shape: 1x16x16x3 - calibration-samples: 2 + name: PicoFaces hardware: active: DevKit-E8 cbuild-run: out/cmsis-executorch+DevKit-E8.cbuild-run.yml @@ -88,8 +87,11 @@ This is the hand-over point to the MLOps side: everything a model-export pipeline needs to know about the target is in this one file, and nothing in it is specific to this example's Python code. -`cbuild setup` writes the file even when the AI layer does not exist yet, so -the flow also works on a checkout without a generated layer. +`cbuild setup` writes the file even when the AI layer does not exist yet. +csolution refuses a layer whose files are missing, so the committed clayer +lists only committed files: `model_pte.c` includes the 14 MB of array rows +from `model_pte_data.inc`, which is not committed and not listed. A build +before step 2 stops at an `#error` that names the missing file. ## 2. `create_ai_layer.py` turns `*.cbuild-mlops.yml` into the AI layer @@ -101,24 +103,44 @@ for an MLOps system. It reads the file and: there, and every other option in `vela.options` (the `misc:` of the csolution's `vela:` node) reaches Vela as an extra flag, so the Python code contains no NPU configuration; -2. exports `model/model.py`: quantizes it, delegates the whole graph to the - Ethos-U and compiles it with Vela; +2. exports `model/model.py`. The model describes itself through a small + contract: `get_methods()` lists the methods of the program (here + `dit_step` and `decode`, each an `nn.Module` with example inputs, a + calibration data generator and its quantization, `a16w8` or `a8w8`), and + `get_params()` returns constants for the application. A model with only + `get_model()` and `get_calibration_inputs()` is exported as the single + method `forward`. Every method is calibrated on its data (pico-faces: + latents from real sampling trajectories), delegated to the Ethos-U as a + whole and compiled with Vela; the script prints the delegate count and the + operators left on the CPU per method (`AI_LAYER_STRICT=1` turns a partially + delegated method into an error); 3. reads the operators the resulting program still calls on the CPU and looks up the matching components in the `PyTorch::ExecuTorch` pack (the version - `cbuild setup` resolved, from `*.cbuild-pack.yml`); + `cbuild setup` resolved for the csolution's pack entry, from + `*.cbuild-pack.yml`); 4. writes the layer into the directory of `model.clayer`: | File | Content | |------|---------| | `ai_layer/ai_layer.clayer.yml` | runtime, kernel utilities and registration, Ethos-U backend and the operator components the program uses | -| `ai_layer/model_pte.c` / `.h` | the program as a 16-byte-aligned C array, `model_pte` / `model_pte_size` | -| `ai_layer/model.pte` | the program itself, for inspection (not committed) | - -The clayer and the C array are committed, so a checkout builds without -Python. For a fully delegated model the component list is short: `Runtime`, -`Kernel Utils`, `Kernel Registration`, `Backend EthosU`, and the int8 boundary -`Quantized quantize` / `Quantized dequantize` operators. Everything else in -the pack is never compiled, let alone linked. +| `ai_layer/model_pte.c` / `.h` | the program as a 16-byte-aligned C array in the section `.rodata.model`, `model_pte` / `model_pte_size`; the same on every run | +| `ai_layer/model_pte_data.inc` | the rows of that array, which `model_pte.c` includes | +| `ai_layer/model_params.h` | the constants from `get_params()`: latent and image shapes, the sampling schedule, the guidance strengths and the conditioning table `pf_cond[class][step][128]` | +| `ai_layer/model.pte` | the program itself, for inspection | + +The clayer, the headers and `model_pte.c` are committed; `model_pte_data.inc` +(14 MB of C source for the 2.8 MB program) and `model.pte` are not, so a +fresh checkout runs step 2 +once before it builds. For a fully delegated model the component list is +short: `Runtime`, `Kernel Utils`, `Kernel Registration`, `Backend EthosU`, +and the boundary `Quantized quantize` / `Quantized dequantize` operators +(they handle 8- and 16-bit activations). Everything else in the pack is never +compiled, let alone linked. + +The program holds two methods; the application loads both once and runs them +in a loop (`src/app_main.cpp`): the Euler sampler and the classifier-free +guidance blend are a few thousand float operations on the Cortex-M, +everything else is NPU work. ## 3. `cbuild` builds the application @@ -133,7 +155,13 @@ step 3. ## Changing the model or the target -- **Another model:** edit `model/model.py`, run steps 2 and 3. +- **Another model:** edit `model/model.py` (`get_methods()`, or `get_model()` + and `get_calibration_inputs()` for a single method), adapt the runner in + `src/app_main.cpp`, run steps 2 and 3. +- **Another precision:** `PICO_FACES_QUANT=a8w8 python create_ai_layer.py ...` + exports the DiT with 8-bit activations (smaller SRAM footprint, visibly + worse faces); `model/verify_export.py --stage fakequant` shows the effect on + the host before a build. - **Another NPU configuration:** edit the `mlops:` node (and add the matching `target-types:` entry and board layer), run steps 1 to 3: diff --git a/documentation/pack-provenance.md b/documentation/pack-provenance.md index 5cf2144a..a5164711 100644 --- a/documentation/pack-provenance.md +++ b/documentation/pack-provenance.md @@ -35,9 +35,11 @@ version — see [Moving to a new ExecuTorch version](#moving-to-a-new-executorch `create_ai_layer.py` reads the installed pack's `.pdsc` out of the pack root (`$CMSIS_PACK_ROOT`, or cpackget's default) to find out which operator -components exist. It reads the version `cbuild setup` resolved, taken from -`cmsis-executorch.cbuild-pack.yml`, so a pack root holding several -ExecuTorch versions cannot make it read the wrong one. +components exist. It reads the version `cbuild setup` resolved for the +csolution's `PyTorch::ExecuTorch` entry, taken from +`cmsis-executorch.cbuild-pack.yml`, so neither a pack root holding several +ExecuTorch versions nor an older resolution that the lock file keeps for the +previous AI layer can make it read the wrong one. ## What is in the pack @@ -174,6 +176,6 @@ in order: A changed operator set simply shows up in the regenerated `ai_layer/ai_layer.clayer.yml`. -Finally, update the version wherever it appears in prose: the README -(Prerequisites and the pack-version note), the csolution header comment and -this page. +Finally, update the version wherever it appears in prose: +`documentation/example.md` (Prerequisites and the pack-version note), +`requirements.txt` and this page. diff --git a/model/LICENSE-pico-faces b/model/LICENSE-pico-faces new file mode 100644 index 00000000..97938b63 --- /dev/null +++ b/model/LICENSE-pico-faces @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2026 Tim B. + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/model/model.py b/model/model.py index 8af0e024..ca2ef2e8 100644 --- a/model/model.py +++ b/model/model.py @@ -1,61 +1,576 @@ # Copyright 2026 Arm Limited and/or its affiliates. # SPDX-License-Identifier: Apache-2.0 -"""The example model: a tiny CNN classifier, quantized to int8 for Ethos-U85 by create_ai_layer.py. +# +# The network modules re-implement pico-faces by Tim B. (cpldcpu), MIT license, +# see model/LICENSE-pico-faces. +"""The example model: pico-faces, a latent rectified-flow face generator, for Ethos-U85. -Small enough to export in seconds and fully partition onto the NPU, but real -enough to exercise conv / relu / pool / linear through Vela. Input is a single -16x16 RGB image (NHWC); output is a 10-class logit vector. +pico-faces (https://github.com/cpldcpu/pico-faces) generates 128x128 RGB faces +with a small diffusion transformer (DiT) on an 8x16x16 latent and a +convolutional VAE decoder. Upstream runs it through a hand-written int8 engine +on an RP2350; here the float checkpoints are re-expressed as ExecuTorch methods +and delegated to the Ethos-U85: + + dit_step(z (1,8,16,16), c (1,128)) -> v (1,8,16,16) one velocity evaluation + decode(z (1,8,16,16)) -> img (1,3,128,128) in [-1, 1] + +The conditioning vector c = t_mlp(timestep_embedding(t)) + y_emb(y) depends only +on the schedule step and the class, so it is evaluated at export into a table +(pf_cond in model_params.h) and the firmware feeds it as an input; the Euler +loop and the classifier-free guidance blend run in C on the Cortex-M. + +Contract with create_ai_layer.py: + get_methods() the methods of the exported program + get_params() constants for ai_layer/model_params.h + +Environment knobs: PICO_FACES_VARIANT (m3_long_cfg | m3_decD_deep_full), +PICO_FACES_QUANT (a16w8 | a8w8 for dit_step; a8w8 shows visible artefacts), +PICO_FACES_DECODE_QUANT (a8w8 | a16w8 for decode), PICO_FACES_CALIB_SEEDS +(calibration trajectories, default 16), PICO_FACES_DIR (a local pico-faces +clone instead of the checkpoints setup_venv.py downloads into model/pico_faces/). """ +from __future__ import annotations + +import functools +import math +import os +import sys +from dataclasses import dataclass +from pathlib import Path +from typing import Callable, Iterable + +import numpy as np import torch +import torch.nn.functional as F from torch import nn -# NHWC, the layout of a camera frame, which the Ethos-U reads as it is. An NCHW -# input costs one more NPU operation that reorders it before the first -# convolution. -INPUT_SHAPE = (1, 16, 16, 3) +HERE = Path(__file__).resolve().parent + +VARIANT = os.environ.get("PICO_FACES_VARIANT", "m3_long_cfg") +# The DiT's residual stream needs more than 8 bits; the decoder's convolutions +# do not, and run about twice as fast with 8-bit activations. +QUANTIZATION = os.environ.get("PICO_FACES_QUANT", "a16w8") +DECODE_QUANTIZATION = os.environ.get("PICO_FACES_DECODE_QUANT", "a8w8") +CALIB_SEEDS = int(os.environ.get("PICO_FACES_CALIB_SEEDS", "16")) + +# The sampling schedule of the exported models (models//export.yaml +# upstream): K_MAX Euler steps from t=1 (noise) towards t=0; k_steps in +# {8, 4, 2, 1} strides through it. +SCHEDULE = [1.0, 0.875, 0.75, 0.625, 0.5, 0.375, 0.25, 0.125] +CFG_W = [4.0, 6.0, 8.0] # guidance strengths upstream bakes tables for +N_CLASSES = 4 # 0 f/neutral, 1 f/smile, 2 m/neutral, 3 m/smile +NULL_CLASS = N_CLASSES # unconditional (also the negative of the CFG blend) +EPS = torch.finfo(torch.float32).eps # nn.RMSNorm(eps=None) upstream + + +# ---------------------------------------------------------------------------- +# Checkpoints + + +@dataclass(frozen=True) +class Checkpoint: + dit: dict[str, torch.Tensor] + dit_cfg: dict + dec: dict[str, torch.Tensor] + dec_plan: list[tuple[int, int]] + img_ch: int + latent_mean: torch.Tensor + latent_std: torch.Tensor + +def checkpoint_dir() -> Path: + if clone := os.environ.get("PICO_FACES_DIR"): + return Path(clone) / "checkpoints" / VARIANT + return HERE / "pico_faces" / VARIANT + + +@functools.lru_cache(maxsize=None) +def load_checkpoint() -> Checkpoint: + sys.path.insert(0, str(HERE.parent)) + from setup_venv import PICO_FACES_FILES, sha256 # stdlib only + + folder = checkpoint_dir() + expected = PICO_FACES_FILES[VARIANT] + for name in expected: + if not (folder / name).is_file(): + sys.exit( + f"{folder / name} is missing. Run ./setup_venv.sh (or `python3 " + "setup_venv.py --download-only`) to download the pico-faces " + "checkpoints, or point PICO_FACES_DIR at a pico-faces clone." + ) + + dit_ckpt = torch.load(folder / "dit_qat.pt", map_location="cpu", weights_only=True) + dit = {k.replace("_orig_mod.", ""): v.float() for k, v in dit_ckpt["ema"].items()} + dit_cfg = dit_ckpt["cfg"] + if dit_cfg.get("arch") != "dit" or dit_cfg.get("act") != "relu2": + sys.exit(f"unsupported pico-faces DiT config: arch={dit_cfg.get('arch')} act={dit_cfg.get('act')}") + + # vae_final.pt pickles a numpy scalar and needs weights_only=False: only + # load it after the hash check, so an unexpected file is never unpickled. + vae_file = folder / "vae_final.pt" + if (actual := sha256(vae_file)) != expected["vae_final.pt"]: + sys.exit(f"{vae_file}: SHA-256 {actual} does not match the pinned checkpoint") + vae_ckpt = torch.load(vae_file, map_location="cpu", weights_only=False) + dec = {k[len("decoder."):]: v.float() for k, v in vae_ckpt["model"].items() if k.startswith("decoder.")} + vae_cfg = vae_ckpt["cfg"] + + stats = np.load(folder / "latent_stats.npz") + return Checkpoint( + dit=dit, + dit_cfg=dit_cfg, + dec=dec, + dec_plan=[tuple(int(x) for x in p) for p in vae_cfg["dec_plan"]], + img_ch=int(vae_cfg.get("img_ch", 1)), + latent_mean=torch.from_numpy(stats["mean"].astype(np.float32)), + latent_std=torch.from_numpy(stats["std"].astype(np.float32)), + ) + + +# ---------------------------------------------------------------------------- +# Building blocks, written with the operators the Ethos-U delegate supports + + +class RMSNorm(nn.Module): + """RMS normalisation over the last dimension (no mean subtraction). + + aten.rms_norm has no Ethos-U lowering, so it is spelled out in primitives: + mul, a mean, add, rsqrt (a table on the NPU) and mul. The mean is a matrix + product with a constant 1/dim vector rather than aten.mean: aten.mean lowers + to a TOSA REDUCE_SUM, for which the ExecuTorch Arm backend documents a + 16-bit Ethos-U85 issue (silent zeros in its softmax tests); the product is + a MATMUL with an int48 accumulator that is exact at both precisions. + """ -class TinyCNN(nn.Module): - def __init__(self, input_shape: tuple[int, ...] = INPUT_SHAPE, num_classes: int = 10) -> None: + def __init__(self, dim: int, weight: bool) -> None: super().__init__() - _, height, width, channels = input_shape - self.features = nn.Sequential( - nn.Conv2d(channels, 8, kernel_size=3, padding=1), - nn.ReLU(), - nn.MaxPool2d(2), # 16x16 -> 8x8 - nn.Conv2d(8, 16, kernel_size=3, padding=1), - nn.ReLU(), - nn.MaxPool2d(2), # 8x8 -> 4x4 - ) - self.classifier = nn.Linear(16 * (height // 4) * (width // 4), num_classes) + self.weight = nn.Parameter(torch.ones(dim)) if weight else None + self.register_buffer("mean_weight", torch.full((1, dim), 1.0 / dim)) def forward(self, x: torch.Tensor) -> torch.Tensor: - # The convolutions take NCHW. Vela folds the permutation into the first one. - x = self.features(x.permute(0, 3, 1, 2)) - x = torch.flatten(x, 1) - return self.classifier(x) + ms = F.linear(x * x, self.mean_weight) # (..., 1): mean of the squares + y = x * torch.rsqrt(ms + EPS) + return y * self.weight if self.weight is not None else y + + +class Attention(nn.Module): + """Multi-head self-attention over the 64 tokens on rank-3 tensors. + + Vela accepts non-elementwise operators up to rank 4 with a batch of 1, so + the heads become the batch dimension of rank-3 bmm operands. The softmax + scale 1/sqrt(hd) is folded into q_norm.weight at load time. The softmax is + written out with its row sums as a matrix product with a ones vector (see + RMSNorm for why aten.mean / REDUCE_SUM is avoided). The max subtraction (a + REDUCE_MAX and a SUB, about 10% of the NPU cycles) is not needed in float, + because the qk-RMSNorm bounds the scores, but without it rows whose maximum + lies far below the calibrated range of the exp table lose all precision and + the images fall apart. `model/verify_export.py --stage tosa` checks the + lowered graphs against the TOSA reference model. + """ + + def __init__(self, dim: int, heads: int, tokens: int) -> None: + super().__init__() + self.dim, self.heads, self.hd, self.tokens = dim, heads, dim // heads, tokens + self.qkv = nn.Linear(dim, 3 * dim) + self.q_norm = RMSNorm(self.hd, weight=True) + self.k_norm = RMSNorm(self.hd, weight=True) + self.proj = nn.Linear(dim, dim) + self.register_buffer("ones", torch.ones(heads, tokens, 1)) + + def forward(self, x: torch.Tensor) -> torch.Tensor: # (1, N, dim) + n, h, hd = self.tokens, self.heads, self.hd + q, k, v = self.qkv(x).split(self.dim, dim=-1) + q = self.q_norm(q.reshape(n, h, hd)).permute(1, 0, 2) # (H, N, hd) + k = self.k_norm(k.reshape(n, h, hd)).permute(1, 2, 0) # (H, hd, N) + v = v.reshape(n, h, hd).permute(1, 0, 2) # (H, N, hd) + s = torch.bmm(q, k) # (H, N, N) + e = torch.exp(s - s.amax(-1, keepdim=True)) + att = e * torch.reciprocal(torch.bmm(e, self.ones)) # softmax rows + out = torch.bmm(att, v).permute(1, 0, 2).reshape(1, n, self.dim) + return self.proj(out) + + +class DiTBlock(nn.Module): + """One adaLN-zero transformer block. + + The upstream `mod` (SiLU + Linear(dim, 6*dim), then chunk) is split into + six Linear(dim, dim) so every modulation vector gets its own activation + scale when quantized; the "1 + s" of the scale vectors is folded into the + biases of the two scale Linears. The relu2 activation is relu followed by + a multiplication (not pow, which would become a table). + """ + + def __init__(self, dim: int, heads: int, mlp_ratio: int, tokens: int) -> None: + super().__init__() + self.norm1 = RMSNorm(dim, weight=False) + self.attn = Attention(dim, heads, tokens) + self.norm2 = RMSNorm(dim, weight=False) + self.fc1 = nn.Linear(dim, mlp_ratio * dim) + self.fc2 = nn.Linear(mlp_ratio * dim, dim) + self.mods = nn.ModuleList([nn.Linear(dim, dim) for _ in range(6)]) # s1 b1 g1 s2 b2 g2 + + def forward(self, x: torch.Tensor, a: torch.Tensor) -> torch.Tensor: # a = silu(c), (1, dim) + s1, b1, g1, s2, b2, g2 = (m(a).reshape(1, 1, -1) for m in self.mods) + x = x + g1 * self.attn(self.norm1(x) * s1 + b1) + h = F.relu(self.fc1(self.norm2(x) * s2 + b2)) + h = h * h + return x + g2 * self.fc2(h) + + +class DiTStep(nn.Module): + """dit_step(z, c) -> v: the DiT velocity for one Euler step. + + z: normalised latent (1, z_ch, z_hw, z_hw); c: conditioning vector (1, dim). + Patchify is a strided Conv2d with the upstream Linear weights re-laid (the + (c, py, px) feature order of upstream's patchify is exactly the flattened + conv kernel layout). Unpatchify keeps the upstream output Linear (with its + bias) and follows it with a strided ConvTranspose2d whose fixed 0/1 weights + are a depth-to-space shuffle; an extra bias add after the transposed conv + would fuse into a RESCALE whose shift is too small for the 16-bit path. + """ + + def __init__(self, cfg: dict) -> None: + super().__init__() + d = cfg["dit"] + self.dim, self.depth, self.heads = int(d["dim"]), int(d["depth"]), int(d["heads"]) + self.patch, self.z_ch, self.z_hw = int(d["patch"]), int(cfg.get("latent_ch", 4)), int(cfg.get("latent_hw", 16)) + self.grid = self.z_hw // self.patch + self.tokens = self.grid * self.grid + pdim = self.z_ch * self.patch * self.patch + + self.embed = nn.Conv2d(self.z_ch, self.dim, self.patch, stride=self.patch) + self.register_buffer("pos", torch.zeros(1, self.tokens, self.dim)) + self.blocks = nn.ModuleList( + [DiTBlock(self.dim, self.heads, int(d["mlp_ratio"]), self.tokens) for _ in range(self.depth)] + ) + self.final_norm = RMSNorm(self.dim, weight=False) + self.final_mods = nn.ModuleList([nn.Linear(self.dim, self.dim) for _ in range(2)]) # s b + self.final = nn.Linear(self.dim, pdim) + self.unshuffle = nn.ConvTranspose2d(pdim, self.z_ch, self.patch, stride=self.patch, bias=False) + shuffle = torch.zeros(pdim, self.z_ch, self.patch, self.patch) + for c in range(self.z_ch): + for py in range(self.patch): + for px in range(self.patch): + shuffle[c * self.patch * self.patch + py * self.patch + px, c, py, px] = 1.0 + with torch.no_grad(): + self.unshuffle.weight.copy_(shuffle) + self.unshuffle.weight.requires_grad_(False) + self._pdim = pdim + + def forward(self, z: torch.Tensor, c: torch.Tensor) -> torch.Tensor: + x = self.embed(z).reshape(1, self.dim, self.tokens).permute(0, 2, 1) + self.pos + a = F.silu(c) + for blk in self.blocks: + x = blk(x, a) + s, b = (m(a).reshape(1, 1, -1) for m in self.final_mods) + x = self.final(self.final_norm(x) * s + b) # (1, tokens, pdim) + x = x.permute(0, 2, 1).reshape(1, self._pdim, self.grid, self.grid) + return self.unshuffle(x) + @torch.no_grad() + def load_state(self, sd: dict[str, torch.Tensor]) -> "DiTStep": + dim, p, C = self.dim, self.patch, self.z_ch + self.embed.weight.copy_(sd["embed.weight"].reshape(dim, C, p, p)) + self.embed.bias.copy_(sd["embed.bias"]) + self.pos.copy_(sd["pos"]) + for i, blk in enumerate(self.blocks): + pre = f"blocks.{i}." + blk.attn.qkv.weight.copy_(sd[pre + "attn.qkv.weight"]) + blk.attn.qkv.bias.copy_(sd[pre + "attn.qkv.bias"]) + blk.attn.q_norm.weight.copy_(sd[pre + "attn.q_norm.weight"] * self.blocks[0].attn.hd ** -0.5) + blk.attn.k_norm.weight.copy_(sd[pre + "attn.k_norm.weight"]) + blk.attn.proj.weight.copy_(sd[pre + "attn.proj.weight"]) + blk.attn.proj.bias.copy_(sd[pre + "attn.proj.bias"]) + blk.fc1.weight.copy_(sd[pre + "mlp.0.weight"]) + blk.fc1.bias.copy_(sd[pre + "mlp.0.bias"]) + blk.fc2.weight.copy_(sd[pre + "mlp.2.weight"]) + blk.fc2.bias.copy_(sd[pre + "mlp.2.bias"]) + w, b = sd[pre + "mod.1.weight"], sd[pre + "mod.1.bias"] + for j, m in enumerate(blk.mods): + m.weight.copy_(w[j * dim:(j + 1) * dim]) + m.bias.copy_(b[j * dim:(j + 1) * dim]) + blk.mods[0].bias.add_(1.0) # 1 + s1 + blk.mods[3].bias.add_(1.0) # 1 + s2 + w, b = sd["final_mod.1.weight"], sd["final_mod.1.bias"] + for j, m in enumerate(self.final_mods): + m.weight.copy_(w[j * dim:(j + 1) * dim]) + m.bias.copy_(b[j * dim:(j + 1) * dim]) + self.final_mods[0].bias.add_(1.0) # 1 + s + self.final.weight.copy_(sd["final.weight"]) + self.final.bias.copy_(sd["final.bias"]) + return self -def get_model(input_shape: tuple[int, ...] = INPUT_SHAPE) -> nn.Module: - # Fixed seed: the example uses untrained (random) weights, and a fixed seed - # keeps the exported program identical from one export to the next (the - # C array also embeds the Vela options, so the same working directory is - # part of that guarantee). - torch.manual_seed(0) - return TinyCNN(input_shape).eval() + @classmethod + def from_checkpoint(cls) -> "DiTStep": + ck = load_checkpoint() + return cls(ck.dit_cfg).load_state(ck.dit).eval() -def get_calibration_inputs( - input_shape: tuple[int, ...] = INPUT_SHAPE, calibration_samples: int = 2 -) -> list[torch.Tensor]: - """Float samples for quantization calibration; the first one is also the export example. +class Cond(nn.Module): + """c = t_mlp(timestep_embedding(t)) + y_emb(y): float, evaluated on the host.""" - Fixed values keep the quantization parameters, and with them the output - logits in the README, the same from one export to the next. Replace them - with representative, preprocessed data when calibrating a trained model. + def __init__(self, cfg: dict) -> None: + super().__init__() + dim, t_dim = int(cfg["dit"]["dim"]), int(cfg["t_embed_dim"]) + half = t_dim // 2 + freqs = torch.exp(-math.log(10000.0) * torch.arange(half, dtype=torch.float32) / half) + self.register_buffer("freqs1000", freqs * 1000.0) # t in [0, 1] scaled like DDPM + self.t_mlp = nn.Sequential(nn.Linear(t_dim, dim), nn.SiLU(), nn.Linear(dim, dim)) + self.y_emb = nn.Embedding(int(cfg.get("n_classes", 0)) + 1, dim) + + def forward(self, t: torch.Tensor, y: torch.Tensor) -> torch.Tensor: # t (B,) float, y (B,) int64 + args = t.float()[:, None] * self.freqs1000[None] + emb = torch.cat([torch.cos(args), torch.sin(args)], dim=-1) + return self.t_mlp(emb) + self.y_emb(y) + + @torch.no_grad() + def cond_table(self) -> torch.Tensor: + """(n_classes + 1, K_MAX, dim): c for every class at every schedule point.""" + n = self.y_emb.num_embeddings + t = torch.tensor(SCHEDULE, dtype=torch.float32) + return torch.stack([self(t, torch.full((len(SCHEDULE),), y, dtype=torch.int64)) for y in range(n)]) + + @torch.no_grad() + def load_state(self, sd: dict[str, torch.Tensor]) -> "Cond": + self.t_mlp[0].weight.copy_(sd["t_mlp.0.weight"]) + self.t_mlp[0].bias.copy_(sd["t_mlp.0.bias"]) + self.t_mlp[2].weight.copy_(sd["t_mlp.2.weight"]) + self.t_mlp[2].bias.copy_(sd["t_mlp.2.bias"]) + self.y_emb.weight.copy_(sd["y_emb.weight"]) + return self + + @classmethod + def from_checkpoint(cls) -> "Cond": + ck = load_checkpoint() + return cls(ck.dit_cfg).load_state(ck.dit).eval() + + +class Decoder(nn.Module): + """decode(z_norm) -> img in [-1, 1]: the VAE decoder. + + A chain of Conv3x3 (+ folded BatchNorm) + ReLU with nearest 2x upsampling + before the layers the plan flags, and a linear output conv. The latent + de-normalisation z = z_norm * std + mean is folded into the first conv. """ - samples = [torch.full(input_shape, 0.5), torch.full(input_shape, -0.5)][:calibration_samples] - for i in range(len(samples), calibration_samples): - samples.append(torch.randn(input_shape, generator=torch.Generator().manual_seed(i))) - return samples + + def __init__(self, plan: list[tuple[int, int]], z_ch: int, img_ch: int) -> None: + super().__init__() + self.up_before: set[int] = set() + body, c_in = [], z_ch + for i, (c_out, up) in enumerate(plan): + if up: + self.up_before.add(i) + body.append(nn.Conv2d(c_in, c_out, 3, padding=1)) + c_in = c_out + self.body = nn.ModuleList(body) + self.out = nn.Conv2d(c_in, img_ch, 3, padding=1) + + def forward(self, z: torch.Tensor) -> torch.Tensor: + h = z + for i, conv in enumerate(self.body): + if i in self.up_before: + h = F.interpolate(h, scale_factor=2.0, mode="nearest") + h = F.relu(conv(h)) + return torch.clamp(self.out(h), -1.0, 1.0) + + @torch.no_grad() + def load_state(self, sd: dict[str, torch.Tensor], mean: torch.Tensor, std: torch.Tensor) -> "Decoder": + for i, conv in enumerate(self.body): + w, b = sd[f"body.{i}.0.weight"], sd[f"body.{i}.0.bias"] + gamma, beta = sd[f"body.{i}.1.weight"], sd[f"body.{i}.1.bias"] + mu, var = sd[f"body.{i}.1.running_mean"], sd[f"body.{i}.1.running_var"] + f = gamma / torch.sqrt(var + 1e-5) + w = w * f[:, None, None, None] + b = (b - mu) * f + beta + if i == 0: # z_real = z_norm * std + mean, folded into the first conv + b = b + (w * mean[None, :, None, None]).sum(dim=(1, 2, 3)) + w = w * std[None, :, None, None] + conv.weight.copy_(w) + conv.bias.copy_(b) + self.out.weight.copy_(sd["out.weight"]) + self.out.bias.copy_(sd["out.bias"]) + return self + + @classmethod + def from_checkpoint(cls) -> "Decoder": + ck = load_checkpoint() + z_ch = int(ck.dit_cfg.get("latent_ch", 4)) + return cls(ck.dec_plan, z_ch, ck.img_ch).load_state(ck.dec, ck.latent_mean, ck.latent_std).eval() + + +# ---------------------------------------------------------------------------- +# Sampling (host reference) and calibration data + + +def schedule_steps(k_steps: int) -> list[tuple[int, float]]: + """[(k, dt)] for k_steps Euler steps striding the K_MAX schedule.""" + stride = len(SCHEDULE) // k_steps + if stride * k_steps != len(SCHEDULE): + raise ValueError(f"k_steps must divide {len(SCHEDULE)}") + ks = list(range(0, len(SCHEDULE), stride)) + ts = [SCHEDULE[k] for k in ks] + [0.0] + return [(k, t - t_next) for k, t, t_next in zip(ks, ts[:-1], ts[1:])] + + +@torch.no_grad() +def euler_sample( + dit: Callable[[torch.Tensor, torch.Tensor], torch.Tensor], + cond: torch.Tensor, + z: torch.Tensor, + y: int, + w: float | None = None, + k_steps: int = 4, + tap: Callable[[torch.Tensor, torch.Tensor], None] | None = None, +) -> torch.Tensor: + """Rectified-flow Euler sampling from noise z (1, C, H, W) to the final latent. + + cond: the (n_cond, K_MAX, dim) table of Cond.cond_table(). w: classifier-free + guidance strength (None or 0 = plain). tap(z, c) sees every dit input pair. + """ + guided = w is not None and w > 0 and y != NULL_CLASS + for k, dt in schedule_steps(k_steps): + c = cond[y, k][None] + if tap: + tap(z, c) + v = dit(z, c) + if guided: + c_null = cond[NULL_CLASS, k][None] + if tap: + tap(z, c_null) + v_null = dit(z, c_null) + v = v_null + w * (v - v_null) + z = z - dt * v + return z + + +def noise(seed: int, z_ch: int, z_hw: int) -> torch.Tensor: + """The firmware's starting noise for a seed: PCG32 (XSH-RR) and a sum of twelve + 12-bit uniforms per value (CLT-12), in CHW order, as src/app_main.cpp computes + it, so the host reference and the board sample from the same latent. The + generator is pico-faces' engine/src/prng.c; upstream fills in token order.""" + mask, mult, inc = (1 << 64) - 1, 6364136223846793005, 1442695040888963407 + state = inc + state = ((state + seed) * mult + inc) & mask + values = np.empty(z_ch * z_hw * z_hw, dtype=np.float32) + for i in range(values.size): + acc = 0 + for _ in range(12): + x, count = state, state >> 59 + state = (x * mult + inc) & mask + x ^= x >> 18 + out = (x >> 27) & 0xFFFFFFFF + acc += (((out >> count) | (out << ((32 - count) & 31))) & 0xFFFFFFFF) >> 20 + values[i] = (acc - 24576) / 4096.0 + return torch.from_numpy(values).reshape(1, z_ch, z_hw, z_hw) + + +@torch.no_grad() +def to_image(img: torch.Tensor) -> np.ndarray: + """(1, C, H, W) in [-1, 1] -> uint8 HWC, the same mapping the firmware uses.""" + x = ((img.clamp(-1, 1) + 1.0) * 127.5).round().clamp(0, 255).to(torch.uint8) + return x[0].permute(1, 2, 0).contiguous().numpy() + + +@functools.lru_cache(maxsize=None) +def _trajectories() -> tuple[list[tuple[torch.Tensor, torch.Tensor]], list[tuple[torch.Tensor]]]: + """Calibration inputs from float sampling runs (as upstream quant/calibrate.py). + + CALIB_SEEDS trajectories at the full K_MAX schedule; classes cycle 0..3, + every second run is guided with w=8 so the hotter guided activations are + covered too (both passes of each guided step are tapped). + """ + dit, cond = DiTStep.from_checkpoint(), Cond.from_checkpoint().cond_table() + dit_inputs: list[tuple[torch.Tensor, torch.Tensor]] = [] + dec_inputs: list[tuple[torch.Tensor]] = [] + for seed in range(CALIB_SEEDS): + z = noise(777 + seed, dit.z_ch, dit.z_hw) + y, w = seed % N_CLASSES, (max(CFG_W) if seed % 2 else None) + z0 = euler_sample(dit, cond, z, y, w, k_steps=len(SCHEDULE), tap=lambda z, c: dit_inputs.append((z.clone(), c.clone()))) + dec_inputs.append((z0,)) + return dit_inputs, dec_inputs + + +def calib_dit_step() -> Iterable[tuple[torch.Tensor, ...]]: + return _trajectories()[0] + + +def calib_decode() -> Iterable[tuple[torch.Tensor, ...]]: + return _trajectories()[1] + + +# ---------------------------------------------------------------------------- +# The contract with create_ai_layer.py + + +@dataclass(frozen=True) +class Method: + """One method of the program; the fields create_ai_layer.Method has.""" + + name: str + module: nn.Module + example_inputs: tuple[torch.Tensor, ...] + calibration: Callable[[], Iterable[tuple[torch.Tensor, ...]]] | None = None + quantization: str = "a8w8" + + +def quantization(kind: str, variable: str) -> str: + if kind not in ("a8w8", "a16w8"): + sys.exit(f"{variable}={kind!r}: expected a8w8 or a16w8") + return kind + + +def example_inputs() -> tuple[torch.Tensor, torch.Tensor]: + """(z, c) for dit_step; z alone is decode's input.""" + ck = load_checkpoint() + z_ch, z_hw = int(ck.dit_cfg.get("latent_ch", 4)), int(ck.dit_cfg.get("latent_hw", 16)) + return noise(0, z_ch, z_hw), Cond.from_checkpoint().cond_table()[NULL_CLASS, 0][None] + + +def get_methods() -> list[Method]: + z, c = example_inputs() + return [ + Method("dit_step", DiTStep.from_checkpoint(), (z, c), calib_dit_step, + quantization(QUANTIZATION, "PICO_FACES_QUANT")), + Method("decode", Decoder.from_checkpoint(), (z,), calib_decode, + quantization(DECODE_QUANTIZATION, "PICO_FACES_DECODE_QUANT")), + ] + + +def macs(module: nn.Module, inputs: tuple[torch.Tensor, ...]) -> int: + """Multiply-accumulates of the convolutions and matrix products of one call.""" + from torch.utils.flop_counter import FlopCounterMode + + with FlopCounterMode(display=False) as counter, torch.no_grad(): + module(*inputs) + return counter.get_total_flops() // 2 + + +def get_params() -> dict: + """Constants the firmware needs; create_ai_layer.py writes them to model_params.h.""" + ck = load_checkpoint() + dit, dec = DiTStep.from_checkpoint(), Decoder.from_checkpoint() + cond = Cond.from_checkpoint().cond_table() # (N_CLASSES + 1, K_MAX, dim) + z, c = example_inputs() + return { + "PF_VARIANT": VARIANT, + "PF_QUANT": f"{QUANTIZATION}/{DECODE_QUANTIZATION}", # dit_step / decode + "PF_LATENT_CH": dit.z_ch, + "PF_LATENT_HW": dit.z_hw, + "PF_IMG_CH": ck.img_ch, + "PF_IMG_HW": dit.z_hw << len(dec.up_before), + "PF_COND_DIM": cond.shape[2], + "PF_N_CLASSES": N_CLASSES, + "PF_NULL_CLASS": NULL_CLASS, # unconditional; also the negative of the guidance blend + "PF_N_COND": cond.shape[0], + "PF_K_MAX": len(SCHEDULE), + "PF_N_CFG_W": len(CFG_W), + "PF_MACS_DIT_STEP": macs(dit, (z, c)), + "PF_MACS_DECODE": macs(dec, (z,)), + # t of every schedule step; a run of k steps uses every (PF_K_MAX / k)-th + # entry and integrates from t to the next used entry (0 after the last). + "pf_schedule": SCHEDULE, + # Guidance strengths pico-faces' firmware cycles through (any w > 0 works here). + "pf_cfg_w": CFG_W, + # c(t_k, y) = t_mlp(timestep_embedding(t_k)) + y_emb(y), indexed [class][step]. + "pf_cond": cond, + } diff --git a/model/verify_export.py b/model/verify_export.py new file mode 100644 index 00000000..755050bc --- /dev/null +++ b/model/verify_export.py @@ -0,0 +1,247 @@ +#!/usr/bin/env python3 +# Copyright 2026 Arm Limited and/or its affiliates. +# SPDX-License-Identifier: Apache-2.0 +"""Host-side checks for the pico-faces export in model.py. + + python model/verify_export.py --stage float --seed 3 --class 1 --w 4 --k 4 --out out/pf_float.png + python model/verify_export.py --stage fakequant --seed 3 --class 1 --w 4 --k 4 --out out/pf_fakequant.png + python model/verify_export.py --stage tosa + python model/verify_export.py --check-upstream /path/to/pico-faces + python model/verify_export.py --compare out/fvp_image.bin out/pf_fakequant.png + +--stage float samples with the float modules of model.py: the reference. +--stage fakequant samples with the quantize/dequantize graphs create_ai_layer.py + produces (convert_pt2e), i.e. what the NPU is expected to compute. +--stage tosa lowers both methods with the TOSA backend and executes one + input each through the TOSA reference model: the integer + semantics the Ethos-U implements (tables, rescales, int48 + accumulators), which the fake-quant graphs do not model. A + large deviation from fakequant here means the NPU output will + be wrong too; run it before flashing a changed 16-bit graph. +--check-upstream compares model.py's re-implementation (folded scales, conv + patchify, BatchNorm and latent folds) against the original + pico-faces modules from a clone of the upstream repository. +--compare PSNR between two images: PNGs, or the raw 128x128 RGB frame + the FVP run writes to out/fvp_image.bin. + +The host stages use the firmware's noise generator, so the same seed, class, +guidance and step count give the image the board and the FVP produce (up to +the rounding differences between the fake-quant graphs and the NPU). + +Runs itself in the solution's .venv, like create_ai_layer.py. +""" + +from __future__ import annotations + +import argparse +import math +import os +import subprocess +import sys +import time +from pathlib import Path + +HERE = Path(__file__).resolve().parent +ROOT = HERE.parent + + +def run_in_venv(required: bool) -> None: + """Re-run under the project's .venv unless this interpreter already is it. + + Only --compare works without it (numpy and pillow are enough).""" + venv = ROOT / ".venv" + if Path(sys.prefix).resolve() == venv.resolve(): + return + python = venv / ("Scripts/python.exe" if os.name == "nt" else "bin/python") + if not python.is_file(): + if not required: + return + sys.exit(f"{venv} does not exist. Create it first: ./setup_venv.sh (Linux/macOS) or setup_venv.bat (Windows)") + sys.exit(subprocess.run([str(python), __file__, *sys.argv[1:]]).returncode) + + +def save_png(img_u8, path: Path) -> None: + from PIL import Image + + path.parent.mkdir(parents=True, exist_ok=True) + Image.fromarray(img_u8, "RGB" if img_u8.shape[-1] == 3 else "L").save(path) + print(f"wrote {path}") + + +def stage_modules(stage: str, mlops_file: str | None): + """(dit_step callable, decode callable) for the requested stage.""" + import model as M + + if stage == "float": + return M.DiTStep.from_checkpoint(), M.Decoder.from_checkpoint() + + sys.path.insert(0, str(ROOT)) + import create_ai_layer as C + + spec = C.compile_spec_from_file(mlops_file) if mlops_file else C.default_compile_spec() + mods = {m.name: C.quantize_method(m, spec) for m in M.get_methods()} + return mods["dit_step"], mods["decode"] + + +def sample(args) -> None: + import model as M + + dit, dec = stage_modules(args.stage, args.mlops) + cond = M.Cond.from_checkpoint().cond_table() + z = M.noise(args.seed, *M.example_inputs()[0].shape[1:3]) + t0 = time.time() + z0 = M.euler_sample(dit, cond, z, args.cls, args.w, args.k) + img = M.to_image(dec(z0)) + print(f"{args.stage}: seed {args.seed} class {args.cls} w {args.w} k {args.k}: {time.time() - t0:.1f} s") + save_png(img, Path(args.out)) + + +def check_tosa(args) -> None: + """Run both methods through the TOSA reference model and compare with fake-quant and float.""" + import torch + from executorch.backends.arm.quantizer import TOSAQuantizer + from executorch.backends.arm.test.runner_utils import TosaReferenceModelDispatch + from executorch.backends.arm.tosa.compile_spec import TosaCompileSpec + from executorch.backends.arm.tosa.partitioner import TOSAPartitioner + from executorch.exir import EdgeCompileConfig, to_edge_transform_and_lower + from torchao.quantization.pt2e.quantize_pt2e import convert_pt2e, prepare_pt2e + + import model as M + + sys.path.insert(0, str(ROOT)) + import create_ai_layer as C + + z = M.noise(args.seed, *M.example_inputs()[0].shape[1:3]) + cond = M.Cond.from_checkpoint().cond_table() + floats = {"dit_step": M.DiTStep.from_checkpoint(), "decode": M.Decoder.from_checkpoint()} + worst = 0.0 + for m in M.get_methods(): + spec = TosaCompileSpec("TOSA-1.0+INT+int16" if m.quantization == "a16w8" else "TOSA-1.0+INT") + cfg = C.quant_config(m.quantization) + graph = torch.export.export(m.module, m.example_inputs).module() + C.strip_guards_fn(graph) + quantizer = TOSAQuantizer(spec) + quantizer.set_global(cfg) + prepared = prepare_pt2e(graph, quantizer) + C.calibrate(prepared, m) + converted = convert_pt2e(prepared) + edge = to_edge_transform_and_lower( + torch.export.export(converted, m.example_inputs), + partitioner=[TOSAPartitioner(spec)], + compile_config=EdgeCompileConfig(_check_ir_validity=False), + ) + program = edge.to_executorch() + inputs = (z, cond[args.cls, 0][None]) if m.name == "dit_step" else (z,) + with torch.no_grad(): + fq = converted(*inputs) + fl = floats[m.name](*inputs) + with TosaReferenceModelDispatch(): + ref = program.exported_program().module()(*inputs) + ref = ref[0] if isinstance(ref, (list, tuple)) else ref + d_fq, d_fl = (ref - fq).abs().max().item(), (ref - fl).abs().max().item() + worst = max(worst, d_fq / max(fl.abs().max().item(), 1e-6)) + print(f" {m.name}: refmodel-vs-fakequant max {d_fq:.4f}, refmodel-vs-float max {d_fl:.4f}, " + f"fakequant-vs-float max {(fq - fl).abs().max().item():.4f}, |float| max {fl.abs().max().item():.2f}") + ok = worst <= 0.05 + print(f"tosa: worst relative deviation from fakequant {worst:.3f} -> {'OK' if ok else 'MISMATCH'}") + sys.exit(0 if ok else 1) + + +def check_upstream(clone: str) -> None: + import torch + + import model as M + + sys.path.insert(0, clone) + from train.common.sincos import timestep_embedding + from train.dit.model import build_model + from train.vae.model import build_vae + + ck = M.load_checkpoint() + up = build_model(ck.dit_cfg).eval() + up.load_state_dict(ck.dit) + vae_ckpt = torch.load(M.checkpoint_dir() / "vae_final.pt", map_location="cpu", weights_only=False) + up_vae = build_vae(vae_ckpt["cfg"]).eval() + up_vae.load_state_dict(vae_ckpt["model"]) + + ours, cond, dec = M.DiTStep.from_checkpoint(), M.Cond.from_checkpoint(), M.Decoder.from_checkpoint() + g = torch.Generator().manual_seed(1) + worst = 0.0 + with torch.no_grad(): + for i in range(8): + z = torch.randn(1, ours.z_ch, ours.z_hw, ours.z_hw, generator=g) * (1.0 + i / 4) + t = torch.rand(1, generator=g) + y = torch.tensor([i % (M.N_CLASSES + 1)]) + c_up = up.t_mlp(timestep_embedding(t, up.t_dim)) + up.y_emb(y) + c_ours = cond(t, y) + d_c = (c_up - c_ours).abs().max().item() + v_up = up(z, t, y) + v_ours = ours(z, c_ours) + d_v = (v_up - v_ours).abs().max().item() / max(v_up.abs().max().item(), 1e-6) + worst = max(worst, d_c, d_v) + print(f" sample {i}: |dc| {d_c:.2e} rel |dv| {d_v:.2e}") + z = torch.randn(1, ours.z_ch, ours.z_hw, ours.z_hw, generator=g) + img_up = up_vae.decoder(z * ck.latent_std[None, :, None, None] + ck.latent_mean[None, :, None, None]).clamp(-1, 1) + img_ours = dec(z) + d_img = (img_up - img_ours).abs().max().item() + worst = max(worst, d_img) + print(f" decoder: |dimg| {d_img:.2e} (max pixel step 7.8e-3)") + # The DiT and conditioning must match to float precision; the decoder folds the + # latent mean into the zero-padded first conv (as upstream does), which shifts + # border pixels by about one 8-bit step. + ok = worst <= 2e-2 + print(f"check-upstream: worst deviation {worst:.2e} -> {'OK' if ok else 'MISMATCH'}") + sys.exit(0 if ok else 1) + + +def load_image(path: str): + """An image as float HWC RGB: a PNG, or a raw 128x128x3 frame (.bin).""" + import numpy as np + from PIL import Image + + if path.endswith(".bin"): + return np.fromfile(path, dtype=np.uint8).reshape(128, 128, 3).astype(np.float64) + return np.asarray(Image.open(path).convert("RGB"), dtype=np.float64) + + +def compare(a: str, b: str, min_psnr: float | None) -> None: + import numpy as np + + x, y = load_image(a), load_image(b) + if x.shape != y.shape: + sys.exit(f"shape mismatch: {x.shape} vs {y.shape}") + mse = ((x - y) ** 2).mean() + psnr = math.inf if mse == 0 else 10 * math.log10(255.0**2 / mse) + print(f"PSNR {psnr:.2f} dB, max |diff| {int(np.abs(x - y).max())}, mean |diff| {np.abs(x - y).mean():.2f}") + if min_psnr is not None and psnr < min_psnr: + sys.exit(f"PSNR below {min_psnr} dB") + + +def main() -> None: + ap = argparse.ArgumentParser(description=__doc__, formatter_class=argparse.RawDescriptionHelpFormatter) + ap.add_argument("--stage", choices=["float", "fakequant", "tosa"], default="float") + ap.add_argument("--seed", type=int, default=3) + ap.add_argument("--class", dest="cls", type=int, default=1, help="0..3, or 4 = unconditional") + ap.add_argument("--w", type=float, default=4.0, help="guidance strength, 0 = plain") + ap.add_argument("--k", type=int, default=4, help="Euler steps: 8, 4, 2 or 1") + ap.add_argument("--out", default="out/pf.png") + ap.add_argument("--mlops", help="*.cbuild-mlops.yml to take the Vela options from (fakequant)") + ap.add_argument("--check-upstream", metavar="CLONE", help="path to a pico-faces clone") + ap.add_argument("--compare", nargs=2, metavar=("A", "B"), help="two images: .png, or a raw 128x128 RGB .bin") + ap.add_argument("--min-psnr", type=float, help="with --compare: fail below this PSNR (dB)") + args = ap.parse_args() + run_in_venv(required=not args.compare) + + sys.path.insert(0, str(HERE)) + if args.check_upstream: + check_upstream(args.check_upstream) + elif args.compare: + compare(*args.compare, args.min_psnr) + elif args.stage == "tosa": + check_tosa(args) + else: + sample(args) + + +if __name__ == "__main__": + main() diff --git a/requirements.txt b/requirements.txt index 75f8ff19..06cecade 100644 --- a/requirements.txt +++ b/requirements.txt @@ -4,13 +4,22 @@ # executorch, torch and torchao must match: a .pte exported by one ExecuTorch # version only loads in the runtime of the same version, and that runtime is # the PyTorch::ExecuTorch@1.5.1 pack pinned in the csolution. ExecuTorch 1.5.1 -# targets torch 2.14.0 (torch_pin.py at the v1.5.1 tag) and torchao 0.18 -# (the wheel requires torchao>=0.18.0,<0.19); prebuilt wheels exist for Linux, -# macOS and Windows, Python 3.10 to 3.14 (the export venv stays below 3.14: -# see requirements-arm-tosa.txt). +# targets torch 2.14.0 and torchao 0.18.0 (torch_pin.py and +# install_requirements.py of the v1.5.1 tag); prebuilt wheels exist for Linux, +# macOS and Windows, Python 3.10 to 3.14 (the export venv stays below 3.14: see +# requirements-arm-tosa.txt). executorch==1.5.1 torch==2.14.0 torchao==0.18.0 # Vela, the Ethos-U compiler. Same pin as executorch's `ethos_u` extra. ethos-u-vela==5.1.0 + +# Used directly by create_ai_layer.py and model/model.py (the cbuild-mlops.yml +# reader, the checkpoint and calibration code). executorch pulls both in as +# well; listing them keeps the dependency explicit. +numpy +pyyaml + +# Host-side checks only: model/verify_export.py reads and writes PNGs. +pillow diff --git a/setup_venv.py b/setup_venv.py index 0d79bc06..b0814479 100755 --- a/setup_venv.py +++ b/setup_venv.py @@ -6,22 +6,45 @@ # # Runs on Linux, macOS and Windows. The thin wrappers setup_venv.sh and # setup_venv.bat just delegate here; everything OS-specific lives in this file. -"""Create (or repair) the .venv used to export the model.""" +"""Create (or repair) the .venv used to export the model, and fetch the model checkpoints.""" from __future__ import annotations import argparse +import hashlib import os import re import shutil import subprocess import sys +import urllib.error +import urllib.request import venv from pathlib import Path HERE = Path(__file__).resolve().parent VENV_DIR = HERE / ".venv" +# The pico-faces checkpoints model/model.py loads (https://github.com/cpldcpu/pico-faces, +# MIT license, see model/LICENSE-pico-faces). They are downloaded from a pinned +# upstream commit and verified by SHA-256 into model/pico_faces//, or read +# from $PICO_FACES_DIR/checkpoints// when that variable points at a clone. +PICO_FACES_REPO = "cpldcpu/pico-faces" +PICO_FACES_COMMIT = "ee15d9d183d8428efaeb3078edf47669cfc23994" # 2026-09-12, adds the LICENSE +PICO_FACES_DIR = HERE / "model" / "pico_faces" +PICO_FACES_FILES: dict[str, dict[str, str]] = { + "m3_long_cfg": { + "dit_qat.pt": "d645192896db72e71905d65d465e9c08384502336f9d02811d476743efac651a", + "vae_final.pt": "273d0d1b1784dec8d122642fd6dc028fc1427763f4b0fcbfdb86853621e46646", + "latent_stats.npz": "3cb07560a18a3e7a4b448e99c4ff00cf531cf51fe8d0ce2e97ab00f2b4113470", + }, + "m3_decD_deep_full": { + "dit_qat.pt": "430ca1ef03c52008e46e477ecdbbcf47d61b8588ebee1556e955bfe52c1905e3", + "vae_final.pt": "3dcd8e09a8717f5011373c77a64e18bd83cfa493a7a6cda6a79d56d7034ef3db", + "latent_stats.npz": "3cb07560a18a3e7a4b448e99c4ff00cf531cf51fe8d0ce2e97ab00f2b4113470", + }, +} + # ExecuTorch 1.5 declares requires-python = ">=3.10,<3.15" in its pyproject.toml, # but the tosa-tools 2026.5.0 it pins for the Arm backend (see # requirements-arm-tosa.txt) only ships wheels up to CPython 3.13, so on 3.14 @@ -137,6 +160,62 @@ def smoke_test(python: Path) -> None: ) +def sha256(path: Path) -> str: + digest = hashlib.sha256() + with path.open("rb") as f: + for chunk in iter(lambda: f.read(1 << 20), b""): + digest.update(chunk) + return digest.hexdigest() + + +def download(url: str, dest: Path) -> None: + """Fetch url into dest with urllib; fall back to curl when the interpreter has + no usable root certificates (the python.org macOS build until its + "Install Certificates" step has been run).""" + try: + with urllib.request.urlopen(url) as response, dest.open("wb") as out: + shutil.copyfileobj(response, out) + return + except urllib.error.URLError as exc: + if "CERTIFICATE_VERIFY_FAILED" not in str(exc) or shutil.which("curl") is None: + raise + print(" (urllib has no root certificates; using curl)", flush=True) + subprocess.run(["curl", "-fsSL", "--retry", "3", "-o", str(dest), url], check=True) + + +def fetch_checkpoints(variant: str) -> None: + """Download the pico-faces checkpoints of `variant` into model/pico_faces//. + + Files already present with the expected SHA-256 are kept; a download with + another hash fails the setup. + """ + if os.environ.get("PICO_FACES_DIR"): + print(f"PICO_FACES_DIR is set ({os.environ['PICO_FACES_DIR']}); not downloading checkpoints.") + return + + target = PICO_FACES_DIR / variant + target.mkdir(parents=True, exist_ok=True) + base = f"https://raw.githubusercontent.com/{PICO_FACES_REPO}/{PICO_FACES_COMMIT}/checkpoints/{variant}/" + for name, expected in PICO_FACES_FILES[variant].items(): + path = target / name + if path.is_file() and sha256(path) == expected: + print(f"checkpoint ok: {path.relative_to(HERE)}") + continue + url = base + name + print(f"downloading {url}", flush=True) + tmp = path.with_suffix(path.suffix + ".part") + download(url, tmp) + actual = sha256(tmp) + if actual != expected: + tmp.unlink(missing_ok=True) + sys.exit( + f"error: {name} from {url} has SHA-256 {actual}, expected {expected}.\n" + "The pinned upstream file changed or the download was corrupted." + ) + tmp.replace(path) + print(f"checkpoint ok: {path.relative_to(HERE)} ({path.stat().st_size / 1e6:.1f} MB)") + + def main() -> int: parser = argparse.ArgumentParser(description=__doc__) parser.add_argument( @@ -158,8 +237,28 @@ def main() -> int: action="store_true", help="delete and rebuild .venv even if it looks usable", ) + parser.add_argument( + "--variant", + default=os.environ.get("PICO_FACES_VARIANT", "m3_long_cfg"), + choices=sorted(PICO_FACES_FILES), + help="pico-faces model variant whose checkpoints to download (default: %(default)s)", + ) + parser.add_argument( + "--skip-download", + action="store_true", + help="do not download the pico-faces checkpoints", + ) + parser.add_argument( + "--download-only", + action="store_true", + help="only download the checkpoints; leave the venv alone", + ) args = parser.parse_args() + if args.download_only: + fetch_checkpoints(args.variant) + return 0 + if args.python and not args.uv: parser.error("--python requires --uv") uv = shutil.which("uv") if args.uv else None @@ -215,6 +314,9 @@ def main() -> int: smoke_test(python) + if not args.skip_download: + fetch_checkpoints(args.variant) + print() print(f"venv ready: {VENV_DIR}") print("create_ai_layer.py runs itself with this interpreter:") diff --git a/src/app_main.cpp b/src/app_main.cpp index b7fc869f..b5b16f59 100644 --- a/src/app_main.cpp +++ b/src/app_main.cpp @@ -1,29 +1,59 @@ // Copyright 2026 Arm Limited and/or its affiliates. // SPDX-License-Identifier: Apache-2.0 // -// Headless ExecuTorch runner for the Ethos-U85 example. Loads the .pte -// embedded by the AI layer (model_pte.h, see create_ai_layer.py), runs one -// inference on the NPU, and prints the output logits. Built entirely from the -// PyTorch::ExecuTorch pack's runtime + operator components; the board layer -// provides main(), stdout and the Ethos-U driver init and then calls app_main. +// pico-faces on Ethos-U85: a face generator built on the ExecuTorch runtime. +// The AI layer (create_ai_layer.py) embeds one program with two methods +// delegated to the NPU: +// +// dit_step(z, c) -> v the diffusion transformer's velocity for one step +// decode(z) -> img the latent decoder, 128x128 RGB in [-1, 1] +// +// and model_params.h with the sampling schedule and the conditioning vectors +// c(t_k, class). This file runs the rectified-flow Euler loop (with optional +// classifier-free guidance) around those methods, converts the image to 8-bit +// RGB and prints a CRC and an ASCII preview. With APP_INTERACTIVE (the +// DevKit-E8 board layer) it then serves pico-faces' serial protocol, so that +// pico-faces' viewer (viewer/view_serial.py) can request and display images: +// +// host -> "G [k_steps] [class] [w]\n" "I\n" prints an info line +// dev -> "RFI2" u32 seed u16 w u16 h u16 ch u16 class | w*h*ch bytes (HWC) +// | u32 crc32 | u32 gen_ms +// +// The board layer provides main(), stdout/stdin and the Ethos-U driver init and +// then calls app_main(). // // EmbeddedModule (arm_embedded_module.hpp) manages program loading, method // memory and execution, like ExecuTorch's Module class does on POSIX hosts. #include +#include #include #include +#include +#include +#include #include +#include + +#include "RTE_Components.h" +#include CMSIS_device_header #include #include #include #include +#include #include #include "arm_embedded_module.hpp" +#include "model_params.h" #include "model_pte.h" +#if defined(ETHOSU_ARCH) +#include "ethosu_driver.h" +#include "pmu_ethosu.h" +#endif + using arm::embedded::EmbeddedModule; using executorch::aten::DimOrderType; using executorch::aten::ScalarType; @@ -31,8 +61,34 @@ using executorch::aten::SizesType; using executorch::aten::Tensor; using executorch::aten::TensorImpl; using executorch::extension::BufferDataLoader; +using executorch::runtime::Error; using executorch::runtime::EValue; using executorch::runtime::MemoryAllocator; +using executorch::runtime::MethodMeta; +using executorch::runtime::Result; +using executorch::runtime::Span; +using executorch::runtime::TensorInfo; + +extern "C" int stdout_putchar(int ch); // CMSIS-Compiler retarget hooks +extern "C" int stdin_getchar(void); +#ifdef APP_BUTTONS +// Board layer (board/DevKit-E8/buttons.c): SW2 joystick presses since the last +// call (bit mask), and a console read that does not block (-1 when nothing is +// waiting). +extern "C" unsigned board_buttons(void); +extern "C" int board_console_poll(void); +constexpr unsigned kButtonLeft = 1u << 0; +constexpr unsigned kButtonRight = 1u << 1; +#endif +#ifdef APP_DISPLAY +// Board layer (board/DevKit-E8/display.c): show an 8-bit RGB image on the +// board's display. Returns 0 on success. +extern "C" int board_display_image(const uint8_t* rgb, int width, int height, int channels); +#endif +#ifdef APP_RESULT_DIR +// Board layer (board/Corstone-320/retarget_stdio.c): write a file on the host. +extern "C" int board_save_file(const char* path, const void* data, size_t n); +#endif namespace { @@ -52,62 +108,604 @@ namespace { #define APP_POOL_ATTRIBUTES #endif +// The boot demo: seed 3, 4 steps, class 1 (female, smiling), guidance 4. +#ifndef APP_DEMO_SEED +#define APP_DEMO_SEED 3 +#endif +#ifndef APP_DEMO_STEPS +#define APP_DEMO_STEPS 4 +#endif +#ifndef APP_DEMO_CLASS +#define APP_DEMO_CLASS 1 +#endif +#ifndef APP_DEMO_W +#define APP_DEMO_W 4.0f +#endif + constexpr size_t kMethodPoolSize = APP_METHOD_POOL_SIZE; constexpr size_t kTempPoolSize = APP_TEMP_POOL_SIZE; +constexpr size_t kLatent = PF_LATENT_CH * PF_LATENT_HW * PF_LATENT_HW; +constexpr size_t kImage = PF_IMG_HW * PF_IMG_HW * PF_IMG_CH; +constexpr const char* kDitStep = "dit_step"; +constexpr const char* kDecode = "decode"; alignas(16) uint8_t g_method_pool[kMethodPoolSize] APP_POOL_ATTRIBUTES; alignas(16) uint8_t g_temp_pool[kTempPoolSize] APP_POOL_ATTRIBUTES; +// Generation state; static so the 32 kB main stack stays small. +float g_z[kLatent]; +float g_v[kLatent]; +float g_vn[kLatent]; +float g_c[PF_COND_DIM]; +uint8_t g_img[kImage]; + +// The method inputs wrap g_z and g_c; EmbeddedModule copies them into the +// method's own input buffers on every call. +std::array g_latent_sizes{1, PF_LATENT_CH, PF_LATENT_HW, PF_LATENT_HW}; +std::array g_latent_order{0, 1, 2, 3}; +std::array g_cond_sizes{1, PF_COND_DIM}; +std::array g_cond_order{0, 1}; +TensorImpl g_z_impl(ScalarType::Float, g_latent_sizes.size(), g_latent_sizes.data(), g_z, g_latent_order.data()); +TensorImpl g_c_impl(ScalarType::Float, g_cond_sizes.size(), g_cond_sizes.data(), g_c, g_cond_order.data()); + +// Per-method NPU counters from the Ethos-U PMU: cycles the NPU was clocked +// (CCNT), cycles it was active, cycles its MAC array was active, and data beats +// read on the two AXI ports (on the Ensemble E8 all traffic, weights from MRAM +// included, arrives on port 0). +struct NpuCounters { + uint64_t cycles; + uint64_t active; + uint64_t mac_active; + uint64_t axi0_read_beats; + uint64_t axi1_read_beats; +}; + +struct Timing { + uint32_t dit_ms; + uint32_t dit_calls; + uint32_t decode_ms; + uint32_t total_ms; + NpuCounters dit_npu; + NpuCounters decode_npu; +}; + +// --------------------------------------------------------------------------- +// Ethos-U PMU: the driver instance belongs to the board layer; the driver's +// reserve/release API hands it out between inferences. + +#if defined(ETHOSU_ARCH) +constexpr uint32_t kPmuCounters = ETHOSU_PMU_CCNT_Msk | ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CNT2_Msk | + ETHOSU_PMU_CNT3_Msk | ETHOSU_PMU_CNT4_Msk; + +void npu_pmu_start() { + ethosu_driver* drv = ethosu_reserve_driver(); + ETHOSU_PMU_Enable(drv); + ETHOSU_PMU_Set_EVTYPER(drv, 0, ETHOSU_PMU_NPU_ACTIVE); + ETHOSU_PMU_Set_EVTYPER(drv, 1, ETHOSU_PMU_MAC_ACTIVE); + ETHOSU_PMU_Set_EVTYPER(drv, 2, ETHOSU_PMU_EXT0_RD_DATA_BEAT_RECEIVED); + ETHOSU_PMU_Set_EVTYPER(drv, 3, ETHOSU_PMU_EXT1_RD_DATA_BEAT_RECEIVED); + ETHOSU_PMU_CYCCNT_Reset(drv); + ETHOSU_PMU_EVCNTR_ALL_Reset(drv); + ETHOSU_PMU_CNTR_Enable(drv, kPmuCounters); + ethosu_release_driver(drv); +} + +void npu_pmu_stop(NpuCounters& c) { + ethosu_driver* drv = ethosu_reserve_driver(); + ETHOSU_PMU_CNTR_Disable(drv, kPmuCounters); + c.cycles += ETHOSU_PMU_Get_CCNTR(drv); + c.active += ETHOSU_PMU_Get_EVCNTR(drv, 0); + c.mac_active += ETHOSU_PMU_Get_EVCNTR(drv, 1); + c.axi0_read_beats += ETHOSU_PMU_Get_EVCNTR(drv, 2); + c.axi1_read_beats += ETHOSU_PMU_Get_EVCNTR(drv, 3); + ethosu_release_driver(drv); +} +#else +void npu_pmu_start() {} +void npu_pmu_stop(NpuCounters&) {} +#endif + +// --------------------------------------------------------------------------- +// Millisecond tick from SysTick, for per-phase timing (the DWT cycle counter +// does not count on every device). Not meaningful on the FVP. + +volatile uint32_t g_ms_ticks; + +void ticks_init() { + SysTick_Config(SystemCoreClock / 1000u); +} + +inline uint32_t ms_now() { return g_ms_ticks; } + +// --------------------------------------------------------------------------- +// PCG32 + CLT-12 gaussian, as pico-faces' engine/src/prng.c. The noise is +// filled in CHW order (upstream fills in token order), so a seed gives other +// faces than on the Pico, but the same as model/verify_export.py on the host. + +uint64_t g_pcg_state; + +void pcg32_seed(uint64_t seed) { + const uint64_t mult = 6364136223846793005ULL, inc = 1442695040888963407ULL; + g_pcg_state = 0; + g_pcg_state = g_pcg_state * mult + inc; + g_pcg_state += seed; + g_pcg_state = g_pcg_state * mult + inc; +} + +uint32_t pcg32_next() { + const uint64_t mult = 6364136223846793005ULL, inc = 1442695040888963407ULL; + uint64_t x = g_pcg_state; + unsigned count = static_cast(x >> 59); + g_pcg_state = x * mult + inc; + x ^= x >> 18; + uint32_t out = static_cast(x >> 27); + return (out >> count) | (out << ((32 - count) & 31)); +} + +float gauss() { + int32_t acc = 0; + for (int j = 0; j < 12; ++j) { + acc += static_cast(pcg32_next() >> 20); + } + return static_cast(acc - 24576) / 4096.0f; +} + +// --------------------------------------------------------------------------- +// CRC-32 (IEEE, reflected), the same as zlib / Python's binascii.crc32. + +uint32_t g_crc_table[256]; + +void crc32_init() { + for (uint32_t i = 0; i < 256; ++i) { + uint32_t c = i; + for (int k = 0; k < 8; ++k) { + c = (c & 1u) ? (0xEDB88320u ^ (c >> 1)) : (c >> 1); + } + g_crc_table[i] = c; + } +} + +uint32_t crc32(const uint8_t* data, size_t n) { + uint32_t c = 0xFFFFFFFFu; + for (size_t i = 0; i < n; ++i) { + c = g_crc_table[(c ^ data[i]) & 0xFFu] ^ (c >> 8); + } + return c ^ 0xFFFFFFFFu; +} + +// --------------------------------------------------------------------------- +// Methods + +bool check_shape(const TensorInfo& info, const char* what, std::initializer_list expect) { + Span sizes = info.sizes(); + bool ok = sizes.size() == expect.size(); + size_t i = 0; + for (int32_t d : expect) { + ok = ok && sizes[i++] == d; + } + if (!ok) { + printf("%s: unexpected shape [", what); + for (size_t j = 0; j < sizes.size(); ++j) { + printf("%s%d", j ? "," : "", static_cast(sizes[j])); + } + printf("], model_params.h says ["); + i = 0; + for (int32_t d : expect) { + printf("%s%d", i++ ? "," : "", static_cast(d)); + } + printf("]\n"); + } + return ok; +} + +// Loads a method up front (EmbeddedModule would do it on the first call) and +// prints what it needs. +bool load_method(EmbeddedModule& module, const char* name) { + Result meta = module.method_meta(name); + if (!meta.ok()) { + printf("method %s not found in the program (err=%u)\n", name, static_cast(meta.error())); + return false; + } + Error err = module.load_method(name); + if (err != Error::Ok) { + printf("load_method(%s) failed (err=%u)\n", name, static_cast(err)); + return false; + } + size_t planned_bytes = 0; + for (size_t i = 0; i < meta->num_memory_planned_buffers(); ++i) { + planned_bytes += static_cast(meta->memory_planned_buffer_size(i).get()); + } + printf(" %-9s %u input(s), %u output(s), %u planned byte(s)\n", name, + static_cast(meta->num_inputs()), static_cast(meta->num_outputs()), + static_cast(planned_bytes)); + return true; +} + +// Executes a method; returns its first output as floats, or nullptr on failure. +// The data stays valid until the method runs again. +const float* run(EmbeddedModule& module, const char* name, const std::vector& inputs) { + Result> outputs = module.execute(name, inputs); + if (!outputs.ok()) { + printf("%s: execute failed (err=%u)\n", name, static_cast(outputs.error())); + return nullptr; + } + return outputs->at(0).toTensor().const_data_ptr(); +} + +// v = dit_step(g_z, g_c) +bool dit_step(EmbeddedModule& module, float* v, Timing& tm) { + uint32_t t0 = ms_now(); + npu_pmu_start(); + const float* out = run(module, kDitStep, {EValue(Tensor(&g_z_impl)), EValue(Tensor(&g_c_impl))}); + if (out == nullptr) { + return false; + } + npu_pmu_stop(tm.dit_npu); + tm.dit_ms += ms_now() - t0; + tm.dit_calls++; + memcpy(v, out, kLatent * sizeof(float)); + return true; +} + +// img (HWC uint8) = decode(g_z) +bool decode(EmbeddedModule& module, uint8_t* img, Timing& tm) { + uint32_t t0 = ms_now(); + npu_pmu_start(); + const float* out = run(module, kDecode, {EValue(Tensor(&g_z_impl))}); // (1, C, H, W) in [-1, 1] + if (out == nullptr) { + return false; + } + npu_pmu_stop(tm.decode_npu); + tm.decode_ms += ms_now() - t0; + const size_t plane = PF_IMG_HW * PF_IMG_HW; + for (size_t p = 0; p < plane; ++p) { + for (size_t ch = 0; ch < PF_IMG_CH; ++ch) { + float x = out[ch * plane + p]; + x = x < -1.0f ? -1.0f : (x > 1.0f ? 1.0f : x); + img[p * PF_IMG_CH + ch] = static_cast(lrintf((x + 1.0f) * 127.5f)); + } + } + return true; +} + +// The rectified-flow Euler sampler: z1 ~ N(0, 1) at t = 1 down to t = 0, then +// decode. k_steps (8, 4, 2 or 1) strides through the PF_K_MAX schedule points. +bool generate(EmbeddedModule& module, uint32_t seed, int k_steps, int cls, float w, uint8_t* img, Timing& tm) { + memset(&tm, 0, sizeof(tm)); + uint32_t t_start = ms_now(); + if (k_steps != 1 && k_steps != 2 && k_steps != 4 && k_steps != 8) { + k_steps = 4; + } + if (cls < 0 || cls >= PF_N_COND) { + cls = PF_NULL_CLASS; + } + const bool guided = cls != PF_NULL_CLASS && w > 0.0f; + const int stride = PF_K_MAX / k_steps; + + pcg32_seed(seed); + for (size_t i = 0; i < kLatent; ++i) { + g_z[i] = gauss(); + } + + for (int i = 0; i < k_steps; ++i) { + const int k = i * stride; + const float t = pf_schedule[k]; + const float t_next = (i + 1 < k_steps) ? pf_schedule[k + stride] : 0.0f; + const float dt = t - t_next; + + memcpy(g_c, pf_cond[cls][k], sizeof(g_c)); + if (!dit_step(module, g_v, tm)) { + return false; + } + if (guided) { + memcpy(g_c, pf_cond[PF_NULL_CLASS][k], sizeof(g_c)); + if (!dit_step(module, g_vn, tm)) { + return false; + } + for (size_t j = 0; j < kLatent; ++j) { // v = v_null + w * (v_cond - v_null) + g_v[j] = g_vn[j] + w * (g_v[j] - g_vn[j]); + } + } + for (size_t j = 0; j < kLatent; ++j) { + g_z[j] -= dt * g_v[j]; + } + } + + if (!decode(module, img, tm)) { + return false; + } + tm.total_ms = ms_now() - t_start; +#ifdef APP_DISPLAY + board_display_image(img, PF_IMG_HW, PF_IMG_HW, PF_IMG_CH); +#endif + return true; +} + +// 32x16 characters from the luminance of 4x8 pixel blocks. +void ascii_preview(const uint8_t* img) { + static const char ramp[] = " .:-=+*#%@"; + const int cols = 32, rows = 16; + const int bw = PF_IMG_HW / cols, bh = PF_IMG_HW / rows; + for (int r = 0; r < rows; ++r) { + char line[cols + 1]; + for (int c = 0; c < cols; ++c) { + uint32_t sum = 0; + for (int y = r * bh; y < (r + 1) * bh; ++y) { + for (int x = c * bw; x < (c + 1) * bw; ++x) { + const uint8_t* px = img + (y * PF_IMG_HW + x) * PF_IMG_CH; + sum += PF_IMG_CH == 3 ? (299u * px[0] + 587u * px[1] + 114u * px[2]) / 1000u : px[0]; + } + } + unsigned lum = sum / (bw * bh); + line[c] = ramp[(lum * (sizeof(ramp) - 2)) / 255u]; + } + line[cols] = 0; + printf(" |%s|\n", line); + } +} + +void print_npu(const char* name, const NpuCounters& c, uint32_t calls, uint64_t macs_per_call) { + if (c.cycles == 0) { + return; + } + const uint64_t macs = macs_per_call * calls; + // 16-byte AXI beats on the Ethos-U85 + const unsigned kb0 = static_cast(c.axi0_read_beats * 16 / 1024); + const unsigned kb1 = static_cast(c.axi1_read_beats * 16 / 1024); + printf(" %-9s NPU %u kcycles, active %u%%, MAC active %u%%, %u MAC/cycle, " + "read %u kB on AXI0 + %u kB on AXI1\n", + name, static_cast(c.cycles / 1000), static_cast(c.active * 100 / c.cycles), + static_cast(c.mac_active * 100 / c.cycles), static_cast(macs / c.cycles), kb0, kb1); +} + +void print_timing(const Timing& tm) { + printf(" dit_step: %u call(s), %u ms total (%u ms each)\n", static_cast(tm.dit_calls), + static_cast(tm.dit_ms), + static_cast(tm.dit_calls ? tm.dit_ms / tm.dit_calls : 0)); + printf(" decode: %u ms\n", static_cast(tm.decode_ms)); + printf(" total: %u ms at %u MHz (wall clock; not meaningful on the FVP)\n", + static_cast(tm.total_ms), static_cast(SystemCoreClock / 1000000u)); + print_npu("dit_step:", tm.dit_npu, tm.dit_calls, PF_MACS_DIT_STEP); + print_npu("decode:", tm.decode_npu, 1, PF_MACS_DECODE); +} + +#if defined(APP_INTERACTIVE) || defined(APP_BUTTONS) +// --------------------------------------------------------------------------- +// After the boot demo (board layers that define APP_INTERACTIVE or APP_BUTTONS) + +// Raw output: the image frames bypass stdio's text handling. +void uart_write(const void* data, size_t n) { + fflush(stdout); + const uint8_t* p = static_cast(data); + for (size_t i = 0; i < n; ++i) { + stdout_putchar(p[i]); + } +} + +void put_u32(uint32_t v) { + uint8_t b[4] = {static_cast(v), static_cast(v >> 8), + static_cast(v >> 16), static_cast(v >> 24)}; + uart_write(b, 4); +} + +void put_u16(uint16_t v) { + uint8_t b[2] = {static_cast(v), static_cast(v >> 8)}; + uart_write(b, 2); +} + +void send_frame(uint32_t seed, int cls, const uint8_t* img, uint32_t gen_ms) { + uart_write("RFI2", 4); + put_u32(seed); + put_u16(PF_IMG_HW); + put_u16(PF_IMG_HW); + put_u16(PF_IMG_CH); + put_u16(static_cast(cls)); + uart_write(img, kImage); + put_u32(crc32(img, kImage)); + put_u32(gen_ms); +} + +// pico-faces' firmware conventions: class defaults to seed % PF_N_COND, and +// without class and w the guidance cycles through {plain, pf_cfg_w...}. +float default_w(uint32_t seed) { + const int w_idx = static_cast(seed % (PF_N_CFG_W + 1)) - 1; + return w_idx >= 0 ? pf_cfg_w[w_idx] : 0.0f; +} + +#ifdef APP_BUTTONS +// Every joystick press picks the next seed, with class and guidance as for a +// bare "G ". +uint32_t g_next_seed = APP_DEMO_SEED + 1; +uint32_t g_button_images = 0; +bool g_continuous = false; + +void generate_next(EmbeddedModule& module) { + const uint32_t seed = g_next_seed++; + const int cls = static_cast(seed % PF_N_COND); + const float w = default_w(seed); + Timing tm; + if (!generate(module, seed, APP_DEMO_STEPS, cls, w, g_img, tm)) { + printf("ERR generate\n"); + return; + } + g_button_images++; + printf("Image %u: seed %u, class %d, w %.1f, %u ms%s\n", static_cast(g_button_images), + static_cast(seed), cls, static_cast(w), static_cast(tm.total_ms), + g_continuous ? " (continuous)" : ""); +} +#endif + +// A console character without blocking when the board layer offers a poll +// (the retarget's stdin_getchar() waits for one, which would stall the joystick). +int console_getchar() { +#ifdef APP_BUTTONS + return board_console_poll(); +#else + return stdin_getchar(); +#endif +} + +// "G [k_steps] [class] [w]": generate and send one frame. +void serve_request(EmbeddedModule& module, const char* line) { + char *e1, *e2, *e3, *e4; + uint32_t seed = static_cast(strtoul(line + 1, &e1, 0)); + int k_steps = static_cast(strtol(e1, &e2, 0)); + if (!k_steps) { + k_steps = 4; + } + long cv = strtol(e2, &e3, 0); + int cls = (e3 != e2) ? static_cast(cv) : static_cast(seed % PF_N_COND); + float w = 0.0f; + long wv = strtol(e3, &e4, 0); + if (e4 != e3) { + w = static_cast(wv); + } else if (e3 == e2) { + w = default_w(seed); + } + Timing tm; + if (!generate(module, seed, k_steps, cls, w, g_img, tm)) { + printf("ERR generate\n"); + return; + } + if (cls < 0 || cls >= PF_N_COND) { + cls = PF_NULL_CLASS; + } + // Timing as text before the binary frame; the viewer syncs on the magic. + printf("Generated: seed %u, %u steps, class %u, w %.1f\n", static_cast(seed), + static_cast(k_steps), static_cast(cls), static_cast(w)); + print_timing(tm); + send_frame(seed, cls, g_img, tm.total_ms); +} + +// Main loop after the boot demo: the serial protocol (APP_INTERACTIVE) and the +// SW2 joystick (APP_BUTTONS: left = one new image, right = start or stop +// continuous generation). +[[noreturn]] void serve(EmbeddedModule& module) { +#ifdef APP_INTERACTIVE + printf("Interactive: send \"G [k_steps] [class] [w]\" (viewer/view_serial.py) or \"I\"\n"); +#endif +#ifdef APP_BUTTONS + printf("Joystick: left = one new image, right = start/stop continuous generation\n"); + (void)board_buttons(); // drop presses latched during boot +#endif + fflush(stdout); + char line[64]; + int n = 0; + for (;;) { +#ifdef APP_BUTTONS + const unsigned pressed = board_buttons(); + if (pressed & kButtonRight) { + g_continuous = !g_continuous; + printf("Continuous generation %s\n", g_continuous ? "started" : "stopped"); + } + if ((pressed & kButtonLeft) || g_continuous) { + generate_next(module); + } +#endif + int ch = console_getchar(); + if (ch < 0) { + continue; + } + if (ch != '\n' && ch != '\r') { + if (n < static_cast(sizeof line) - 1) { + line[n++] = static_cast(ch); + } + continue; + } + line[n] = 0; + n = 0; +#ifdef APP_INTERACTIVE + if (line[0] == 'G') { + serve_request(module, line); + } else if (line[0] == 'I') { + printf("pico-faces-executorch %s %s K=%u latent=%ux%ux%u img=%ux%ux%u cond=%u pte=%lu\n", + PF_VARIANT, PF_QUANT, static_cast(PF_K_MAX), PF_LATENT_CH, PF_LATENT_HW, + PF_LATENT_HW, PF_IMG_HW, PF_IMG_HW, PF_IMG_CH, static_cast(PF_N_COND), + model_pte_size); + fflush(stdout); + } +#endif + } +} +#endif + } // namespace +extern "C" void SysTick_Handler(void) { g_ms_ticks++; } + +// ExecuTorch's log sink (the runtime's default prints nothing): with +// ET_LOG_ENABLED the runtime's error messages reach the console, e.g. why +// load_method failed. +extern "C" void et_pal_emit_log_message(et_timestamp_t, et_pal_log_level_t level, const char* filename, + const char*, size_t line, const char* message, size_t) { + printf("[ET %c] %s:%u %s\n", static_cast(level), filename, static_cast(line), message); +} + extern "C" int app_main(void) { executorch::runtime::runtime_init(); + ticks_init(); + crc32_init(); - printf("ExecuTorch Ethos-U85 example: %lu byte model\n", model_pte_size); + printf("ExecuTorch pico-faces (%s, %s): %lu byte program\n", PF_VARIANT, PF_QUANT, model_pte_size); - EmbeddedModule module( + static EmbeddedModule module( model_pte, model_pte_size, std::make_unique(model_pte, model_pte_size), std::make_unique(kMethodPoolSize, g_method_pool), std::make_unique(kTempPoolSize, g_temp_pool)); - // TinyCNN takes one 16x16 RGB image in NHWC order (see model/model.py), - // filled here with a deterministic ramp. The tensor only wraps the buffer; - // no tensor extension (and its std::random_device) is needed for that. - alignas(16) static float input_data[16 * 16 * 3]; - for (size_t i = 0; i < sizeof(input_data) / sizeof(input_data[0]); ++i) { - input_data[i] = static_cast(i % 32) / 32.0f - 0.5f; - } - std::array sizes{1, 16, 16, 3}; - std::array dim_order{0, 1, 2, 3}; - TensorImpl input_impl(ScalarType::Float, sizes.size(), sizes.data(), input_data, dim_order.data()); - Tensor input(&input_impl); - - auto outputs = module.forward(input); - if (!outputs.ok()) { - printf("forward failed (err=%u)\n", static_cast(outputs.error())); - return 1; - } - if (outputs->empty()) { - printf("forward returned no outputs\n"); + printf("Methods:\n"); + if (!load_method(module, kDitStep) || !load_method(module, kDecode)) { return 1; } - - const EValue& out = outputs->front(); - if (out.isTensor()) { - Tensor t = out.toTensor(); - printf("Output: %u element(s):", static_cast(t.numel())); - if (t.scalar_type() == ScalarType::Float) { - const float* p = t.const_data_ptr(); - for (size_t i = 0; i < t.numel(); ++i) { - printf(" %.4f", p[i]); - } + { + MethodMeta dit = module.method_meta(kDitStep).get(); + MethodMeta dec = module.method_meta(kDecode).get(); + if (!check_shape(dit.input_tensor_meta(0).get(), "dit_step input z", {1, PF_LATENT_CH, PF_LATENT_HW, PF_LATENT_HW}) || + !check_shape(dit.input_tensor_meta(1).get(), "dit_step input c", {1, PF_COND_DIM}) || + !check_shape(dit.output_tensor_meta(0).get(), "dit_step output v", {1, PF_LATENT_CH, PF_LATENT_HW, PF_LATENT_HW}) || + !check_shape(dec.input_tensor_meta(0).get(), "decode input z", {1, PF_LATENT_CH, PF_LATENT_HW, PF_LATENT_HW}) || + !check_shape(dec.output_tensor_meta(0).get(), "decode output img", {1, PF_IMG_CH, PF_IMG_HW, PF_IMG_HW})) { + return 1; } - printf("\n"); } + // Boot demo: one image with fixed parameters. The CRC identifies the image: + // the same program gives the same CRC on every run and on the FVP. + Timing tm; + printf("Generating: seed %u, %u steps, class %u, w %.1f\n", static_cast(APP_DEMO_SEED), + static_cast(APP_DEMO_STEPS), static_cast(APP_DEMO_CLASS), + static_cast(APP_DEMO_W)); + fflush(stdout); + if (!generate(module, APP_DEMO_SEED, APP_DEMO_STEPS, APP_DEMO_CLASS, APP_DEMO_W, g_img, tm)) { + return 1; + } + print_timing(tm); + printf("Image: %ux%ux%u, CRC32 %08x\n", PF_IMG_HW, PF_IMG_HW, PF_IMG_CH, + static_cast(crc32(g_img, kImage))); + ascii_preview(g_img); +#ifdef APP_RESULT_DIR + // Simulation: hand the image and the measurements to the host through + // semihosting (model/verify_export.py --compare reads the image). + { + static char text[256]; + int n = snprintf(text, sizeof(text), + "seed %u steps %u class %u w %.1f crc32 %08x dit_cycles %u decode_cycles %u\n", + static_cast(APP_DEMO_SEED), static_cast(APP_DEMO_STEPS), + static_cast(APP_DEMO_CLASS), static_cast(APP_DEMO_W), + static_cast(crc32(g_img, kImage)), static_cast(tm.dit_npu.cycles), + static_cast(tm.decode_npu.cycles)); + bool ok = board_save_file(APP_RESULT_DIR "/fvp_image.bin", g_img, kImage) == 0 && + board_save_file(APP_RESULT_DIR "/fvp_result.txt", text, n > 0 ? static_cast(n) : 0) == 0; + printf("Result files in " APP_RESULT_DIR ": %s\n", ok ? "written" : "FAILED"); + } +#endif printf("Test_result: PASS\n"); - printf("\x04"); // EOT: ends the FVP run (semihosting exit); a board just sees a 0x04 + printf("\x04"); // EOT: the end marker for a console log fflush(stdout); + +#if defined(APP_INTERACTIVE) || defined(APP_BUTTONS) + serve(module); +#endif return 0; } diff --git a/vcpkg-configuration.json b/vcpkg-configuration.json index e9340040..45b31104 100644 --- a/vcpkg-configuration.json +++ b/vcpkg-configuration.json @@ -8,9 +8,9 @@ ], "requires": { "arm:tools/open-cmsis-pack/cmsis-toolbox": "2.15.0", - "arm:compilers/arm/arm-none-eabi-gcc": "14.3.1", - "arm:compilers/arm/llvm-embedded": "22.1.0", - "arm:tools/kitware/cmake": "4.2.1", + "arm:compilers/arm/arm-none-eabi-gcc": "15.3.1", + "arm:compilers/arm/llvm-embedded": "23.1.0", + "arm:tools/kitware/cmake": "4.3.3", "arm:tools/ninja-build/ninja": "1.13.2", "arm:models/arm/avh-fvp": "11.32.23", "arm:compilers/arm/armclang": "6.24.0"